1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Intel CPU Microcode Update Driver for Linux
5 * Copyright (C) 2000-2006 Tigran Aivazian <aivazian.tigran@gmail.com>
6 * 2006 Shaohua Li <shaohua.li@intel.com>
8 * Intel CPU microcode early update for Linux
10 * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com>
11 * H Peter Anvin" <hpa@zytor.com>
15 * This needs to be before all headers so that pr_debug in printk.h doesn't turn
16 * printk calls into no_printk().
20 #define pr_fmt(fmt) "microcode: " fmt
22 #include <linux/earlycpio.h>
23 #include <linux/firmware.h>
24 #include <linux/uaccess.h>
25 #include <linux/vmalloc.h>
26 #include <linux/initrd.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/cpu.h>
30 #include <linux/uio.h>
33 #include <asm/microcode_intel.h>
34 #include <asm/intel-family.h>
35 #include <asm/processor.h>
36 #include <asm/tlbflush.h>
37 #include <asm/setup.h>
40 static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin";
42 /* Current microcode patch used in early patching on the APs. */
43 static struct microcode_intel *intel_ucode_patch;
45 /* last level cache size per core */
46 static int llc_size_per_core;
48 static inline bool cpu_signatures_match(unsigned int s1, unsigned int p1,
49 unsigned int s2, unsigned int p2)
54 /* Processor flags are either both 0 ... */
58 /* ... or they intersect. */
63 * Returns 1 if update has been found, 0 otherwise.
65 static int find_matching_signature(void *mc, unsigned int csig, int cpf)
67 struct microcode_header_intel *mc_hdr = mc;
68 struct extended_sigtable *ext_hdr;
69 struct extended_signature *ext_sig;
72 if (cpu_signatures_match(csig, cpf, mc_hdr->sig, mc_hdr->pf))
75 /* Look for ext. headers: */
76 if (get_totalsize(mc_hdr) <= get_datasize(mc_hdr) + MC_HEADER_SIZE)
79 ext_hdr = mc + get_datasize(mc_hdr) + MC_HEADER_SIZE;
80 ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE;
82 for (i = 0; i < ext_hdr->count; i++) {
83 if (cpu_signatures_match(csig, cpf, ext_sig->sig, ext_sig->pf))
91 * Returns 1 if update has been found, 0 otherwise.
93 static int has_newer_microcode(void *mc, unsigned int csig, int cpf, int new_rev)
95 struct microcode_header_intel *mc_hdr = mc;
97 if (mc_hdr->rev <= new_rev)
100 return find_matching_signature(mc, csig, cpf);
104 * Given CPU signature and a microcode patch, this function finds if the
105 * microcode patch has matching family and model with the CPU.
107 * %true - if there's a match
110 static bool microcode_matches(struct microcode_header_intel *mc_header,
113 unsigned long total_size = get_totalsize(mc_header);
114 unsigned long data_size = get_datasize(mc_header);
115 struct extended_sigtable *ext_header;
116 unsigned int fam_ucode, model_ucode;
117 struct extended_signature *ext_sig;
118 unsigned int fam, model;
121 fam = x86_family(sig);
122 model = x86_model(sig);
124 fam_ucode = x86_family(mc_header->sig);
125 model_ucode = x86_model(mc_header->sig);
127 if (fam == fam_ucode && model == model_ucode)
130 /* Look for ext. headers: */
131 if (total_size <= data_size + MC_HEADER_SIZE)
134 ext_header = (void *) mc_header + data_size + MC_HEADER_SIZE;
135 ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
136 ext_sigcount = ext_header->count;
138 for (i = 0; i < ext_sigcount; i++) {
139 fam_ucode = x86_family(ext_sig->sig);
140 model_ucode = x86_model(ext_sig->sig);
142 if (fam == fam_ucode && model == model_ucode)
150 static struct ucode_patch *memdup_patch(void *data, unsigned int size)
152 struct ucode_patch *p;
154 p = kzalloc(sizeof(struct ucode_patch), GFP_KERNEL);
158 p->data = kmemdup(data, size, GFP_KERNEL);
167 static void save_microcode_patch(void *data, unsigned int size)
169 struct microcode_header_intel *mc_hdr, *mc_saved_hdr;
170 struct ucode_patch *iter, *tmp, *p = NULL;
171 bool prev_found = false;
172 unsigned int sig, pf;
174 mc_hdr = (struct microcode_header_intel *)data;
176 list_for_each_entry_safe(iter, tmp, µcode_cache, plist) {
177 mc_saved_hdr = (struct microcode_header_intel *)iter->data;
178 sig = mc_saved_hdr->sig;
179 pf = mc_saved_hdr->pf;
181 if (find_matching_signature(data, sig, pf)) {
184 if (mc_hdr->rev <= mc_saved_hdr->rev)
187 p = memdup_patch(data, size);
189 pr_err("Error allocating buffer %p\n", data);
191 list_replace(&iter->plist, &p->plist);
199 * There weren't any previous patches found in the list cache; save the
203 p = memdup_patch(data, size);
205 pr_err("Error allocating buffer for %p\n", data);
207 list_add_tail(&p->plist, µcode_cache);
214 * Save for early loading. On 32-bit, that needs to be a physical
215 * address as the APs are running from physical addresses, before
216 * paging has been enabled.
218 if (IS_ENABLED(CONFIG_X86_32))
219 intel_ucode_patch = (struct microcode_intel *)__pa_nodebug(p->data);
221 intel_ucode_patch = p->data;
224 static int microcode_sanity_check(void *mc, int print_err)
226 unsigned long total_size, data_size, ext_table_size;
227 struct microcode_header_intel *mc_header = mc;
228 struct extended_sigtable *ext_header = NULL;
229 u32 sum, orig_sum, ext_sigcount = 0, i;
230 struct extended_signature *ext_sig;
232 total_size = get_totalsize(mc_header);
233 data_size = get_datasize(mc_header);
235 if (data_size + MC_HEADER_SIZE > total_size) {
237 pr_err("Error: bad microcode data file size.\n");
241 if (mc_header->ldrver != 1 || mc_header->hdrver != 1) {
243 pr_err("Error: invalid/unknown microcode update format.\n");
247 ext_table_size = total_size - (MC_HEADER_SIZE + data_size);
248 if (ext_table_size) {
249 u32 ext_table_sum = 0;
252 if ((ext_table_size < EXT_HEADER_SIZE)
253 || ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) {
255 pr_err("Error: truncated extended signature table.\n");
259 ext_header = mc + MC_HEADER_SIZE + data_size;
260 if (ext_table_size != exttable_size(ext_header)) {
262 pr_err("Error: extended signature table size mismatch.\n");
266 ext_sigcount = ext_header->count;
269 * Check extended table checksum: the sum of all dwords that
270 * comprise a valid table must be 0.
272 ext_tablep = (u32 *)ext_header;
274 i = ext_table_size / sizeof(u32);
276 ext_table_sum += ext_tablep[i];
280 pr_warn("Bad extended signature table checksum, aborting.\n");
286 * Calculate the checksum of update data and header. The checksum of
287 * valid update data and header including the extended signature table
291 i = (MC_HEADER_SIZE + data_size) / sizeof(u32);
293 orig_sum += ((u32 *)mc)[i];
297 pr_err("Bad microcode data checksum, aborting.\n");
305 * Check extended signature checksum: 0 => valid.
307 for (i = 0; i < ext_sigcount; i++) {
308 ext_sig = (void *)ext_header + EXT_HEADER_SIZE +
309 EXT_SIGNATURE_SIZE * i;
311 sum = (mc_header->sig + mc_header->pf + mc_header->cksum) -
312 (ext_sig->sig + ext_sig->pf + ext_sig->cksum);
315 pr_err("Bad extended signature checksum, aborting.\n");
323 * Get microcode matching with BSP's model. Only CPUs with the same model as
324 * BSP can stay in the platform.
326 static struct microcode_intel *
327 scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save)
329 struct microcode_header_intel *mc_header;
330 struct microcode_intel *patch = NULL;
331 unsigned int mc_size;
334 if (size < sizeof(struct microcode_header_intel))
337 mc_header = (struct microcode_header_intel *)data;
339 mc_size = get_totalsize(mc_header);
342 microcode_sanity_check(data, 0) < 0)
347 if (!microcode_matches(mc_header, uci->cpu_sig.sig)) {
353 save_microcode_patch(data, mc_size);
359 if (!has_newer_microcode(data,
366 struct microcode_header_intel *phdr = &patch->hdr;
368 if (!has_newer_microcode(data,
375 /* We have a newer patch, save it. */
388 static int collect_cpu_info_early(struct ucode_cpu_info *uci)
391 unsigned int family, model;
392 struct cpu_signature csig = { 0 };
393 unsigned int eax, ebx, ecx, edx;
395 memset(uci, 0, sizeof(*uci));
399 native_cpuid(&eax, &ebx, &ecx, &edx);
402 family = x86_family(eax);
403 model = x86_model(eax);
405 if ((model >= 5) || (family > 6)) {
406 /* get processor flags from MSR 0x17 */
407 native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
408 csig.pf = 1 << ((val[1] >> 18) & 7);
411 csig.rev = intel_get_microcode_revision();
419 static void show_saved_mc(void)
423 unsigned int sig, pf, rev, total_size, data_size, date;
424 struct ucode_cpu_info uci;
425 struct ucode_patch *p;
427 if (list_empty(µcode_cache)) {
428 pr_debug("no microcode data saved.\n");
432 collect_cpu_info_early(&uci);
434 sig = uci.cpu_sig.sig;
436 rev = uci.cpu_sig.rev;
437 pr_debug("CPU: sig=0x%x, pf=0x%x, rev=0x%x\n", sig, pf, rev);
439 list_for_each_entry(p, µcode_cache, plist) {
440 struct microcode_header_intel *mc_saved_header;
441 struct extended_sigtable *ext_header;
442 struct extended_signature *ext_sig;
445 mc_saved_header = (struct microcode_header_intel *)p->data;
447 sig = mc_saved_header->sig;
448 pf = mc_saved_header->pf;
449 rev = mc_saved_header->rev;
450 date = mc_saved_header->date;
452 total_size = get_totalsize(mc_saved_header);
453 data_size = get_datasize(mc_saved_header);
455 pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n",
456 i++, sig, pf, rev, total_size,
459 (date >> 16) & 0xff);
461 /* Look for ext. headers: */
462 if (total_size <= data_size + MC_HEADER_SIZE)
465 ext_header = (void *)mc_saved_header + data_size + MC_HEADER_SIZE;
466 ext_sigcount = ext_header->count;
467 ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
469 for (j = 0; j < ext_sigcount; j++) {
473 pr_debug("\tExtended[%d]: sig=0x%x, pf=0x%x\n",
483 * Save this microcode patch. It will be loaded early when a CPU is
484 * hot-added or resumes.
486 static void save_mc_for_early(u8 *mc, unsigned int size)
488 /* Synchronization during CPU hotplug. */
489 static DEFINE_MUTEX(x86_cpu_microcode_mutex);
491 mutex_lock(&x86_cpu_microcode_mutex);
493 save_microcode_patch(mc, size);
496 mutex_unlock(&x86_cpu_microcode_mutex);
499 static bool load_builtin_intel_microcode(struct cpio_data *cp)
501 unsigned int eax = 1, ebx, ecx = 0, edx;
504 if (IS_ENABLED(CONFIG_X86_32))
507 native_cpuid(&eax, &ebx, &ecx, &edx);
509 sprintf(name, "intel-ucode/%02x-%02x-%02x",
510 x86_family(eax), x86_model(eax), x86_stepping(eax));
512 return get_builtin_firmware(cp, name);
516 * Print ucode update info.
519 print_ucode_info(struct ucode_cpu_info *uci, unsigned int date)
521 pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n",
525 (date >> 16) & 0xff);
530 static int delay_ucode_info;
531 static int current_mc_date;
534 * Print early updated ucode info after printk works. This is delayed info dump.
536 void show_ucode_info_early(void)
538 struct ucode_cpu_info uci;
540 if (delay_ucode_info) {
541 collect_cpu_info_early(&uci);
542 print_ucode_info(&uci, current_mc_date);
543 delay_ucode_info = 0;
548 * At this point, we can not call printk() yet. Delay printing microcode info in
549 * show_ucode_info_early() until printk() works.
551 static void print_ucode(struct ucode_cpu_info *uci)
553 struct microcode_intel *mc;
554 int *delay_ucode_info_p;
555 int *current_mc_date_p;
561 delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info);
562 current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date);
564 *delay_ucode_info_p = 1;
565 *current_mc_date_p = mc->hdr.date;
569 static inline void print_ucode(struct ucode_cpu_info *uci)
571 struct microcode_intel *mc;
577 print_ucode_info(uci, mc->hdr.date);
581 static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
583 struct microcode_intel *mc;
591 * Save us the MSR write below - which is a particular expensive
592 * operation - when the other hyperthread has updated the microcode
595 rev = intel_get_microcode_revision();
596 if (rev >= mc->hdr.rev) {
597 uci->cpu_sig.rev = rev;
602 * Writeback and invalidate caches before updating microcode to avoid
603 * internal issues depending on what the microcode is updating.
607 /* write microcode via MSR 0x79 */
608 native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
610 rev = intel_get_microcode_revision();
611 if (rev != mc->hdr.rev)
614 uci->cpu_sig.rev = rev;
619 print_ucode_info(uci, mc->hdr.date);
624 int __init save_microcode_in_initrd_intel(void)
626 struct ucode_cpu_info uci;
630 * initrd is going away, clear patch ptr. We will scan the microcode one
631 * last time before jettisoning and save a patch, if found. Then we will
632 * update that pointer too, with a stable patch address to use when
633 * resuming the cores.
635 intel_ucode_patch = NULL;
637 if (!load_builtin_intel_microcode(&cp))
638 cp = find_microcode_in_initrd(ucode_path, false);
640 if (!(cp.data && cp.size))
643 collect_cpu_info_early(&uci);
645 scan_microcode(cp.data, cp.size, &uci, true);
653 * @res_patch, output: a pointer to the patch we found.
655 static struct microcode_intel *__load_ucode_intel(struct ucode_cpu_info *uci)
657 static const char *path;
661 if (IS_ENABLED(CONFIG_X86_32)) {
662 path = (const char *)__pa_nodebug(ucode_path);
669 /* try built-in microcode first */
670 if (!load_builtin_intel_microcode(&cp))
671 cp = find_microcode_in_initrd(path, use_pa);
673 if (!(cp.data && cp.size))
676 collect_cpu_info_early(uci);
678 return scan_microcode(cp.data, cp.size, uci, false);
681 void __init load_ucode_intel_bsp(void)
683 struct microcode_intel *patch;
684 struct ucode_cpu_info uci;
686 patch = __load_ucode_intel(&uci);
692 apply_microcode_early(&uci, true);
695 void load_ucode_intel_ap(void)
697 struct microcode_intel *patch, **iup;
698 struct ucode_cpu_info uci;
700 if (IS_ENABLED(CONFIG_X86_32))
701 iup = (struct microcode_intel **) __pa_nodebug(&intel_ucode_patch);
703 iup = &intel_ucode_patch;
707 patch = __load_ucode_intel(&uci);
716 if (apply_microcode_early(&uci, true)) {
717 /* Mixed-silicon system? Try to refetch the proper patch: */
724 static struct microcode_intel *find_patch(struct ucode_cpu_info *uci)
726 struct microcode_header_intel *phdr;
727 struct ucode_patch *iter, *tmp;
729 list_for_each_entry_safe(iter, tmp, µcode_cache, plist) {
731 phdr = (struct microcode_header_intel *)iter->data;
733 if (phdr->rev <= uci->cpu_sig.rev)
736 if (!find_matching_signature(phdr,
746 void reload_ucode_intel(void)
748 struct microcode_intel *p;
749 struct ucode_cpu_info uci;
751 collect_cpu_info_early(&uci);
753 p = find_patch(&uci);
759 apply_microcode_early(&uci, false);
762 static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
764 static struct cpu_signature prev;
765 struct cpuinfo_x86 *c = &cpu_data(cpu_num);
768 memset(csig, 0, sizeof(*csig));
770 csig->sig = cpuid_eax(0x00000001);
772 if ((c->x86_model >= 5) || (c->x86 > 6)) {
773 /* get processor flags from MSR 0x17 */
774 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
775 csig->pf = 1 << ((val[1] >> 18) & 7);
778 csig->rev = c->microcode;
780 /* No extra locking on prev, races are harmless. */
781 if (csig->sig != prev.sig || csig->pf != prev.pf || csig->rev != prev.rev) {
782 pr_info("sig=0x%x, pf=0x%x, revision=0x%x\n",
783 csig->sig, csig->pf, csig->rev);
790 static enum ucode_state apply_microcode_intel(int cpu)
792 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
793 struct cpuinfo_x86 *c = &cpu_data(cpu);
794 struct microcode_intel *mc;
795 enum ucode_state ret;
799 /* We should bind the task to the CPU */
800 if (WARN_ON(raw_smp_processor_id() != cpu))
803 /* Look for a newer patch in our cache: */
804 mc = find_patch(uci);
812 * Save us the MSR write below - which is a particular expensive
813 * operation - when the other hyperthread has updated the microcode
816 rev = intel_get_microcode_revision();
817 if (rev >= mc->hdr.rev) {
823 * Writeback and invalidate caches before updating microcode to avoid
824 * internal issues depending on what the microcode is updating.
828 /* write microcode via MSR 0x79 */
829 wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
831 rev = intel_get_microcode_revision();
833 if (rev != mc->hdr.rev) {
834 pr_err("CPU%d update to revision 0x%x failed\n",
839 if (rev != prev_rev) {
840 pr_info("updated to revision 0x%x, date = %04x-%02x-%02x\n",
842 mc->hdr.date & 0xffff,
844 (mc->hdr.date >> 16) & 0xff);
851 uci->cpu_sig.rev = rev;
854 /* Update boot_cpu_data's revision too, if we're on the BSP: */
855 if (c->cpu_index == boot_cpu_data.cpu_index)
856 boot_cpu_data.microcode = rev;
861 static enum ucode_state generic_load_microcode(int cpu, struct iov_iter *iter)
863 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
864 unsigned int curr_mc_size = 0, new_mc_size = 0;
865 enum ucode_state ret = UCODE_OK;
866 int new_rev = uci->cpu_sig.rev;
867 u8 *new_mc = NULL, *mc = NULL;
868 unsigned int csig, cpf;
870 while (iov_iter_count(iter)) {
871 struct microcode_header_intel mc_header;
872 unsigned int mc_size, data_size;
875 if (!copy_from_iter_full(&mc_header, sizeof(mc_header), iter)) {
876 pr_err("error! Truncated or inaccessible header in microcode data file\n");
880 mc_size = get_totalsize(&mc_header);
881 if (mc_size < sizeof(mc_header)) {
882 pr_err("error! Bad data in microcode data file (totalsize too small)\n");
885 data_size = mc_size - sizeof(mc_header);
886 if (data_size > iov_iter_count(iter)) {
887 pr_err("error! Bad data in microcode data file (truncated file?)\n");
891 /* For performance reasons, reuse mc area when possible */
892 if (!mc || mc_size > curr_mc_size) {
894 mc = vmalloc(mc_size);
897 curr_mc_size = mc_size;
900 memcpy(mc, &mc_header, sizeof(mc_header));
901 data = mc + sizeof(mc_header);
902 if (!copy_from_iter_full(data, data_size, iter) ||
903 microcode_sanity_check(mc, 1) < 0) {
907 csig = uci->cpu_sig.sig;
908 cpf = uci->cpu_sig.pf;
909 if (has_newer_microcode(mc, csig, cpf, new_rev)) {
911 new_rev = mc_header.rev;
913 new_mc_size = mc_size;
914 mc = NULL; /* trigger new vmalloc */
921 if (iov_iter_count(iter)) {
930 uci->mc = (struct microcode_intel *)new_mc;
933 * If early loading microcode is supported, save this mc into
934 * permanent memory. So it will be loaded early when a CPU is hot added
937 save_mc_for_early(new_mc, new_mc_size);
939 pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
940 cpu, new_rev, uci->cpu_sig.rev);
945 static bool is_blacklisted(unsigned int cpu)
947 struct cpuinfo_x86 *c = &cpu_data(cpu);
950 * Late loading on model 79 with microcode revision less than 0x0b000021
951 * and LLC size per core bigger than 2.5MB may result in a system hang.
952 * This behavior is documented in item BDF90, #334165 (Intel Xeon
953 * Processor E7-8800/4800 v4 Product Family).
956 c->x86_model == INTEL_FAM6_BROADWELL_X &&
957 c->x86_stepping == 0x01 &&
958 llc_size_per_core > 2621440 &&
959 c->microcode < 0x0b000021) {
960 pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);
961 pr_err_once("Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
968 static enum ucode_state request_microcode_fw(int cpu, struct device *device,
971 struct cpuinfo_x86 *c = &cpu_data(cpu);
972 const struct firmware *firmware;
973 struct iov_iter iter;
974 enum ucode_state ret;
978 if (is_blacklisted(cpu))
981 sprintf(name, "intel-ucode/%02x-%02x-%02x",
982 c->x86, c->x86_model, c->x86_stepping);
984 if (request_firmware_direct(&firmware, name, device)) {
985 pr_debug("data file %s load failed\n", name);
989 kvec.iov_base = (void *)firmware->data;
990 kvec.iov_len = firmware->size;
991 iov_iter_kvec(&iter, WRITE, &kvec, 1, firmware->size);
992 ret = generic_load_microcode(cpu, &iter);
994 release_firmware(firmware);
999 static enum ucode_state
1000 request_microcode_user(int cpu, const void __user *buf, size_t size)
1002 struct iov_iter iter;
1005 if (is_blacklisted(cpu))
1006 return UCODE_NFOUND;
1008 iov.iov_base = (void __user *)buf;
1010 iov_iter_init(&iter, WRITE, &iov, 1, size);
1012 return generic_load_microcode(cpu, &iter);
1015 static struct microcode_ops microcode_intel_ops = {
1016 .request_microcode_user = request_microcode_user,
1017 .request_microcode_fw = request_microcode_fw,
1018 .collect_cpu_info = collect_cpu_info,
1019 .apply_microcode = apply_microcode_intel,
1022 static int __init calc_llc_size_per_core(struct cpuinfo_x86 *c)
1024 u64 llc_size = c->x86_cache_size * 1024ULL;
1026 do_div(llc_size, c->x86_max_cores);
1028 return (int)llc_size;
1031 struct microcode_ops * __init init_intel_microcode(void)
1033 struct cpuinfo_x86 *c = &boot_cpu_data;
1035 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
1036 cpu_has(c, X86_FEATURE_IA64)) {
1037 pr_err("Intel CPU family 0x%x not supported\n", c->x86);
1041 llc_size_per_core = calc_llc_size_per_core(c);
1043 return µcode_intel_ops;