2 * AMD CPU Microcode Update Driver for Linux
4 * This driver allows to upgrade microcode on F10h AMD
7 * Copyright (C) 2008-2011 Advanced Micro Devices Inc.
9 * Author: Peter Oruba <peter.oruba@amd.com>
12 * Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
15 * Copyright (C) 2013 Advanced Micro Devices, Inc.
17 * Author: Jacob Shin <jacob.shin@amd.com>
18 * Fixes: Borislav Petkov <bp@suse.de>
20 * Licensed under the terms of the GNU General Public
21 * License version 2. See file COPYING for details.
23 #define pr_fmt(fmt) "microcode: " fmt
25 #include <linux/earlycpio.h>
26 #include <linux/firmware.h>
27 #include <linux/uaccess.h>
28 #include <linux/vmalloc.h>
29 #include <linux/initrd.h>
30 #include <linux/kernel.h>
31 #include <linux/pci.h>
33 #include <asm/microcode_amd.h>
34 #include <asm/microcode.h>
35 #include <asm/processor.h>
36 #include <asm/setup.h>
40 static struct equiv_cpu_entry *equiv_cpu_table;
43 struct list_head plist;
49 static LIST_HEAD(pcache);
52 * This points to the current valid container of microcode patches which we will
53 * save from the initrd before jettisoning its contents.
56 static size_t container_size;
57 static bool ucode_builtin;
59 static u32 ucode_new_rev;
60 static u8 amd_ucode_patch[PATCH_MAX_SIZE];
61 static u16 this_equiv_id;
63 static struct cpio_data ucode_cpio;
65 static struct cpio_data __init find_ucode_in_initrd(void)
67 #ifdef CONFIG_BLK_DEV_INITRD
73 * Microcode patch container file is prepended to the initrd in cpio
74 * format. See Documentation/x86/early-microcode.txt
76 static __initdata char ucode_path[] = "kernel/x86/microcode/AuthenticAMD.bin";
79 struct boot_params *p;
82 * On 32-bit, early load occurs before paging is turned on so we need
83 * to use physical addresses.
85 p = (struct boot_params *)__pa_nodebug(&boot_params);
86 path = (char *)__pa_nodebug(ucode_path);
87 start = (void *)p->hdr.ramdisk_image;
88 size = p->hdr.ramdisk_size;
91 start = (void *)(boot_params.hdr.ramdisk_image + PAGE_OFFSET);
92 size = boot_params.hdr.ramdisk_size;
93 #endif /* !CONFIG_X86_32 */
95 return find_cpio_data(path, start, size, NULL);
97 return (struct cpio_data){ NULL, 0, "" };
101 static size_t compute_container_size(u8 *data, u32 total_size)
104 u32 *header = (u32 *)data;
106 if (header[0] != UCODE_MAGIC ||
107 header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
108 header[2] == 0) /* size */
111 size = header[2] + CONTAINER_HDR_SZ;
118 header = (u32 *)data;
120 if (header[0] != UCODE_UCODE_TYPE)
124 * Sanity-check patch size.
126 patch_size = header[1];
127 if (patch_size > PATCH_MAX_SIZE)
130 size += patch_size + SECTION_HDR_SIZE;
131 data += patch_size + SECTION_HDR_SIZE;
132 total_size -= patch_size + SECTION_HDR_SIZE;
139 * Early load occurs before we can vmalloc(). So we look for the microcode
140 * patch container file in initrd, traverse equivalent cpu table, look for a
141 * matching microcode patch, and update, all in initrd memory in place.
142 * When vmalloc() is available for use later -- on 64-bit during first AP load,
143 * and on 32-bit during save_microcode_in_initrd_amd() -- we can call
144 * load_microcode_amd() to save equivalent cpu table and microcode patches in
145 * kernel heap memory.
147 static void apply_ucode_in_initrd(void *ucode, size_t size, bool save_patch)
149 struct equiv_cpu_entry *eq;
153 u8 (*patch)[PATCH_MAX_SIZE];
156 u32 rev, eax, ebx, ecx, edx;
160 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
161 cont_sz = (size_t *)__pa_nodebug(&container_size);
162 cont = (u8 **)__pa_nodebug(&container);
163 patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch);
165 new_rev = &ucode_new_rev;
166 cont_sz = &container_size;
168 patch = &amd_ucode_patch;
173 header = (u32 *)data;
175 /* find equiv cpu table */
176 if (header[0] != UCODE_MAGIC ||
177 header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
178 header[2] == 0) /* size */
183 native_cpuid(&eax, &ebx, &ecx, &edx);
186 eq = (struct equiv_cpu_entry *)(data + CONTAINER_HDR_SZ);
190 /* Advance past the container header */
191 offset = header[2] + CONTAINER_HDR_SZ;
195 eq_id = find_equiv_id(eq, eax);
197 this_equiv_id = eq_id;
198 *cont_sz = compute_container_size(*cont, left + offset);
201 * truncate how much we need to iterate over in the
202 * ucode update loop below
204 left = *cont_sz - offset;
209 * support multiple container files appended together. if this
210 * one does not have a matching equivalent cpu entry, we fast
211 * forward to the next container file.
214 header = (u32 *)data;
215 if (header[0] == UCODE_MAGIC &&
216 header[1] == UCODE_EQUIV_CPU_TABLE_TYPE)
219 offset = header[1] + SECTION_HDR_SIZE;
224 /* mark where the next microcode container file starts */
225 offset = data - (u8 *)ucode;
235 if (check_current_patch_level(&rev, true))
239 struct microcode_amd *mc;
241 header = (u32 *)data;
242 if (header[0] != UCODE_UCODE_TYPE || /* type */
243 header[1] == 0) /* size */
246 mc = (struct microcode_amd *)(data + SECTION_HDR_SIZE);
248 if (eq_id == mc->hdr.processor_rev_id && rev < mc->hdr.patch_id) {
250 if (!__apply_microcode_amd(mc)) {
251 rev = mc->hdr.patch_id;
256 min_t(u32, header[1], PATCH_MAX_SIZE));
260 offset = header[1] + SECTION_HDR_SIZE;
266 static bool __init load_builtin_amd_microcode(struct cpio_data *cp,
270 char fw_name[36] = "amd-ucode/microcode_amd.bin";
273 snprintf(fw_name, sizeof(fw_name),
274 "amd-ucode/microcode_amd_fam%.2xh.bin", family);
276 return get_builtin_firmware(cp, fw_name);
282 void __init load_ucode_amd_bsp(unsigned int family)
290 data = (void **)__pa_nodebug(&ucode_cpio.data);
291 size = (size_t *)__pa_nodebug(&ucode_cpio.size);
292 builtin = (bool *)__pa_nodebug(&ucode_builtin);
294 data = &ucode_cpio.data;
295 size = &ucode_cpio.size;
296 builtin = &ucode_builtin;
299 *builtin = load_builtin_amd_microcode(&cp, family);
301 cp = find_ucode_in_initrd();
303 if (!(cp.data && cp.size))
309 apply_ucode_in_initrd(cp.data, cp.size, true);
314 * On 32-bit, since AP's early load occurs before paging is turned on, we
315 * cannot traverse cpu_equiv_table and pcache in kernel heap memory. So during
316 * cold boot, AP will apply_ucode_in_initrd() just like the BSP. During
317 * save_microcode_in_initrd_amd() BSP's patch is copied to amd_ucode_patch,
318 * which is used upon resume from suspend.
320 void load_ucode_amd_ap(void)
322 struct microcode_amd *mc;
326 mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch);
327 if (mc->hdr.patch_id && mc->hdr.processor_rev_id) {
328 __apply_microcode_amd(mc);
332 ucode = (void *)__pa_nodebug(&container);
333 usize = (size_t *)__pa_nodebug(&container_size);
335 if (!*ucode || !*usize)
338 apply_ucode_in_initrd(*ucode, *usize, false);
341 static void __init collect_cpu_sig_on_bsp(void *arg)
343 unsigned int cpu = smp_processor_id();
344 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
346 uci->cpu_sig.sig = cpuid_eax(0x00000001);
349 static void __init get_bsp_sig(void)
351 unsigned int bsp = boot_cpu_data.cpu_index;
352 struct ucode_cpu_info *uci = ucode_cpu_info + bsp;
354 if (!uci->cpu_sig.sig)
355 smp_call_function_single(bsp, collect_cpu_sig_on_bsp, NULL, 1);
358 void load_ucode_amd_ap(void)
360 unsigned int cpu = smp_processor_id();
361 struct equiv_cpu_entry *eq;
362 struct microcode_amd *mc;
363 u8 *cont = container;
367 /* Exit if called on the BSP. */
375 * 64-bit runs with paging enabled, thus early==false.
377 if (check_current_patch_level(&rev, false))
380 /* Add CONFIG_RANDOMIZE_MEMORY offset. */
382 cont += PAGE_OFFSET - __PAGE_OFFSET_BASE;
384 eax = cpuid_eax(0x00000001);
385 eq = (struct equiv_cpu_entry *)(cont + CONTAINER_HDR_SZ);
387 eq_id = find_equiv_id(eq, eax);
391 if (eq_id == this_equiv_id) {
392 mc = (struct microcode_amd *)amd_ucode_patch;
394 if (mc && rev < mc->hdr.patch_id) {
395 if (!__apply_microcode_amd(mc))
396 ucode_new_rev = mc->hdr.patch_id;
400 if (!ucode_cpio.data)
404 * AP has a different equivalence ID than BSP, looks like
405 * mixed-steppings silicon so go through the ucode blob anew.
407 apply_ucode_in_initrd(ucode_cpio.data, ucode_cpio.size, false);
412 int __init save_microcode_in_initrd_amd(void)
416 enum ucode_state ret;
425 cont = (unsigned long)container;
426 cont_va = __va(container);
429 * We need the physical address of the container for both bitness since
430 * boot_params.hdr.ramdisk_image is a physical address.
432 cont = __pa(container);
437 * Take into account the fact that the ramdisk might get relocated and
438 * therefore we need to recompute the container's position in virtual
441 if (relocated_ramdisk)
442 container = (u8 *)(__va(relocated_ramdisk) +
443 (cont - boot_params.hdr.ramdisk_image));
447 /* Add CONFIG_RANDOMIZE_MEMORY offset. */
449 container += PAGE_OFFSET - __PAGE_OFFSET_BASE;
451 eax = cpuid_eax(0x00000001);
452 eax = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
454 ret = load_microcode_amd(smp_processor_id(), eax, container, container_size);
459 * This will be freed any msec now, stash patches for the current
460 * family and switch to patch cache for cpu hotplug, etc later.
468 void reload_ucode_amd(void)
470 struct microcode_amd *mc;
474 * early==false because this is a syscore ->resume path and by
475 * that time paging is long enabled.
477 if (check_current_patch_level(&rev, false))
480 mc = (struct microcode_amd *)amd_ucode_patch;
482 if (mc && rev < mc->hdr.patch_id) {
483 if (!__apply_microcode_amd(mc)) {
484 ucode_new_rev = mc->hdr.patch_id;
485 pr_info("reload patch_level=0x%08x\n", ucode_new_rev);
489 static u16 __find_equiv_id(unsigned int cpu)
491 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
492 return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig);
495 static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
499 BUG_ON(!equiv_cpu_table);
501 while (equiv_cpu_table[i].equiv_cpu != 0) {
502 if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
503 return equiv_cpu_table[i].installed_cpu;
510 * a small, trivial cache of per-family ucode patches
512 static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
514 struct ucode_patch *p;
516 list_for_each_entry(p, &pcache, plist)
517 if (p->equiv_cpu == equiv_cpu)
522 static void update_cache(struct ucode_patch *new_patch)
524 struct ucode_patch *p;
526 list_for_each_entry(p, &pcache, plist) {
527 if (p->equiv_cpu == new_patch->equiv_cpu) {
528 if (p->patch_id >= new_patch->patch_id)
529 /* we already have the latest patch */
532 list_replace(&p->plist, &new_patch->plist);
538 /* no patch found, add it */
539 list_add_tail(&new_patch->plist, &pcache);
542 static void free_cache(void)
544 struct ucode_patch *p, *tmp;
546 list_for_each_entry_safe(p, tmp, &pcache, plist) {
547 __list_del(p->plist.prev, p->plist.next);
553 static struct ucode_patch *find_patch(unsigned int cpu)
557 equiv_id = __find_equiv_id(cpu);
561 return cache_find_patch(equiv_id);
564 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
566 struct cpuinfo_x86 *c = &cpu_data(cpu);
567 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
568 struct ucode_patch *p;
570 csig->sig = cpuid_eax(0x00000001);
571 csig->rev = c->microcode;
574 * a patch could have been loaded early, set uci->mc so that
575 * mc_bp_resume() can call apply_microcode()
578 if (p && (p->patch_id == csig->rev))
581 pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
586 static unsigned int verify_patch_size(u8 family, u32 patch_size,
591 #define F1XH_MPB_MAX_SIZE 2048
592 #define F14H_MPB_MAX_SIZE 1824
593 #define F15H_MPB_MAX_SIZE 4096
594 #define F16H_MPB_MAX_SIZE 3458
598 max_size = F14H_MPB_MAX_SIZE;
601 max_size = F15H_MPB_MAX_SIZE;
604 max_size = F16H_MPB_MAX_SIZE;
607 max_size = F1XH_MPB_MAX_SIZE;
611 if (patch_size > min_t(u32, size, max_size)) {
612 pr_err("patch size mismatch\n");
620 * Those patch levels cannot be updated to newer ones and thus should be final.
622 static u32 final_levels[] = {
626 0, /* T-101 terminator */
630 * Check the current patch level on this CPU.
632 * @rev: Use it to return the patch level. It is set to 0 in the case of
636 * - true: if update should stop
639 bool check_current_patch_level(u32 *rev, bool early)
645 native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy);
647 if (IS_ENABLED(CONFIG_X86_32) && early)
648 levels = (u32 *)__pa_nodebug(&final_levels);
650 levels = final_levels;
652 for (i = 0; levels[i]; i++) {
653 if (lvl == levels[i]) {
666 int __apply_microcode_amd(struct microcode_amd *mc_amd)
670 native_wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
672 /* verify patch application was successful */
673 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
674 if (rev != mc_amd->hdr.patch_id)
680 int apply_microcode_amd(int cpu)
682 struct cpuinfo_x86 *c = &cpu_data(cpu);
683 struct microcode_amd *mc_amd;
684 struct ucode_cpu_info *uci;
685 struct ucode_patch *p;
688 BUG_ON(raw_smp_processor_id() != cpu);
690 uci = ucode_cpu_info + cpu;
699 if (check_current_patch_level(&rev, false))
702 /* need to apply patch? */
703 if (rev >= mc_amd->hdr.patch_id) {
705 uci->cpu_sig.rev = rev;
709 if (__apply_microcode_amd(mc_amd)) {
710 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
711 cpu, mc_amd->hdr.patch_id);
714 pr_info("CPU%d: new patch_level=0x%08x\n", cpu,
715 mc_amd->hdr.patch_id);
717 uci->cpu_sig.rev = mc_amd->hdr.patch_id;
718 c->microcode = mc_amd->hdr.patch_id;
723 static int install_equiv_cpu_table(const u8 *buf)
725 unsigned int *ibuf = (unsigned int *)buf;
726 unsigned int type = ibuf[1];
727 unsigned int size = ibuf[2];
729 if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
730 pr_err("empty section/"
731 "invalid type field in container file section header\n");
735 equiv_cpu_table = vmalloc(size);
736 if (!equiv_cpu_table) {
737 pr_err("failed to allocate equivalent CPU table\n");
741 memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
743 /* add header length */
744 return size + CONTAINER_HDR_SZ;
747 static void free_equiv_cpu_table(void)
749 vfree(equiv_cpu_table);
750 equiv_cpu_table = NULL;
753 static void cleanup(void)
755 free_equiv_cpu_table();
760 * We return the current size even if some of the checks failed so that
761 * we can skip over the next patch. If we return a negative value, we
762 * signal a grave error like a memory allocation has failed and the
763 * driver cannot continue functioning normally. In such cases, we tear
764 * down everything we've used up so far and exit.
766 static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover)
768 struct microcode_header_amd *mc_hdr;
769 struct ucode_patch *patch;
770 unsigned int patch_size, crnt_size, ret;
774 patch_size = *(u32 *)(fw + 4);
775 crnt_size = patch_size + SECTION_HDR_SIZE;
776 mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
777 proc_id = mc_hdr->processor_rev_id;
779 proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
781 pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
785 /* check if patch is for the current family */
786 proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
787 if (proc_fam != family)
790 if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
791 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
796 ret = verify_patch_size(family, patch_size, leftover);
798 pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
802 patch = kzalloc(sizeof(*patch), GFP_KERNEL);
804 pr_err("Patch allocation failure.\n");
808 patch->data = kmemdup(fw + SECTION_HDR_SIZE, patch_size, GFP_KERNEL);
810 pr_err("Patch data allocation failure.\n");
815 INIT_LIST_HEAD(&patch->plist);
816 patch->patch_id = mc_hdr->patch_id;
817 patch->equiv_cpu = proc_id;
819 pr_debug("%s: Added patch_id: 0x%08x, proc_id: 0x%04x\n",
820 __func__, patch->patch_id, proc_id);
822 /* ... and add to cache. */
828 static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
831 enum ucode_state ret = UCODE_ERROR;
832 unsigned int leftover;
837 offset = install_equiv_cpu_table(data);
839 pr_err("failed to create equivalent cpu table\n");
843 leftover = size - offset;
845 if (*(u32 *)fw != UCODE_UCODE_TYPE) {
846 pr_err("invalid type field in container file section header\n");
847 free_equiv_cpu_table();
852 crnt_size = verify_and_add_patch(family, fw, leftover);
857 leftover -= crnt_size;
863 enum ucode_state load_microcode_amd(int cpu, u8 family, const u8 *data, size_t size)
865 enum ucode_state ret;
867 /* free old equiv table */
868 free_equiv_cpu_table();
870 ret = __load_microcode_amd(family, data, size);
876 /* save BSP's matching patch for early load */
877 if (cpu_data(cpu).cpu_index == boot_cpu_data.cpu_index) {
878 struct ucode_patch *p = find_patch(cpu);
880 memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
881 memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data),
890 * AMD microcode firmware naming convention, up to family 15h they are in
893 * amd-ucode/microcode_amd.bin
895 * This legacy file is always smaller than 2K in size.
897 * Beginning with family 15h, they are in family-specific firmware files:
899 * amd-ucode/microcode_amd_fam15h.bin
900 * amd-ucode/microcode_amd_fam16h.bin
903 * These might be larger than 2K.
905 static enum ucode_state request_microcode_amd(int cpu, struct device *device,
908 char fw_name[36] = "amd-ucode/microcode_amd.bin";
909 struct cpuinfo_x86 *c = &cpu_data(cpu);
910 enum ucode_state ret = UCODE_NFOUND;
911 const struct firmware *fw;
913 /* reload ucode container only on the boot cpu */
914 if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index)
918 snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
920 if (request_firmware_direct(&fw, (const char *)fw_name, device)) {
921 pr_debug("failed to load file %s\n", fw_name);
926 if (*(u32 *)fw->data != UCODE_MAGIC) {
927 pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
931 ret = load_microcode_amd(cpu, c->x86, fw->data, fw->size);
934 release_firmware(fw);
940 static enum ucode_state
941 request_microcode_user(int cpu, const void __user *buf, size_t size)
946 static void microcode_fini_cpu_amd(int cpu)
948 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
953 static struct microcode_ops microcode_amd_ops = {
954 .request_microcode_user = request_microcode_user,
955 .request_microcode_fw = request_microcode_amd,
956 .collect_cpu_info = collect_cpu_info_amd,
957 .apply_microcode = apply_microcode_amd,
958 .microcode_fini_cpu = microcode_fini_cpu_amd,
961 struct microcode_ops * __init init_amd_microcode(void)
963 struct cpuinfo_x86 *c = &boot_cpu_data;
965 if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
966 pr_warn("AMD CPU family 0x%x not supported\n", c->x86);
971 pr_info_once("microcode updated early to new patch_level=0x%08x\n",
974 return µcode_amd_ops;
977 void __exit exit_amd_microcode(void)