2 * Intel specific MCE features.
3 * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
4 * Copyright (C) 2008, 2009 Intel Corporation
8 #include <linux/init.h>
9 #include <linux/interrupt.h>
10 #include <linux/percpu.h>
11 #include <asm/processor.h>
15 #include <asm/hw_irq.h>
17 #include <asm/therm_throt.h>
19 asmlinkage void smp_thermal_interrupt(void)
28 rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
29 if (therm_throt_process(msr_val & 1))
30 mce_log_therm_throt_event(msr_val);
32 inc_irq_stat(irq_thermal_count);
36 static void intel_init_thermal(struct cpuinfo_x86 *c)
40 unsigned int cpu = smp_processor_id();
42 if (!cpu_has(c, X86_FEATURE_ACPI))
45 if (!cpu_has(c, X86_FEATURE_ACC))
48 /* first check if TM1 is already enabled by the BIOS, in which
49 * case there might be some SMM goo which handles it, so we can't even
50 * put a handler since it might be delivered via SMI already.
52 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
53 h = apic_read(APIC_LVTTHMR);
54 if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
56 "CPU%d: Thermal monitoring handled by SMI\n", cpu);
60 if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))
63 if (h & APIC_VECTOR_MASK) {
65 "CPU%d: Thermal LVT vector (%#x) already "
66 "installed\n", cpu, (h & APIC_VECTOR_MASK));
70 h = THERMAL_APIC_VECTOR;
71 h |= (APIC_DM_FIXED | APIC_LVT_MASKED);
72 apic_write(APIC_LVTTHMR, h);
74 rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
75 wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);
77 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
78 wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
80 l = apic_read(APIC_LVTTHMR);
81 apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
82 printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n",
83 cpu, tm2 ? "TM2" : "TM1");
85 /* enable thermal throttle processing */
86 atomic_set(&therm_throt_en, 1);
91 * Support for Intel Correct Machine Check Interrupts. This allows
92 * the CPU to raise an interrupt when a corrected machine check happened.
93 * Normally we pick those up using a regular polling timer.
94 * Also supports reliable discovery of shared banks.
97 static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
100 * cmci_discover_lock protects against parallel discovery attempts
101 * which could race against each other.
103 static DEFINE_SPINLOCK(cmci_discover_lock);
105 #define CMCI_THRESHOLD 1
107 static int cmci_supported(int *banks)
112 * Vendor check is not strictly needed, but the initial
113 * initialization is vendor keyed and this
114 * makes sure none of the backdoors are entered otherwise.
116 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
118 if (!cpu_has_apic || lapic_get_maxlvt() < 6)
120 rdmsrl(MSR_IA32_MCG_CAP, cap);
121 *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
122 return !!(cap & MCG_CMCI_P);
126 * The interrupt handler. This is called on every event.
127 * Just call the poller directly to log any events.
128 * This could in theory increase the threshold under high load,
129 * but doesn't for now.
131 static void intel_threshold_interrupt(void)
133 machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
137 static void print_update(char *type, int *hdr, int num)
140 printk(KERN_INFO "CPU %d MCA banks", smp_processor_id());
142 printk(KERN_CONT " %s:%d", type, num);
146 * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
147 * on this CPU. Use the algorithm recommended in the SDM to discover shared
150 static void cmci_discover(int banks, int boot)
152 unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned);
157 spin_lock_irqsave(&cmci_discover_lock, flags);
158 for (i = 0; i < banks; i++) {
161 if (test_bit(i, owned))
164 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
166 /* Already owned by someone else? */
168 if (test_and_clear_bit(i, owned) || boot)
169 print_update("SHD", &hdr, i);
170 __clear_bit(i, __get_cpu_var(mce_poll_banks));
174 val |= CMCI_EN | CMCI_THRESHOLD;
175 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
176 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
178 /* Did the enable bit stick? -- the bank supports CMCI */
180 if (!test_and_set_bit(i, owned) || boot)
181 print_update("CMCI", &hdr, i);
182 __clear_bit(i, __get_cpu_var(mce_poll_banks));
184 WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
187 spin_unlock_irqrestore(&cmci_discover_lock, flags);
189 printk(KERN_CONT "\n");
193 * Just in case we missed an event during initialization check
194 * all the CMCI owned banks.
196 void cmci_recheck(void)
201 if (!mce_available(¤t_cpu_data) || !cmci_supported(&banks))
203 local_irq_save(flags);
204 machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
205 local_irq_restore(flags);
209 * Disable CMCI on this CPU for all banks it owns when it goes down.
210 * This allows other CPUs to claim the banks on rediscovery.
212 void cmci_clear(void)
219 if (!cmci_supported(&banks))
221 spin_lock_irqsave(&cmci_discover_lock, flags);
222 for (i = 0; i < banks; i++) {
223 if (!test_bit(i, __get_cpu_var(mce_banks_owned)))
226 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
227 val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK);
228 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
229 __clear_bit(i, __get_cpu_var(mce_banks_owned));
231 spin_unlock_irqrestore(&cmci_discover_lock, flags);
235 * After a CPU went down cycle through all the others and rediscover
236 * Must run in process context.
238 void cmci_rediscover(int dying)
244 if (!cmci_supported(&banks))
246 if (!alloc_cpumask_var(&old, GFP_KERNEL))
248 cpumask_copy(old, ¤t->cpus_allowed);
250 for_each_online_cpu (cpu) {
253 if (set_cpus_allowed_ptr(current, cpumask_of(cpu)))
255 /* Recheck banks in case CPUs don't all have the same */
256 if (cmci_supported(&banks))
257 cmci_discover(banks, 0);
260 set_cpus_allowed_ptr(current, old);
261 free_cpumask_var(old);
265 * Reenable CMCI on this CPU in case a CPU down failed.
267 void cmci_reenable(void)
270 if (cmci_supported(&banks))
271 cmci_discover(banks, 0);
274 static void intel_init_cmci(void)
278 if (!cmci_supported(&banks))
281 mce_threshold_vector = intel_threshold_interrupt;
282 cmci_discover(banks, 1);
284 * For CPU #0 this runs with still disabled APIC, but that's
285 * ok because only the vector is set up. We still do another
286 * check for the banks later for CPU #0 just to make sure
287 * to not miss any events.
289 apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED);
293 void mce_intel_feature_init(struct cpuinfo_x86 *c)
295 intel_init_thermal(c);