2 * Intel specific MCE features.
3 * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
4 * Copyright (C) 2008, 2009 Intel Corporation
8 #include <linux/init.h>
9 #include <linux/interrupt.h>
10 #include <linux/percpu.h>
11 #include <asm/processor.h>
15 #include <asm/hw_irq.h>
17 #include <asm/therm_throt.h>
22 asmlinkage void smp_thermal_interrupt(void)
31 rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
32 if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT))
33 mce_log_therm_throt_event(msr_val);
35 inc_irq_stat(irq_thermal_count);
40 * Support for Intel Correct Machine Check Interrupts. This allows
41 * the CPU to raise an interrupt when a corrected machine check happened.
42 * Normally we pick those up using a regular polling timer.
43 * Also supports reliable discovery of shared banks.
46 static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
49 * cmci_discover_lock protects against parallel discovery attempts
50 * which could race against each other.
52 static DEFINE_SPINLOCK(cmci_discover_lock);
54 #define CMCI_THRESHOLD 1
56 static int cmci_supported(int *banks)
60 if (mce_cmci_disabled || mce_ignore_ce)
64 * Vendor check is not strictly needed, but the initial
65 * initialization is vendor keyed and this
66 * makes sure none of the backdoors are entered otherwise.
68 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
70 if (!cpu_has_apic || lapic_get_maxlvt() < 6)
72 rdmsrl(MSR_IA32_MCG_CAP, cap);
73 *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
74 return !!(cap & MCG_CMCI_P);
78 * The interrupt handler. This is called on every event.
79 * Just call the poller directly to log any events.
80 * This could in theory increase the threshold under high load,
81 * but doesn't for now.
83 static void intel_threshold_interrupt(void)
85 machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
89 static void print_update(char *type, int *hdr, int num)
92 printk(KERN_INFO "CPU %d MCA banks", smp_processor_id());
94 printk(KERN_CONT " %s:%d", type, num);
98 * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
99 * on this CPU. Use the algorithm recommended in the SDM to discover shared
102 static void cmci_discover(int banks, int boot)
104 unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned);
109 spin_lock_irqsave(&cmci_discover_lock, flags);
110 for (i = 0; i < banks; i++) {
113 if (test_bit(i, owned))
116 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
118 /* Already owned by someone else? */
120 if (test_and_clear_bit(i, owned) || boot)
121 print_update("SHD", &hdr, i);
122 __clear_bit(i, __get_cpu_var(mce_poll_banks));
126 val |= CMCI_EN | CMCI_THRESHOLD;
127 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
128 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
130 /* Did the enable bit stick? -- the bank supports CMCI */
132 if (!test_and_set_bit(i, owned) || boot)
133 print_update("CMCI", &hdr, i);
134 __clear_bit(i, __get_cpu_var(mce_poll_banks));
136 WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
139 spin_unlock_irqrestore(&cmci_discover_lock, flags);
141 printk(KERN_CONT "\n");
145 * Just in case we missed an event during initialization check
146 * all the CMCI owned banks.
148 void cmci_recheck(void)
153 if (!mce_available(¤t_cpu_data) || !cmci_supported(&banks))
155 local_irq_save(flags);
156 machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
157 local_irq_restore(flags);
161 * Disable CMCI on this CPU for all banks it owns when it goes down.
162 * This allows other CPUs to claim the banks on rediscovery.
164 void cmci_clear(void)
171 if (!cmci_supported(&banks))
173 spin_lock_irqsave(&cmci_discover_lock, flags);
174 for (i = 0; i < banks; i++) {
175 if (!test_bit(i, __get_cpu_var(mce_banks_owned)))
178 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
179 val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK);
180 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
181 __clear_bit(i, __get_cpu_var(mce_banks_owned));
183 spin_unlock_irqrestore(&cmci_discover_lock, flags);
187 * After a CPU went down cycle through all the others and rediscover
188 * Must run in process context.
190 void cmci_rediscover(int dying)
196 if (!cmci_supported(&banks))
198 if (!alloc_cpumask_var(&old, GFP_KERNEL))
200 cpumask_copy(old, ¤t->cpus_allowed);
202 for_each_online_cpu(cpu) {
205 if (set_cpus_allowed_ptr(current, cpumask_of(cpu)))
207 /* Recheck banks in case CPUs don't all have the same */
208 if (cmci_supported(&banks))
209 cmci_discover(banks, 0);
212 set_cpus_allowed_ptr(current, old);
213 free_cpumask_var(old);
217 * Reenable CMCI on this CPU in case a CPU down failed.
219 void cmci_reenable(void)
222 if (cmci_supported(&banks))
223 cmci_discover(banks, 0);
226 static void intel_init_cmci(void)
230 if (!cmci_supported(&banks))
233 mce_threshold_vector = intel_threshold_interrupt;
234 cmci_discover(banks, 1);
236 * For CPU #0 this runs with still disabled APIC, but that's
237 * ok because only the vector is set up. We still do another
238 * check for the banks later for CPU #0 just to make sure
239 * to not miss any events.
241 apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED);
245 void mce_intel_feature_init(struct cpuinfo_x86 *c)
247 intel_init_thermal(c);