arch/x86/kernel/cpu/mcheck/mce_amd.c

   1 /*
   2  *  (c) 2005-2016 Advanced Micro Devices, Inc.
   3  *  Your use of this code is subject to the terms and conditions of the
   4  *  GNU general public license version 2. See "COPYING" or
   5  *  http://www.gnu.org/licenses/gpl.html
   6  *
   7  *  Written by Jacob Shin - AMD, Inc.
   8  *  Maintained by: Borislav Petkov <bp@alien8.de>
   9  *
  10  *  All MC4_MISCi registers are shared between cores on a node.
  11  */
  12 #include <linux/interrupt.h>
  13 #include <linux/notifier.h>
  14 #include <linux/kobject.h>
  15 #include <linux/percpu.h>
  16 #include <linux/errno.h>
  17 #include <linux/sched.h>
  18 #include <linux/sysfs.h>
  19 #include <linux/slab.h>
  20 #include <linux/init.h>
  21 #include <linux/cpu.h>
  22 #include <linux/smp.h>
  23 #include <linux/string.h>
  24
  25 #include <asm/amd_nb.h>
  26 #include <asm/apic.h>
  27 #include <asm/mce.h>
  28 #include <asm/msr.h>
  29 #include <asm/trace/irq_vectors.h>
  30
  31 #include "mce-internal.h"
  32
  33 #define NR_BLOCKS         5
  34 #define THRESHOLD_MAX     0xFFF
  35 #define INT_TYPE_APIC     0x00020000
  36 #define MASK_VALID_HI     0x80000000
  37 #define MASK_CNTP_HI      0x40000000
  38 #define MASK_LOCKED_HI    0x20000000
  39 #define MASK_LVTOFF_HI    0x00F00000
  40 #define MASK_COUNT_EN_HI  0x00080000
  41 #define MASK_INT_TYPE_HI  0x00060000
  42 #define MASK_OVERFLOW_HI  0x00010000
  43 #define MASK_ERR_COUNT_HI 0x00000FFF
  44 #define MASK_BLKPTR_LO    0xFF000000
  45 #define MCG_XBLK_ADDR     0xC0000400
  46
  47 /* Deferred error settings */
  48 #define MSR_CU_DEF_ERR          0xC0000410
  49 #define MASK_DEF_LVTOFF         0x000000F0
  50 #define MASK_DEF_INT_TYPE       0x00000006
  51 #define DEF_LVT_OFF             0x2
  52 #define DEF_INT_TYPE_APIC       0x2
  53
  54 /* Scalable MCA: */
  55
  56 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
  57 #define SMCA_THR_LVT_OFF        0xF000
  58
  59 static bool thresholding_en;
  60
  61 static const char * const th_names[] = {
  62         "load_store",
  63         "insn_fetch",
  64         "combined_unit",
  65         "decode_unit",
  66         "northbridge",
  67         "execution_unit",
  68 };
  69
  70 static const char * const smca_umc_block_names[] = {
  71         "dram_ecc",
  72         "misc_umc"
  73 };
  74
  75 struct smca_bank_name {
  76         const char *name;       /* Short name for sysfs */
  77         const char *long_name;  /* Long name for pretty-printing */
  78 };
  79
  80 static struct smca_bank_name smca_names[] = {
  81         [SMCA_LS]       = { "load_store",       "Load Store Unit" },
  82         [SMCA_IF]       = { "insn_fetch",       "Instruction Fetch Unit" },
  83         [SMCA_L2_CACHE] = { "l2_cache",         "L2 Cache" },
  84         [SMCA_DE]       = { "decode_unit",      "Decode Unit" },
  85         [SMCA_RESERVED] = { "reserved",         "Reserved" },
  86         [SMCA_EX]       = { "execution_unit",   "Execution Unit" },
  87         [SMCA_FP]       = { "floating_point",   "Floating Point Unit" },
  88         [SMCA_L3_CACHE] = { "l3_cache",         "L3 Cache" },
  89         [SMCA_CS]       = { "coherent_slave",   "Coherent Slave" },
  90         [SMCA_PIE]      = { "pie",              "Power, Interrupts, etc." },
  91         [SMCA_UMC]      = { "umc",              "Unified Memory Controller" },
  92         [SMCA_PB]       = { "param_block",      "Parameter Block" },
  93         [SMCA_PSP]      = { "psp",              "Platform Security Processor" },
  94         [SMCA_SMU]      = { "smu",              "System Management Unit" },
  95 };
  96
  97 static u32 smca_bank_addrs[MAX_NR_BANKS][NR_BLOCKS] __ro_after_init =
  98 {
  99         [0 ... MAX_NR_BANKS - 1] = { [0 ... NR_BLOCKS - 1] = -1 }
 100 };
 101
 102 const char *smca_get_name(enum smca_bank_types t)
 103 {
 104         if (t >= N_SMCA_BANK_TYPES)
 105                 return NULL;
 106
 107         return smca_names[t].name;
 108 }
 109
 110 const char *smca_get_long_name(enum smca_bank_types t)
 111 {
 112         if (t >= N_SMCA_BANK_TYPES)
 113                 return NULL;
 114
 115         return smca_names[t].long_name;
 116 }
 117 EXPORT_SYMBOL_GPL(smca_get_long_name);
 118
 119 static enum smca_bank_types smca_get_bank_type(unsigned int bank)
 120 {
 121         struct smca_bank *b;
 122
 123         if (bank >= MAX_NR_BANKS)
 124                 return N_SMCA_BANK_TYPES;
 125
 126         b = &smca_banks[bank];
 127         if (!b->hwid)
 128                 return N_SMCA_BANK_TYPES;
 129
 130         return b->hwid->bank_type;
 131 }
 132
 133 static struct smca_hwid smca_hwid_mcatypes[] = {
 134         /* { bank_type, hwid_mcatype, xec_bitmap } */
 135
 136         /* Reserved type */
 137         { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 },
 138
 139         /* ZN Core (HWID=0xB0) MCA types */
 140         { SMCA_LS,       HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF },
 141         { SMCA_IF,       HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
 142         { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF },
 143         { SMCA_DE,       HWID_MCATYPE(0xB0, 0x3), 0x1FF },
 144         /* HWID 0xB0 MCATYPE 0x4 is Reserved */
 145         { SMCA_EX,       HWID_MCATYPE(0xB0, 0x5), 0x7FF },
 146         { SMCA_FP,       HWID_MCATYPE(0xB0, 0x6), 0x7F },
 147         { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF },
 148
 149         /* Data Fabric MCA types */
 150         { SMCA_CS,       HWID_MCATYPE(0x2E, 0x0), 0x1FF },
 151         { SMCA_PIE,      HWID_MCATYPE(0x2E, 0x1), 0xF },
 152
 153         /* Unified Memory Controller MCA type */
 154         { SMCA_UMC,      HWID_MCATYPE(0x96, 0x0), 0x3F },
 155
 156         /* Parameter Block MCA type */
 157         { SMCA_PB,       HWID_MCATYPE(0x05, 0x0), 0x1 },
 158
 159         /* Platform Security Processor MCA type */
 160         { SMCA_PSP,      HWID_MCATYPE(0xFF, 0x0), 0x1 },
 161
 162         /* System Management Unit MCA type */
 163         { SMCA_SMU,      HWID_MCATYPE(0x01, 0x0), 0x1 },
 164 };
 165
 166 struct smca_bank smca_banks[MAX_NR_BANKS];
 167 EXPORT_SYMBOL_GPL(smca_banks);
 168
 169 /*
 170  * In SMCA enabled processors, we can have multiple banks for a given IP type.
 171  * So to define a unique name for each bank, we use a temp c-string to append
 172  * the MCA_IPID[InstanceId] to type's name in get_name().
 173  *
 174  * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
 175  * is greater than 8 plus 1 (for underscore) plus length of longest type name.
 176  */
 177 #define MAX_MCATYPE_NAME_LEN    30
 178 static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
 179
 180 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
 181 static DEFINE_PER_CPU(unsigned int, bank_map);  /* see which banks are on */
 182
 183 static void amd_threshold_interrupt(void);
 184 static void amd_deferred_error_interrupt(void);
 185
 186 static void default_deferred_error_interrupt(void)
 187 {
 188         pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR);
 189 }
 190 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
 191
 192 static void smca_configure(unsigned int bank, unsigned int cpu)
 193 {
 194         unsigned int i, hwid_mcatype;
 195         struct smca_hwid *s_hwid;
 196         u32 high, low;
 197         u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);
 198
 199         /* Set appropriate bits in MCA_CONFIG */
 200         if (!rdmsr_safe(smca_config, &low, &high)) {
 201                 /*
 202                  * OS is required to set the MCAX bit to acknowledge that it is
 203                  * now using the new MSR ranges and new registers under each
 204                  * bank. It also means that the OS will configure deferred
 205                  * errors in the new MCx_CONFIG register. If the bit is not set,
 206                  * uncorrectable errors will cause a system panic.
 207                  *
 208                  * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
 209                  */
 210                 high |= BIT(0);
 211
 212                 /*
 213                  * SMCA sets the Deferred Error Interrupt type per bank.
 214                  *
 215                  * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
 216                  * if the DeferredIntType bit field is available.
 217                  *
 218                  * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
 219                  * high portion of the MSR). OS should set this to 0x1 to enable
 220                  * APIC based interrupt. First, check that no interrupt has been
 221                  * set.
 222                  */
 223                 if ((low & BIT(5)) && !((high >> 5) & 0x3))
 224                         high |= BIT(5);
 225
 226                 wrmsr(smca_config, low, high);
 227         }
 228
 229         /* Return early if this bank was already initialized. */
 230         if (smca_banks[bank].hwid)
 231                 return;
 232
 233         if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
 234                 pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
 235                 return;
 236         }
 237
 238         hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
 239                                     (high & MCI_IPID_MCATYPE) >> 16);
 240
 241         for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
 242                 s_hwid = &smca_hwid_mcatypes[i];
 243                 if (hwid_mcatype == s_hwid->hwid_mcatype) {
 244                         smca_banks[bank].hwid = s_hwid;
 245                         smca_banks[bank].id = low;
 246                         smca_banks[bank].sysfs_id = s_hwid->count++;
 247                         break;
 248                 }
 249         }
 250 }
 251
 252 struct thresh_restart {
 253         struct threshold_block  *b;
 254         int                     reset;
 255         int                     set_lvt_off;
 256         int                     lvt_off;
 257         u16                     old_limit;
 258 };
 259
 260 static inline bool is_shared_bank(int bank)
 261 {
 262         /*
 263          * Scalable MCA provides for only one core to have access to the MSRs of
 264          * a shared bank.
 265          */
 266         if (mce_flags.smca)
 267                 return false;
 268
 269         /* Bank 4 is for northbridge reporting and is thus shared */
 270         return (bank == 4);
 271 }
 272
 273 static const char *bank4_names(const struct threshold_block *b)
 274 {
 275         switch (b->address) {
 276         /* MSR4_MISC0 */
 277         case 0x00000413:
 278                 return "dram";
 279
 280         case 0xc0000408:
 281                 return "ht_links";
 282
 283         case 0xc0000409:
 284                 return "l3_cache";
 285
 286         default:
 287                 WARN(1, "Funny MSR: 0x%08x\n", b->address);
 288                 return "";
 289         }
 290 };
 291
 292
 293 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
 294 {
 295         /*
 296          * bank 4 supports APIC LVT interrupts implicitly since forever.
 297          */
 298         if (bank == 4)
 299                 return true;
 300
 301         /*
 302          * IntP: interrupt present; if this bit is set, the thresholding
 303          * bank can generate APIC LVT interrupts
 304          */
 305         return msr_high_bits & BIT(28);
 306 }
 307
 308 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
 309 {
 310         int msr = (hi & MASK_LVTOFF_HI) >> 20;
 311
 312         if (apic < 0) {
 313                 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
 314                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
 315                        b->bank, b->block, b->address, hi, lo);
 316                 return 0;
 317         }
 318
 319         if (apic != msr) {
 320                 /*
 321                  * On SMCA CPUs, LVT offset is programmed at a different MSR, and
 322                  * the BIOS provides the value. The original field where LVT offset
 323                  * was set is reserved. Return early here:
 324                  */
 325                 if (mce_flags.smca)
 326                         return 0;
 327
 328                 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
 329                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
 330                        b->cpu, apic, b->bank, b->block, b->address, hi, lo);
 331                 return 0;
 332         }
 333
 334         return 1;
 335 };
 336
 337 /* Reprogram MCx_MISC MSR behind this threshold bank. */
 338 static void threshold_restart_bank(void *_tr)
 339 {
 340         struct thresh_restart *tr = _tr;
 341         u32 hi, lo;
 342
 343         rdmsr(tr->b->address, lo, hi);
 344
 345         if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
 346                 tr->reset = 1;  /* limit cannot be lower than err count */
 347
 348         if (tr->reset) {                /* reset err count and overflow bit */
 349                 hi =
 350                     (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
 351                     (THRESHOLD_MAX - tr->b->threshold_limit);
 352         } else if (tr->old_limit) {     /* change limit w/o reset */
 353                 int new_count = (hi & THRESHOLD_MAX) +
 354                     (tr->old_limit - tr->b->threshold_limit);
 355
 356                 hi = (hi & ~MASK_ERR_COUNT_HI) |
 357                     (new_count & THRESHOLD_MAX);
 358         }
 359
 360         /* clear IntType */
 361         hi &= ~MASK_INT_TYPE_HI;
 362
 363         if (!tr->b->interrupt_capable)
 364                 goto done;
 365
 366         if (tr->set_lvt_off) {
 367                 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
 368                         /* set new lvt offset */
 369                         hi &= ~MASK_LVTOFF_HI;
 370                         hi |= tr->lvt_off << 20;
 371                 }
 372         }
 373
 374         if (tr->b->interrupt_enable)
 375                 hi |= INT_TYPE_APIC;
 376
 377  done:
 378
 379         hi |= MASK_COUNT_EN_HI;
 380         wrmsr(tr->b->address, lo, hi);
 381 }
 382
 383 static void mce_threshold_block_init(struct threshold_block *b, int offset)
 384 {
 385         struct thresh_restart tr = {
 386                 .b                      = b,
 387                 .set_lvt_off            = 1,
 388                 .lvt_off                = offset,
 389         };
 390
 391         b->threshold_limit              = THRESHOLD_MAX;
 392         threshold_restart_bank(&tr);
 393 };
 394
 395 static int setup_APIC_mce_threshold(int reserved, int new)
 396 {
 397         if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
 398                                               APIC_EILVT_MSG_FIX, 0))
 399                 return new;
 400
 401         return reserved;
 402 }
 403
 404 static int setup_APIC_deferred_error(int reserved, int new)
 405 {
 406         if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR,
 407                                               APIC_EILVT_MSG_FIX, 0))
 408                 return new;
 409
 410         return reserved;
 411 }
 412
 413 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
 414 {
 415         u32 low = 0, high = 0;
 416         int def_offset = -1, def_new;
 417
 418         if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high))
 419                 return;
 420
 421         def_new = (low & MASK_DEF_LVTOFF) >> 4;
 422         if (!(low & MASK_DEF_LVTOFF)) {
 423                 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
 424                 def_new = DEF_LVT_OFF;
 425                 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4);
 426         }
 427
 428         def_offset = setup_APIC_deferred_error(def_offset, def_new);
 429         if ((def_offset == def_new) &&
 430             (deferred_error_int_vector != amd_deferred_error_interrupt))
 431                 deferred_error_int_vector = amd_deferred_error_interrupt;
 432
 433         if (!mce_flags.smca)
 434                 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
 435
 436         wrmsr(MSR_CU_DEF_ERR, low, high);
 437 }
 438
 439 static u32 smca_get_block_address(unsigned int cpu, unsigned int bank,
 440                                   unsigned int block)
 441 {
 442         u32 low, high;
 443         u32 addr = 0;
 444
 445         if (smca_get_bank_type(bank) == SMCA_RESERVED)
 446                 return addr;
 447
 448         if (!block)
 449                 return MSR_AMD64_SMCA_MCx_MISC(bank);
 450
 451         /* Check our cache first: */
 452         if (smca_bank_addrs[bank][block] != -1)
 453                 return smca_bank_addrs[bank][block];
 454
 455         /*
 456          * For SMCA enabled processors, BLKPTR field of the first MISC register
 457          * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4).
 458          */
 459         if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
 460                 goto out;
 461
 462         if (!(low & MCI_CONFIG_MCAX))
 463                 goto out;
 464
 465         if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
 466             (low & MASK_BLKPTR_LO))
 467                 addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
 468
 469 out:
 470         smca_bank_addrs[bank][block] = addr;
 471         return addr;
 472 }
 473
 474 static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high,
 475                              unsigned int bank, unsigned int block)
 476 {
 477         u32 addr = 0, offset = 0;
 478
 479         if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
 480                 return addr;
 481
 482         if (mce_flags.smca)
 483                 return smca_get_block_address(cpu, bank, block);
 484
 485         /* Fall back to method we used for older processors: */
 486         switch (block) {
 487         case 0:
 488                 addr = msr_ops.misc(bank);
 489                 break;
 490         case 1:
 491                 offset = ((low & MASK_BLKPTR_LO) >> 21);
 492                 if (offset)
 493                         addr = MCG_XBLK_ADDR + offset;
 494                 break;
 495         default:
 496                 addr = ++current_addr;
 497         }
 498         return addr;
 499 }
 500
 501 static int
 502 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
 503                         int offset, u32 misc_high)
 504 {
 505         unsigned int cpu = smp_processor_id();
 506         u32 smca_low, smca_high;
 507         struct threshold_block b;
 508         int new;
 509
 510         if (!block)
 511                 per_cpu(bank_map, cpu) |= (1 << bank);
 512
 513         memset(&b, 0, sizeof(b));
 514         b.cpu                   = cpu;
 515         b.bank                  = bank;
 516         b.block                 = block;
 517         b.address               = addr;
 518         b.interrupt_capable     = lvt_interrupt_supported(bank, misc_high);
 519
 520         if (!b.interrupt_capable)
 521                 goto done;
 522
 523         b.interrupt_enable = 1;
 524
 525         if (!mce_flags.smca) {
 526                 new = (misc_high & MASK_LVTOFF_HI) >> 20;
 527                 goto set_offset;
 528         }
 529
 530         /* Gather LVT offset for thresholding: */
 531         if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
 532                 goto out;
 533
 534         new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
 535
 536 set_offset:
 537         offset = setup_APIC_mce_threshold(offset, new);
 538
 539         if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt))
 540                 mce_threshold_vector = amd_threshold_interrupt;
 541
 542 done:
 543         mce_threshold_block_init(&b, offset);
 544
 545 out:
 546         return offset;
 547 }
 548
 549 /* cpu init entry point, called from mce.c with preempt off */
 550 void mce_amd_feature_init(struct cpuinfo_x86 *c)
 551 {
 552         u32 low = 0, high = 0, address = 0;
 553         unsigned int bank, block, cpu = smp_processor_id();
 554         int offset = -1;
 555
 556         for (bank = 0; bank < mca_cfg.banks; ++bank) {
 557                 if (mce_flags.smca)
 558                         smca_configure(bank, cpu);
 559
 560                 for (block = 0; block < NR_BLOCKS; ++block) {
 561                         address = get_block_address(cpu, address, low, high, bank, block);
 562                         if (!address)
 563                                 break;
 564
 565                         if (rdmsr_safe(address, &low, &high))
 566                                 break;
 567
 568                         if (!(high & MASK_VALID_HI))
 569                                 continue;
 570
 571                         if (!(high & MASK_CNTP_HI)  ||
 572                              (high & MASK_LOCKED_HI))
 573                                 continue;
 574
 575                         offset = prepare_threshold_block(bank, block, address, offset, high);
 576                 }
 577         }
 578
 579         if (mce_flags.succor)
 580                 deferred_error_interrupt_enable(c);
 581 }
 582
 583 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
 584 {
 585         u64 dram_base_addr, dram_limit_addr, dram_hole_base;
 586         /* We start from the normalized address */
 587         u64 ret_addr = norm_addr;
 588
 589         u32 tmp;
 590
 591         u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask;
 592         u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
 593         u8 intlv_addr_sel, intlv_addr_bit;
 594         u8 num_intlv_bits, hashed_bit;
 595         u8 lgcy_mmio_hole_en, base = 0;
 596         u8 cs_mask, cs_id = 0;
 597         bool hash_enabled = false;
 598
 599         /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
 600         if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
 601                 goto out_err;
 602
 603         /* Remove HiAddrOffset from normalized address, if enabled: */
 604         if (tmp & BIT(0)) {
 605                 u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
 606
 607                 if (norm_addr >= hi_addr_offset) {
 608                         ret_addr -= hi_addr_offset;
 609                         base = 1;
 610                 }
 611         }
 612
 613         /* Read D18F0x110 (DramBaseAddress). */
 614         if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp))
 615                 goto out_err;
 616
 617         /* Check if address range is valid. */
 618         if (!(tmp & BIT(0))) {
 619                 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
 620                         __func__, tmp);
 621                 goto out_err;
 622         }
 623
 624         lgcy_mmio_hole_en = tmp & BIT(1);
 625         intlv_num_chan    = (tmp >> 4) & 0xF;
 626         intlv_addr_sel    = (tmp >> 8) & 0x7;
 627         dram_base_addr    = (tmp & GENMASK_ULL(31, 12)) << 16;
 628
 629         /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
 630         if (intlv_addr_sel > 3) {
 631                 pr_err("%s: Invalid interleave address select %d.\n",
 632                         __func__, intlv_addr_sel);
 633                 goto out_err;
 634         }
 635
 636         /* Read D18F0x114 (DramLimitAddress). */
 637         if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp))
 638                 goto out_err;
 639
 640         intlv_num_sockets = (tmp >> 8) & 0x1;
 641         intlv_num_dies    = (tmp >> 10) & 0x3;
 642         dram_limit_addr   = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
 643
 644         intlv_addr_bit = intlv_addr_sel + 8;
 645
 646         /* Re-use intlv_num_chan by setting it equal to log2(#channels) */
 647         switch (intlv_num_chan) {
 648         case 0: intlv_num_chan = 0; break;
 649         case 1: intlv_num_chan = 1; break;
 650         case 3: intlv_num_chan = 2; break;
 651         case 5: intlv_num_chan = 3; break;
 652         case 7: intlv_num_chan = 4; break;
 653
 654         case 8: intlv_num_chan = 1;
 655                 hash_enabled = true;
 656                 break;
 657         default:
 658                 pr_err("%s: Invalid number of interleaved channels %d.\n",
 659                         __func__, intlv_num_chan);
 660                 goto out_err;
 661         }
 662
 663         num_intlv_bits = intlv_num_chan;
 664
 665         if (intlv_num_dies > 2) {
 666                 pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
 667                         __func__, intlv_num_dies);
 668                 goto out_err;
 669         }
 670
 671         num_intlv_bits += intlv_num_dies;
 672
 673         /* Add a bit if sockets are interleaved. */
 674         num_intlv_bits += intlv_num_sockets;
 675
 676         /* Assert num_intlv_bits <= 4 */
 677         if (num_intlv_bits > 4) {
 678                 pr_err("%s: Invalid interleave bits %d.\n",
 679                         __func__, num_intlv_bits);
 680                 goto out_err;
 681         }
 682
 683         if (num_intlv_bits > 0) {
 684                 u64 temp_addr_x, temp_addr_i, temp_addr_y;
 685                 u8 die_id_bit, sock_id_bit, cs_fabric_id;
 686
 687                 /*
 688                  * Read FabricBlockInstanceInformation3_CS[BlockFabricID].
 689                  * This is the fabric id for this coherent slave. Use
 690                  * umc/channel# as instance id of the coherent slave
 691                  * for FICAA.
 692                  */
 693                 if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp))
 694                         goto out_err;
 695
 696                 cs_fabric_id = (tmp >> 8) & 0xFF;
 697                 die_id_bit   = 0;
 698
 699                 /* If interleaved over more than 1 channel: */
 700                 if (intlv_num_chan) {
 701                         die_id_bit = intlv_num_chan;
 702                         cs_mask    = (1 << die_id_bit) - 1;
 703                         cs_id      = cs_fabric_id & cs_mask;
 704                 }
 705
 706                 sock_id_bit = die_id_bit;
 707
 708                 /* Read D18F1x208 (SystemFabricIdMask). */
 709                 if (intlv_num_dies || intlv_num_sockets)
 710                         if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp))
 711                                 goto out_err;
 712
 713                 /* If interleaved over more than 1 die. */
 714                 if (intlv_num_dies) {
 715                         sock_id_bit  = die_id_bit + intlv_num_dies;
 716                         die_id_shift = (tmp >> 24) & 0xF;
 717                         die_id_mask  = (tmp >> 8) & 0xFF;
 718
 719                         cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
 720                 }
 721
 722                 /* If interleaved over more than 1 socket. */
 723                 if (intlv_num_sockets) {
 724                         socket_id_shift = (tmp >> 28) & 0xF;
 725                         socket_id_mask  = (tmp >> 16) & 0xFF;
 726
 727                         cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
 728                 }
 729
 730                 /*
 731                  * The pre-interleaved address consists of XXXXXXIIIYYYYY
 732                  * where III is the ID for this CS, and XXXXXXYYYYY are the
 733                  * address bits from the post-interleaved address.
 734                  * "num_intlv_bits" has been calculated to tell us how many "I"
 735                  * bits there are. "intlv_addr_bit" tells us how many "Y" bits
 736                  * there are (where "I" starts).
 737                  */
 738                 temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0);
 739                 temp_addr_i = (cs_id << intlv_addr_bit);
 740                 temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
 741                 ret_addr    = temp_addr_x | temp_addr_i | temp_addr_y;
 742         }
 743
 744         /* Add dram base address */
 745         ret_addr += dram_base_addr;
 746
 747         /* If legacy MMIO hole enabled */
 748         if (lgcy_mmio_hole_en) {
 749                 if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp))
 750                         goto out_err;
 751
 752                 dram_hole_base = tmp & GENMASK(31, 24);
 753                 if (ret_addr >= dram_hole_base)
 754                         ret_addr += (BIT_ULL(32) - dram_hole_base);
 755         }
 756
 757         if (hash_enabled) {
 758                 /* Save some parentheses and grab ls-bit at the end. */
 759                 hashed_bit =    (ret_addr >> 12) ^
 760                                 (ret_addr >> 18) ^
 761                                 (ret_addr >> 21) ^
 762                                 (ret_addr >> 30) ^
 763                                 cs_id;
 764
 765                 hashed_bit &= BIT(0);
 766
 767                 if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0)))
 768                         ret_addr ^= BIT(intlv_addr_bit);
 769         }
 770
 771         /* Is calculated system address is above DRAM limit address? */
 772         if (ret_addr > dram_limit_addr)
 773                 goto out_err;
 774
 775         *sys_addr = ret_addr;
 776         return 0;
 777
 778 out_err:
 779         return -EINVAL;
 780 }
 781 EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr);
 782
 783 bool amd_mce_is_memory_error(struct mce *m)
 784 {
 785         /* ErrCodeExt[20:16] */
 786         u8 xec = (m->status >> 16) & 0x1f;
 787
 788         if (mce_flags.smca)
 789                 return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0;
 790
 791         return m->bank == 4 && xec == 0x8;
 792 }
 793
 794 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
 795 {
 796         struct mce m;
 797
 798         mce_setup(&m);
 799
 800         m.status = status;
 801         m.misc   = misc;
 802         m.bank   = bank;
 803         m.tsc    = rdtsc();
 804
 805         if (m.status & MCI_STATUS_ADDRV) {
 806                 m.addr = addr;
 807
 808                 /*
 809                  * Extract [55:<lsb>] where lsb is the least significant
 810                  * *valid* bit of the address bits.
 811                  */
 812                 if (mce_flags.smca) {
 813                         u8 lsb = (m.addr >> 56) & 0x3f;
 814
 815                         m.addr &= GENMASK_ULL(55, lsb);
 816                 }
 817         }
 818
 819         if (mce_flags.smca) {
 820                 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid);
 821
 822                 if (m.status & MCI_STATUS_SYNDV)
 823                         rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd);
 824         }
 825
 826         mce_log(&m);
 827 }
 828
 829 asmlinkage __visible void __irq_entry smp_deferred_error_interrupt(void)
 830 {
 831         entering_irq();
 832         trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR);
 833         inc_irq_stat(irq_deferred_error_count);
 834         deferred_error_int_vector();
 835         trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR);
 836         exiting_ack_irq();
 837 }
 838
 839 /*
 840  * Returns true if the logged error is deferred. False, otherwise.
 841  */
 842 static inline bool
 843 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
 844 {
 845         u64 status, addr = 0;
 846
 847         rdmsrl(msr_stat, status);
 848         if (!(status & MCI_STATUS_VAL))
 849                 return false;
 850
 851         if (status & MCI_STATUS_ADDRV)
 852                 rdmsrl(msr_addr, addr);
 853
 854         __log_error(bank, status, addr, misc);
 855
 856         wrmsrl(msr_stat, 0);
 857
 858         return status & MCI_STATUS_DEFERRED;
 859 }
 860
 861 /*
 862  * We have three scenarios for checking for Deferred errors:
 863  *
 864  * 1) Non-SMCA systems check MCA_STATUS and log error if found.
 865  * 2) SMCA systems check MCA_STATUS. If error is found then log it and also
 866  *    clear MCA_DESTAT.
 867  * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and
 868  *    log it.
 869  */
 870 static void log_error_deferred(unsigned int bank)
 871 {
 872         bool defrd;
 873
 874         defrd = _log_error_bank(bank, msr_ops.status(bank),
 875                                         msr_ops.addr(bank), 0);
 876
 877         if (!mce_flags.smca)
 878                 return;
 879
 880         /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */
 881         if (defrd) {
 882                 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);
 883                 return;
 884         }
 885
 886         /*
 887          * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check
 888          * for a valid error.
 889          */
 890         _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank),
 891                               MSR_AMD64_SMCA_MCx_DEADDR(bank), 0);
 892 }
 893
 894 /* APIC interrupt handler for deferred errors */
 895 static void amd_deferred_error_interrupt(void)
 896 {
 897         unsigned int bank;
 898
 899         for (bank = 0; bank < mca_cfg.banks; ++bank)
 900                 log_error_deferred(bank);
 901 }
 902
 903 static void log_error_thresholding(unsigned int bank, u64 misc)
 904 {
 905         _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc);
 906 }
 907
 908 static void log_and_reset_block(struct threshold_block *block)
 909 {
 910         struct thresh_restart tr;
 911         u32 low = 0, high = 0;
 912
 913         if (!block)
 914                 return;
 915
 916         if (rdmsr_safe(block->address, &low, &high))
 917                 return;
 918
 919         if (!(high & MASK_OVERFLOW_HI))
 920                 return;
 921
 922         /* Log the MCE which caused the threshold event. */
 923         log_error_thresholding(block->bank, ((u64)high << 32) | low);
 924
 925         /* Reset threshold block after logging error. */
 926         memset(&tr, 0, sizeof(tr));
 927         tr.b = block;
 928         threshold_restart_bank(&tr);
 929 }
 930
 931 /*
 932  * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
 933  * goes off when error_count reaches threshold_limit.
 934  */
 935 static void amd_threshold_interrupt(void)
 936 {
 937         struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL;
 938         unsigned int bank, cpu = smp_processor_id();
 939
 940         for (bank = 0; bank < mca_cfg.banks; ++bank) {
 941                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
 942                         continue;
 943
 944                 first_block = per_cpu(threshold_banks, cpu)[bank]->blocks;
 945                 if (!first_block)
 946                         continue;
 947
 948                 /*
 949                  * The first block is also the head of the list. Check it first
 950                  * before iterating over the rest.
 951                  */
 952                 log_and_reset_block(first_block);
 953                 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj)
 954                         log_and_reset_block(block);
 955         }
 956 }
 957
 958 /*
 959  * Sysfs Interface
 960  */
 961
 962 struct threshold_attr {
 963         struct attribute attr;
 964         ssize_t (*show) (struct threshold_block *, char *);
 965         ssize_t (*store) (struct threshold_block *, const char *, size_t count);
 966 };
 967
 968 #define SHOW_FIELDS(name)                                               \
 969 static ssize_t show_ ## name(struct threshold_block *b, char *buf)      \
 970 {                                                                       \
 971         return sprintf(buf, "%lu\n", (unsigned long) b->name);          \
 972 }
 973 SHOW_FIELDS(interrupt_enable)
 974 SHOW_FIELDS(threshold_limit)
 975
 976 static ssize_t
 977 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
 978 {
 979         struct thresh_restart tr;
 980         unsigned long new;
 981
 982         if (!b->interrupt_capable)
 983                 return -EINVAL;
 984
 985         if (kstrtoul(buf, 0, &new) < 0)
 986                 return -EINVAL;
 987
 988         b->interrupt_enable = !!new;
 989
 990         memset(&tr, 0, sizeof(tr));
 991         tr.b            = b;
 992
 993         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
 994
 995         return size;
 996 }
 997
 998 static ssize_t
 999 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
1000 {
1001         struct thresh_restart tr;
1002         unsigned long new;
1003
1004         if (kstrtoul(buf, 0, &new) < 0)
1005                 return -EINVAL;
1006
1007         if (new > THRESHOLD_MAX)
1008                 new = THRESHOLD_MAX;
1009         if (new < 1)
1010                 new = 1;
1011
1012         memset(&tr, 0, sizeof(tr));
1013         tr.old_limit = b->threshold_limit;
1014         b->threshold_limit = new;
1015         tr.b = b;
1016
1017         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
1018
1019         return size;
1020 }
1021
1022 static ssize_t show_error_count(struct threshold_block *b, char *buf)
1023 {
1024         u32 lo, hi;
1025
1026         rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);
1027
1028         return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
1029                                      (THRESHOLD_MAX - b->threshold_limit)));
1030 }
1031
1032 static struct threshold_attr error_count = {
1033         .attr = {.name = __stringify(error_count), .mode = 0444 },
1034         .show = show_error_count,
1035 };
1036
1037 #define RW_ATTR(val)                                                    \
1038 static struct threshold_attr val = {                                    \
1039         .attr   = {.name = __stringify(val), .mode = 0644 },            \
1040         .show   = show_## val,                                          \
1041         .store  = store_## val,                                         \
1042 };
1043
1044 RW_ATTR(interrupt_enable);
1045 RW_ATTR(threshold_limit);
1046
1047 static struct attribute *default_attrs[] = {
1048         &threshold_limit.attr,
1049         &error_count.attr,
1050         NULL,   /* possibly interrupt_enable if supported, see below */
1051         NULL,
1052 };
1053
1054 #define to_block(k)     container_of(k, struct threshold_block, kobj)
1055 #define to_attr(a)      container_of(a, struct threshold_attr, attr)
1056
1057 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
1058 {
1059         struct threshold_block *b = to_block(kobj);
1060         struct threshold_attr *a = to_attr(attr);
1061         ssize_t ret;
1062
1063         ret = a->show ? a->show(b, buf) : -EIO;
1064
1065         return ret;
1066 }
1067
1068 static ssize_t store(struct kobject *kobj, struct attribute *attr,
1069                      const char *buf, size_t count)
1070 {
1071         struct threshold_block *b = to_block(kobj);
1072         struct threshold_attr *a = to_attr(attr);
1073         ssize_t ret;
1074
1075         ret = a->store ? a->store(b, buf, count) : -EIO;
1076
1077         return ret;
1078 }
1079
1080 static const struct sysfs_ops threshold_ops = {
1081         .show                   = show,
1082         .store                  = store,
1083 };
1084
1085 static struct kobj_type threshold_ktype = {
1086         .sysfs_ops              = &threshold_ops,
1087         .default_attrs          = default_attrs,
1088 };
1089
1090 static const char *get_name(unsigned int bank, struct threshold_block *b)
1091 {
1092         enum smca_bank_types bank_type;
1093
1094         if (!mce_flags.smca) {
1095                 if (b && bank == 4)
1096                         return bank4_names(b);
1097
1098                 return th_names[bank];
1099         }
1100
1101         bank_type = smca_get_bank_type(bank);
1102         if (bank_type >= N_SMCA_BANK_TYPES)
1103                 return NULL;
1104
1105         if (b && bank_type == SMCA_UMC) {
1106                 if (b->block < ARRAY_SIZE(smca_umc_block_names))
1107                         return smca_umc_block_names[b->block];
1108                 return NULL;
1109         }
1110
1111         if (smca_banks[bank].hwid->count == 1)
1112                 return smca_get_name(bank_type);
1113
1114         snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN,
1115                  "%s_%x", smca_get_name(bank_type),
1116                           smca_banks[bank].sysfs_id);
1117         return buf_mcatype;
1118 }
1119
1120 static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
1121                                      unsigned int block, u32 address)
1122 {
1123         struct threshold_block *b = NULL;
1124         u32 low, high;
1125         int err;
1126
1127         if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
1128                 return 0;
1129
1130         if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
1131                 return 0;
1132
1133         if (!(high & MASK_VALID_HI)) {
1134                 if (block)
1135                         goto recurse;
1136                 else
1137                         return 0;
1138         }
1139
1140         if (!(high & MASK_CNTP_HI)  ||
1141              (high & MASK_LOCKED_HI))
1142                 goto recurse;
1143
1144         b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
1145         if (!b)
1146                 return -ENOMEM;
1147
1148         b->block                = block;
1149         b->bank                 = bank;
1150         b->cpu                  = cpu;
1151         b->address              = address;
1152         b->interrupt_enable     = 0;
1153         b->interrupt_capable    = lvt_interrupt_supported(bank, high);
1154         b->threshold_limit      = THRESHOLD_MAX;
1155
1156         if (b->interrupt_capable) {
1157                 threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
1158                 b->interrupt_enable = 1;
1159         } else {
1160                 threshold_ktype.default_attrs[2] = NULL;
1161         }
1162
1163         INIT_LIST_HEAD(&b->miscj);
1164
1165         if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
1166                 list_add(&b->miscj,
1167                          &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
1168         } else {
1169                 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
1170         }
1171
1172         err = kobject_init_and_add(&b->kobj, &threshold_ktype,
1173                                    per_cpu(threshold_banks, cpu)[bank]->kobj,
1174                                    get_name(bank, b));
1175         if (err)
1176                 goto out_free;
1177 recurse:
1178         address = get_block_address(cpu, address, low, high, bank, ++block);
1179         if (!address)
1180                 return 0;
1181
1182         err = allocate_threshold_blocks(cpu, bank, block, address);
1183         if (err)
1184                 goto out_free;
1185
1186         if (b)
1187                 kobject_uevent(&b->kobj, KOBJ_ADD);
1188
1189         return err;
1190
1191 out_free:
1192         if (b) {
1193                 kobject_put(&b->kobj);
1194                 list_del(&b->miscj);
1195                 kfree(b);
1196         }
1197         return err;
1198 }
1199
1200 static int __threshold_add_blocks(struct threshold_bank *b)
1201 {
1202         struct list_head *head = &b->blocks->miscj;
1203         struct threshold_block *pos = NULL;
1204         struct threshold_block *tmp = NULL;
1205         int err = 0;
1206
1207         err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
1208         if (err)
1209                 return err;
1210
1211         list_for_each_entry_safe(pos, tmp, head, miscj) {
1212
1213                 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
1214                 if (err) {
1215                         list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
1216                                 kobject_del(&pos->kobj);
1217
1218                         return err;
1219                 }
1220         }
1221         return err;
1222 }
1223
1224 static int threshold_create_bank(unsigned int cpu, unsigned int bank)
1225 {
1226         struct device *dev = per_cpu(mce_device, cpu);
1227         struct amd_northbridge *nb = NULL;
1228         struct threshold_bank *b = NULL;
1229         const char *name = get_name(bank, NULL);
1230         int err = 0;
1231
1232         if (!dev)
1233                 return -ENODEV;
1234
1235         if (is_shared_bank(bank)) {
1236                 nb = node_to_amd_nb(amd_get_nb_id(cpu));
1237
1238                 /* threshold descriptor already initialized on this node? */
1239                 if (nb && nb->bank4) {
1240                         /* yes, use it */
1241                         b = nb->bank4;
1242                         err = kobject_add(b->kobj, &dev->kobj, name);
1243                         if (err)
1244                                 goto out;
1245
1246                         per_cpu(threshold_banks, cpu)[bank] = b;
1247                         refcount_inc(&b->cpus);
1248
1249                         err = __threshold_add_blocks(b);
1250
1251                         goto out;
1252                 }
1253         }
1254
1255         b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
1256         if (!b) {
1257                 err = -ENOMEM;
1258                 goto out;
1259         }
1260
1261         b->kobj = kobject_create_and_add(name, &dev->kobj);
1262         if (!b->kobj) {
1263                 err = -EINVAL;
1264                 goto out_free;
1265         }
1266
1267         per_cpu(threshold_banks, cpu)[bank] = b;
1268
1269         if (is_shared_bank(bank)) {
1270                 refcount_set(&b->cpus, 1);
1271
1272                 /* nb is already initialized, see above */
1273                 if (nb) {
1274                         WARN_ON(nb->bank4);
1275                         nb->bank4 = b;
1276                 }
1277         }
1278
1279         err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank));
1280         if (!err)
1281                 goto out;
1282
1283  out_free:
1284         kfree(b);
1285
1286  out:
1287         return err;
1288 }
1289
1290 static void deallocate_threshold_block(unsigned int cpu,
1291                                                  unsigned int bank)
1292 {
1293         struct threshold_block *pos = NULL;
1294         struct threshold_block *tmp = NULL;
1295         struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
1296
1297         if (!head)
1298                 return;
1299
1300         list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
1301                 kobject_put(&pos->kobj);
1302                 list_del(&pos->miscj);
1303                 kfree(pos);
1304         }
1305
1306         kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
1307         per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
1308 }
1309
1310 static void __threshold_remove_blocks(struct threshold_bank *b)
1311 {
1312         struct threshold_block *pos = NULL;
1313         struct threshold_block *tmp = NULL;
1314
1315         kobject_del(b->kobj);
1316
1317         list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
1318                 kobject_del(&pos->kobj);
1319 }
1320
1321 static void threshold_remove_bank(unsigned int cpu, int bank)
1322 {
1323         struct amd_northbridge *nb;
1324         struct threshold_bank *b;
1325
1326         b = per_cpu(threshold_banks, cpu)[bank];
1327         if (!b)
1328                 return;
1329
1330         if (!b->blocks)
1331                 goto free_out;
1332
1333         if (is_shared_bank(bank)) {
1334                 if (!refcount_dec_and_test(&b->cpus)) {
1335                         __threshold_remove_blocks(b);
1336                         per_cpu(threshold_banks, cpu)[bank] = NULL;
1337                         return;
1338                 } else {
1339                         /*
1340                          * the last CPU on this node using the shared bank is
1341                          * going away, remove that bank now.
1342                          */
1343                         nb = node_to_amd_nb(amd_get_nb_id(cpu));
1344                         nb->bank4 = NULL;
1345                 }
1346         }
1347
1348         deallocate_threshold_block(cpu, bank);
1349
1350 free_out:
1351         kobject_del(b->kobj);
1352         kobject_put(b->kobj);
1353         kfree(b);
1354         per_cpu(threshold_banks, cpu)[bank] = NULL;
1355 }
1356
1357 int mce_threshold_remove_device(unsigned int cpu)
1358 {
1359         unsigned int bank;
1360
1361         if (!thresholding_en)
1362                 return 0;
1363
1364         for (bank = 0; bank < mca_cfg.banks; ++bank) {
1365                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1366                         continue;
1367                 threshold_remove_bank(cpu, bank);
1368         }
1369         kfree(per_cpu(threshold_banks, cpu));
1370         per_cpu(threshold_banks, cpu) = NULL;
1371         return 0;
1372 }
1373
1374 /* create dir/files for all valid threshold banks */
1375 int mce_threshold_create_device(unsigned int cpu)
1376 {
1377         unsigned int bank;
1378         struct threshold_bank **bp;
1379         int err = 0;
1380
1381         if (!thresholding_en)
1382                 return 0;
1383
1384         bp = per_cpu(threshold_banks, cpu);
1385         if (bp)
1386                 return 0;
1387
1388         bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks,
1389                      GFP_KERNEL);
1390         if (!bp)
1391                 return -ENOMEM;
1392
1393         per_cpu(threshold_banks, cpu) = bp;
1394
1395         for (bank = 0; bank < mca_cfg.banks; ++bank) {
1396                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1397                         continue;
1398                 err = threshold_create_bank(cpu, bank);
1399                 if (err)
1400                         goto err;
1401         }
1402         return err;
1403 err:
1404         mce_threshold_remove_device(cpu);
1405         return err;
1406 }
1407
1408 static __init int threshold_init_device(void)
1409 {
1410         unsigned lcpu = 0;
1411
1412         if (mce_threshold_vector == amd_threshold_interrupt)
1413                 thresholding_en = true;
1414
1415         /* to hit CPUs online before the notifier is up */
1416         for_each_online_cpu(lcpu) {
1417                 int err = mce_threshold_create_device(lcpu);
1418
1419                 if (err)
1420                         return err;
1421         }
1422
1423         return 0;
1424 }
1425 /*
1426  * there are 3 funcs which need to be _initcalled in a logic sequence:
1427  * 1. xen_late_init_mcelog
1428  * 2. mcheck_init_device
1429  * 3. threshold_init_device
1430  *
1431  * xen_late_init_mcelog must register xen_mce_chrdev_device before
1432  * native mce_chrdev_device registration if running under xen platform;
1433  *
1434  * mcheck_init_device should be inited before threshold_init_device to
1435  * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
1436  *
1437  * so we use following _initcalls
1438  * 1. device_initcall(xen_late_init_mcelog);
1439  * 2. device_initcall_sync(mcheck_init_device);
1440  * 3. late_initcall(threshold_init_device);
1441  *
1442  * when running under xen, the initcall order is 1,2,3;
1443  * on baremetal, we skip 1 and we do only 2 and 3.
1444  */
1445 late_initcall(threshold_init_device);