2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/thread_info.h>
14 #include <linux/capability.h>
15 #include <linux/miscdevice.h>
16 #include <linux/ratelimit.h>
17 #include <linux/rcupdate.h>
18 #include <linux/kobject.h>
19 #include <linux/uaccess.h>
20 #include <linux/kdebug.h>
21 #include <linux/kernel.h>
22 #include <linux/percpu.h>
23 #include <linux/string.h>
24 #include <linux/device.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/delay.h>
27 #include <linux/ctype.h>
28 #include <linux/sched.h>
29 #include <linux/sysfs.h>
30 #include <linux/types.h>
31 #include <linux/slab.h>
32 #include <linux/init.h>
33 #include <linux/kmod.h>
34 #include <linux/poll.h>
35 #include <linux/nmi.h>
36 #include <linux/cpu.h>
37 #include <linux/ras.h>
38 #include <linux/smp.h>
41 #include <linux/debugfs.h>
42 #include <linux/irq_work.h>
43 #include <linux/export.h>
44 #include <linux/jump_label.h>
45 #include <linux/set_memory.h>
47 #include <asm/intel-family.h>
48 #include <asm/processor.h>
49 #include <asm/traps.h>
50 #include <asm/tlbflush.h>
53 #include <asm/reboot.h>
55 #include "mce-internal.h"
57 static DEFINE_MUTEX(mce_log_mutex);
59 /* sysfs synchronization */
60 static DEFINE_MUTEX(mce_sysfs_mutex);
62 #define CREATE_TRACE_POINTS
63 #include <trace/events/mce.h>
65 #define SPINUNIT 100 /* 100ns */
67 DEFINE_PER_CPU(unsigned, mce_exception_count);
69 struct mce_bank *mce_banks __read_mostly;
70 struct mce_vendor_flags mce_flags __read_mostly;
72 struct mca_config mca_cfg __read_mostly = {
76 * 0: always panic on uncorrected errors, log corrected errors
77 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
78 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
79 * 3: never panic or SIGBUS, log all errors (for testing only)
85 static DEFINE_PER_CPU(struct mce, mces_seen);
86 static unsigned long mce_need_notify;
87 static int cpu_missing;
90 * MCA banks polled by the period polling timer for corrected events.
91 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
93 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
94 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
98 * MCA banks controlled through firmware first for corrected errors.
99 * This is a global list of banks for which we won't enable CMCI and we
100 * won't poll. Firmware controls these banks and is responsible for
101 * reporting corrected errors through GHES. Uncorrected/recoverable
102 * errors are still notified through a machine check.
104 mce_banks_t mce_banks_ce_disabled;
106 static struct work_struct mce_work;
107 static struct irq_work mce_irq_work;
109 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
112 * CPU/chipset specific EDAC code can register a notifier call here to print
113 * MCE errors in a human-readable form.
115 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
117 /* Do initial initialization of a struct mce */
118 void mce_setup(struct mce *m)
120 memset(m, 0, sizeof(struct mce));
121 m->cpu = m->extcpu = smp_processor_id();
122 /* need the internal __ version to avoid deadlocks */
123 m->time = __ktime_get_real_seconds();
124 m->cpuvendor = boot_cpu_data.x86_vendor;
125 m->cpuid = cpuid_eax(1);
126 m->socketid = cpu_data(m->extcpu).phys_proc_id;
127 m->apicid = cpu_data(m->extcpu).initial_apicid;
128 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
130 if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
131 rdmsrl(MSR_PPIN, m->ppin);
133 m->microcode = boot_cpu_data.microcode;
136 DEFINE_PER_CPU(struct mce, injectm);
137 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
139 void mce_log(struct mce *m)
141 if (!mce_gen_pool_add(m))
142 irq_work_queue(&mce_irq_work);
145 void mce_inject_log(struct mce *m)
147 mutex_lock(&mce_log_mutex);
149 mutex_unlock(&mce_log_mutex);
151 EXPORT_SYMBOL_GPL(mce_inject_log);
153 static struct notifier_block mce_srao_nb;
156 * We run the default notifier if we have only the SRAO, the first and the
157 * default notifier registered. I.e., the mandatory NUM_DEFAULT_NOTIFIERS
158 * notifiers registered on the chain.
160 #define NUM_DEFAULT_NOTIFIERS 3
161 static atomic_t num_notifiers;
163 void mce_register_decode_chain(struct notifier_block *nb)
165 if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC))
168 atomic_inc(&num_notifiers);
170 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
172 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
174 void mce_unregister_decode_chain(struct notifier_block *nb)
176 atomic_dec(&num_notifiers);
178 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
180 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
182 static inline u32 ctl_reg(int bank)
184 return MSR_IA32_MCx_CTL(bank);
187 static inline u32 status_reg(int bank)
189 return MSR_IA32_MCx_STATUS(bank);
192 static inline u32 addr_reg(int bank)
194 return MSR_IA32_MCx_ADDR(bank);
197 static inline u32 misc_reg(int bank)
199 return MSR_IA32_MCx_MISC(bank);
202 static inline u32 smca_ctl_reg(int bank)
204 return MSR_AMD64_SMCA_MCx_CTL(bank);
207 static inline u32 smca_status_reg(int bank)
209 return MSR_AMD64_SMCA_MCx_STATUS(bank);
212 static inline u32 smca_addr_reg(int bank)
214 return MSR_AMD64_SMCA_MCx_ADDR(bank);
217 static inline u32 smca_misc_reg(int bank)
219 return MSR_AMD64_SMCA_MCx_MISC(bank);
222 struct mca_msr_regs msr_ops = {
224 .status = status_reg,
229 static void __print_mce(struct mce *m)
231 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
233 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
234 m->mcgstatus, m->bank, m->status);
237 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
238 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
241 if (m->cs == __KERNEL_CS)
242 pr_cont("{%pS}", (void *)(unsigned long)m->ip);
246 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
248 pr_cont("ADDR %llx ", m->addr);
250 pr_cont("MISC %llx ", m->misc);
252 if (mce_flags.smca) {
254 pr_cont("SYND %llx ", m->synd);
256 pr_cont("IPID %llx ", m->ipid);
261 * Note this output is parsed by external tools and old fields
262 * should not be changed.
264 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
265 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
269 static void print_mce(struct mce *m)
273 if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON)
274 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
277 #define PANIC_TIMEOUT 5 /* 5 seconds */
279 static atomic_t mce_panicked;
281 static int fake_panic;
282 static atomic_t mce_fake_panicked;
284 /* Panic in progress. Enable interrupts and wait for final IPI */
285 static void wait_for_panic(void)
287 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
291 while (timeout-- > 0)
293 if (panic_timeout == 0)
294 panic_timeout = mca_cfg.panic_timeout;
295 panic("Panicing machine check CPU died");
298 static void mce_panic(const char *msg, struct mce *final, char *exp)
301 struct llist_node *pending;
302 struct mce_evt_llist *l;
306 * Make sure only one CPU runs in machine check panic
308 if (atomic_inc_return(&mce_panicked) > 1)
315 /* Don't log too much for fake panic */
316 if (atomic_inc_return(&mce_fake_panicked) > 1)
319 pending = mce_gen_pool_prepare_records();
320 /* First print corrected ones that are still unlogged */
321 llist_for_each_entry(l, pending, llnode) {
322 struct mce *m = &l->mce;
323 if (!(m->status & MCI_STATUS_UC)) {
326 apei_err = apei_write_mce(m);
329 /* Now print uncorrected but with the final one last */
330 llist_for_each_entry(l, pending, llnode) {
331 struct mce *m = &l->mce;
332 if (!(m->status & MCI_STATUS_UC))
334 if (!final || mce_cmp(m, final)) {
337 apei_err = apei_write_mce(m);
343 apei_err = apei_write_mce(final);
346 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
348 pr_emerg(HW_ERR "Machine check: %s\n", exp);
350 if (panic_timeout == 0)
351 panic_timeout = mca_cfg.panic_timeout;
354 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
357 /* Support code for software error injection */
359 static int msr_to_offset(u32 msr)
361 unsigned bank = __this_cpu_read(injectm.bank);
363 if (msr == mca_cfg.rip_msr)
364 return offsetof(struct mce, ip);
365 if (msr == msr_ops.status(bank))
366 return offsetof(struct mce, status);
367 if (msr == msr_ops.addr(bank))
368 return offsetof(struct mce, addr);
369 if (msr == msr_ops.misc(bank))
370 return offsetof(struct mce, misc);
371 if (msr == MSR_IA32_MCG_STATUS)
372 return offsetof(struct mce, mcgstatus);
376 /* MSR access wrappers used for error injection */
377 static u64 mce_rdmsrl(u32 msr)
381 if (__this_cpu_read(injectm.finished)) {
382 int offset = msr_to_offset(msr);
386 return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
389 if (rdmsrl_safe(msr, &v)) {
390 WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr);
392 * Return zero in case the access faulted. This should
393 * not happen normally but can happen if the CPU does
394 * something weird, or if the code is buggy.
402 static void mce_wrmsrl(u32 msr, u64 v)
404 if (__this_cpu_read(injectm.finished)) {
405 int offset = msr_to_offset(msr);
408 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
415 * Collect all global (w.r.t. this processor) status about this machine
416 * check into our "mce" struct so that we can use it later to assess
417 * the severity of the problem as we read per-bank specific details.
419 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
423 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
426 * Get the address of the instruction at the time of
427 * the machine check error.
429 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
434 * When in VM86 mode make the cs look like ring 3
435 * always. This is a lie, but it's better than passing
436 * the additional vm86 bit around everywhere.
438 if (v8086_mode(regs))
441 /* Use accurate RIP reporting if available. */
443 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
447 int mce_available(struct cpuinfo_x86 *c)
449 if (mca_cfg.disabled)
451 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
454 static void mce_schedule_work(void)
456 if (!mce_gen_pool_empty())
457 schedule_work(&mce_work);
460 static void mce_irq_work_cb(struct irq_work *entry)
465 static void mce_report_event(struct pt_regs *regs)
467 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
470 * Triggering the work queue here is just an insurance
471 * policy in case the syscall exit notify handler
472 * doesn't run soon enough or ends up running on the
473 * wrong CPU (can happen when audit sleeps)
479 irq_work_queue(&mce_irq_work);
483 * Check if the address reported by the CPU is in a format we can parse.
484 * It would be possible to add code for most other cases, but all would
485 * be somewhat complicated (e.g. segment offset would require an instruction
486 * parser). So only support physical addresses up to page granuality for now.
488 static int mce_usable_address(struct mce *m)
490 if (!(m->status & MCI_STATUS_ADDRV))
493 /* Checks after this one are Intel-specific: */
494 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
497 if (!(m->status & MCI_STATUS_MISCV))
500 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
503 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
509 bool mce_is_memory_error(struct mce *m)
511 if (m->cpuvendor == X86_VENDOR_AMD ||
512 m->cpuvendor == X86_VENDOR_HYGON) {
513 return amd_mce_is_memory_error(m);
514 } else if (m->cpuvendor == X86_VENDOR_INTEL) {
516 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
518 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
519 * indicating a memory error. Bit 8 is used for indicating a
520 * cache hierarchy error. The combination of bit 2 and bit 3
521 * is used for indicating a `generic' cache hierarchy error
522 * But we can't just blindly check the above bits, because if
523 * bit 11 is set, then it is a bus/interconnect error - and
524 * either way the above bits just gives more detail on what
525 * bus/interconnect error happened. Note that bit 12 can be
526 * ignored, as it's the "filter" bit.
528 return (m->status & 0xef80) == BIT(7) ||
529 (m->status & 0xef00) == BIT(8) ||
530 (m->status & 0xeffc) == 0xc;
535 EXPORT_SYMBOL_GPL(mce_is_memory_error);
537 static bool mce_is_correctable(struct mce *m)
539 if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
542 if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED)
545 if (m->status & MCI_STATUS_UC)
551 static bool cec_add_mce(struct mce *m)
556 /* We eat only correctable DRAM errors with usable addresses. */
557 if (mce_is_memory_error(m) &&
558 mce_is_correctable(m) &&
559 mce_usable_address(m))
560 if (!cec_add_elem(m->addr >> PAGE_SHIFT))
566 static int mce_first_notifier(struct notifier_block *nb, unsigned long val,
569 struct mce *m = (struct mce *)data;
577 /* Emit the trace record: */
580 set_bit(0, &mce_need_notify);
587 static struct notifier_block first_nb = {
588 .notifier_call = mce_first_notifier,
589 .priority = MCE_PRIO_FIRST,
592 static int srao_decode_notifier(struct notifier_block *nb, unsigned long val,
595 struct mce *mce = (struct mce *)data;
601 if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) {
602 pfn = mce->addr >> PAGE_SHIFT;
603 if (!memory_failure(pfn, 0))
609 static struct notifier_block mce_srao_nb = {
610 .notifier_call = srao_decode_notifier,
611 .priority = MCE_PRIO_SRAO,
614 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
617 struct mce *m = (struct mce *)data;
622 if (atomic_read(&num_notifiers) > NUM_DEFAULT_NOTIFIERS)
630 static struct notifier_block mce_default_nb = {
631 .notifier_call = mce_default_notifier,
632 /* lowest prio, we want it to run last. */
633 .priority = MCE_PRIO_LOWEST,
637 * Read ADDR and MISC registers.
639 static void mce_read_aux(struct mce *m, int i)
641 if (m->status & MCI_STATUS_MISCV)
642 m->misc = mce_rdmsrl(msr_ops.misc(i));
644 if (m->status & MCI_STATUS_ADDRV) {
645 m->addr = mce_rdmsrl(msr_ops.addr(i));
648 * Mask the reported address by the reported granularity.
650 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
651 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
657 * Extract [55:<lsb>] where lsb is the least significant
658 * *valid* bit of the address bits.
660 if (mce_flags.smca) {
661 u8 lsb = (m->addr >> 56) & 0x3f;
663 m->addr &= GENMASK_ULL(55, lsb);
667 if (mce_flags.smca) {
668 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
670 if (m->status & MCI_STATUS_SYNDV)
671 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
675 DEFINE_PER_CPU(unsigned, mce_poll_count);
678 * Poll for corrected events or events that happened before reset.
679 * Those are just logged through /dev/mcelog.
681 * This is executed in standard interrupt context.
683 * Note: spec recommends to panic for fatal unsignalled
684 * errors here. However this would be quite problematic --
685 * we would need to reimplement the Monarch handling and
686 * it would mess up the exclusion between exception handler
687 * and poll hander -- * so we skip this for now.
688 * These cases should not happen anyways, or only when the CPU
689 * is already totally * confused. In this case it's likely it will
690 * not fully execute the machine check handler either.
692 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
694 bool error_seen = false;
698 this_cpu_inc(mce_poll_count);
700 mce_gather_info(&m, NULL);
702 if (flags & MCP_TIMESTAMP)
705 for (i = 0; i < mca_cfg.banks; i++) {
706 if (!mce_banks[i].ctl || !test_bit(i, *b))
714 m.status = mce_rdmsrl(msr_ops.status(i));
715 if (!(m.status & MCI_STATUS_VAL))
719 * Uncorrected or signalled events are handled by the exception
720 * handler when it is enabled, so don't process those here.
722 * TBD do the same check for MCI_STATUS_EN here?
724 if (!(flags & MCP_UC) &&
725 (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC)))
732 m.severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
735 * Don't get the IP here because it's unlikely to
736 * have anything to do with the actual error location.
738 if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce)
740 else if (mce_usable_address(&m)) {
742 * Although we skipped logging this, we still want
743 * to take action. Add to the pool so the registered
744 * notifiers will see it.
746 if (!mce_gen_pool_add(&m))
751 * Clear state for this bank.
753 mce_wrmsrl(msr_ops.status(i), 0);
757 * Don't clear MCG_STATUS here because it's only defined for
765 EXPORT_SYMBOL_GPL(machine_check_poll);
768 * Do a quick check if any of the events requires a panic.
769 * This decides if we keep the events around or clear them.
771 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
772 struct pt_regs *regs)
777 for (i = 0; i < mca_cfg.banks; i++) {
778 m->status = mce_rdmsrl(msr_ops.status(i));
779 if (!(m->status & MCI_STATUS_VAL))
782 __set_bit(i, validp);
783 if (quirk_no_way_out)
784 quirk_no_way_out(i, m, regs);
786 if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
796 * Variable to establish order between CPUs while scanning.
797 * Each CPU spins initially until executing is equal its number.
799 static atomic_t mce_executing;
802 * Defines order of CPUs on entry. First CPU becomes Monarch.
804 static atomic_t mce_callin;
807 * Check if a timeout waiting for other CPUs happened.
809 static int mce_timed_out(u64 *t, const char *msg)
812 * The others already did panic for some reason.
813 * Bail out like in a timeout.
814 * rmb() to tell the compiler that system_state
815 * might have been modified by someone else.
818 if (atomic_read(&mce_panicked))
820 if (!mca_cfg.monarch_timeout)
822 if ((s64)*t < SPINUNIT) {
823 if (mca_cfg.tolerant <= 1)
824 mce_panic(msg, NULL, NULL);
830 touch_nmi_watchdog();
835 * The Monarch's reign. The Monarch is the CPU who entered
836 * the machine check handler first. It waits for the others to
837 * raise the exception too and then grades them. When any
838 * error is fatal panic. Only then let the others continue.
840 * The other CPUs entering the MCE handler will be controlled by the
841 * Monarch. They are called Subjects.
843 * This way we prevent any potential data corruption in a unrecoverable case
844 * and also makes sure always all CPU's errors are examined.
846 * Also this detects the case of a machine check event coming from outer
847 * space (not detected by any CPUs) In this case some external agent wants
848 * us to shut down, so panic too.
850 * The other CPUs might still decide to panic if the handler happens
851 * in a unrecoverable place, but in this case the system is in a semi-stable
852 * state and won't corrupt anything by itself. It's ok to let the others
853 * continue for a bit first.
855 * All the spin loops have timeouts; when a timeout happens a CPU
856 * typically elects itself to be Monarch.
858 static void mce_reign(void)
861 struct mce *m = NULL;
862 int global_worst = 0;
867 * This CPU is the Monarch and the other CPUs have run
868 * through their handlers.
869 * Grade the severity of the errors of all the CPUs.
871 for_each_possible_cpu(cpu) {
872 int severity = mce_severity(&per_cpu(mces_seen, cpu),
875 if (severity > global_worst) {
877 global_worst = severity;
878 m = &per_cpu(mces_seen, cpu);
883 * Cannot recover? Panic here then.
884 * This dumps all the mces in the log buffer and stops the
887 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
888 mce_panic("Fatal machine check", m, msg);
891 * For UC somewhere we let the CPU who detects it handle it.
892 * Also must let continue the others, otherwise the handling
893 * CPU could deadlock on a lock.
897 * No machine check event found. Must be some external
898 * source or one CPU is hung. Panic.
900 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
901 mce_panic("Fatal machine check from unknown source", NULL, NULL);
904 * Now clear all the mces_seen so that they don't reappear on
907 for_each_possible_cpu(cpu)
908 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
911 static atomic_t global_nwo;
914 * Start of Monarch synchronization. This waits until all CPUs have
915 * entered the exception handler and then determines if any of them
916 * saw a fatal event that requires panic. Then it executes them
917 * in the entry order.
918 * TBD double check parallel CPU hotunplug
920 static int mce_start(int *no_way_out)
923 int cpus = num_online_cpus();
924 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
929 atomic_add(*no_way_out, &global_nwo);
931 * Rely on the implied barrier below, such that global_nwo
932 * is updated before mce_callin.
934 order = atomic_inc_return(&mce_callin);
939 while (atomic_read(&mce_callin) != cpus) {
940 if (mce_timed_out(&timeout,
941 "Timeout: Not all CPUs entered broadcast exception handler")) {
942 atomic_set(&global_nwo, 0);
949 * mce_callin should be read before global_nwo
955 * Monarch: Starts executing now, the others wait.
957 atomic_set(&mce_executing, 1);
960 * Subject: Now start the scanning loop one by one in
961 * the original callin order.
962 * This way when there are any shared banks it will be
963 * only seen by one CPU before cleared, avoiding duplicates.
965 while (atomic_read(&mce_executing) < order) {
966 if (mce_timed_out(&timeout,
967 "Timeout: Subject CPUs unable to finish machine check processing")) {
968 atomic_set(&global_nwo, 0);
976 * Cache the global no_way_out state.
978 *no_way_out = atomic_read(&global_nwo);
984 * Synchronize between CPUs after main scanning loop.
985 * This invokes the bulk of the Monarch processing.
987 static int mce_end(int order)
990 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
998 * Allow others to run.
1000 atomic_inc(&mce_executing);
1003 /* CHECKME: Can this race with a parallel hotplug? */
1004 int cpus = num_online_cpus();
1007 * Monarch: Wait for everyone to go through their scanning
1010 while (atomic_read(&mce_executing) <= cpus) {
1011 if (mce_timed_out(&timeout,
1012 "Timeout: Monarch CPU unable to finish machine check processing"))
1022 * Subject: Wait for Monarch to finish.
1024 while (atomic_read(&mce_executing) != 0) {
1025 if (mce_timed_out(&timeout,
1026 "Timeout: Monarch CPU did not finish machine check processing"))
1032 * Don't reset anything. That's done by the Monarch.
1038 * Reset all global state.
1041 atomic_set(&global_nwo, 0);
1042 atomic_set(&mce_callin, 0);
1046 * Let others run again.
1048 atomic_set(&mce_executing, 0);
1052 static void mce_clear_state(unsigned long *toclear)
1056 for (i = 0; i < mca_cfg.banks; i++) {
1057 if (test_bit(i, toclear))
1058 mce_wrmsrl(msr_ops.status(i), 0);
1062 static int do_memory_failure(struct mce *m)
1064 int flags = MF_ACTION_REQUIRED;
1067 pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr);
1068 if (!(m->mcgstatus & MCG_STATUS_RIPV))
1069 flags |= MF_MUST_KILL;
1070 ret = memory_failure(m->addr >> PAGE_SHIFT, flags);
1072 pr_err("Memory error not recovered");
1074 set_mce_nospec(m->addr >> PAGE_SHIFT);
1080 * Cases where we avoid rendezvous handler timeout:
1081 * 1) If this CPU is offline.
1083 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1084 * skip those CPUs which remain looping in the 1st kernel - see
1085 * crash_nmi_callback().
1087 * Note: there still is a small window between kexec-ing and the new,
1088 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1089 * might not get handled properly.
1091 static bool __mc_check_crashing_cpu(int cpu)
1093 if (cpu_is_offline(cpu) ||
1094 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1097 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
1098 if (mcgstatus & MCG_STATUS_RIPV) {
1099 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1106 static void __mc_scan_banks(struct mce *m, struct mce *final,
1107 unsigned long *toclear, unsigned long *valid_banks,
1108 int no_way_out, int *worst)
1110 struct mca_config *cfg = &mca_cfg;
1113 for (i = 0; i < cfg->banks; i++) {
1114 __clear_bit(i, toclear);
1115 if (!test_bit(i, valid_banks))
1118 if (!mce_banks[i].ctl)
1125 m->status = mce_rdmsrl(msr_ops.status(i));
1126 if (!(m->status & MCI_STATUS_VAL))
1130 * Corrected or non-signaled errors are handled by
1131 * machine_check_poll(). Leave them alone, unless this panics.
1133 if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1137 /* Set taint even when machine check was not enabled. */
1138 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1140 severity = mce_severity(m, cfg->tolerant, NULL, true);
1143 * When machine check was for corrected/deferred handler don't
1144 * touch, unless we're panicking.
1146 if ((severity == MCE_KEEP_SEVERITY ||
1147 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1150 __set_bit(i, toclear);
1152 /* Machine check event was not enabled. Clear, but ignore. */
1153 if (severity == MCE_NO_SEVERITY)
1158 /* assuming valid severity level != 0 */
1159 m->severity = severity;
1163 if (severity > *worst) {
1169 /* mce_clear_state will clear *final, save locally for use later */
1174 * The actual machine check handler. This only handles real
1175 * exceptions when something got corrupted coming in through int 18.
1177 * This is executed in NMI context not subject to normal locking rules. This
1178 * implies that most kernel services cannot be safely used. Don't even
1179 * think about putting a printk in there!
1181 * On Intel systems this is entered on all CPUs in parallel through
1182 * MCE broadcast. However some CPUs might be broken beyond repair,
1183 * so be always careful when synchronizing with others.
1185 void do_machine_check(struct pt_regs *regs, long error_code)
1187 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1188 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1189 struct mca_config *cfg = &mca_cfg;
1190 int cpu = smp_processor_id();
1191 char *msg = "Unknown";
1192 struct mce m, *final;
1196 * Establish sequential order between the CPUs entering the machine
1202 * If no_way_out gets set, there is no safe way to recover from this
1203 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1208 * If kill_it gets set, there might be a way to recover from this
1214 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1219 if (__mc_check_crashing_cpu(cpu))
1224 this_cpu_inc(mce_exception_count);
1226 mce_gather_info(&m, regs);
1229 final = this_cpu_ptr(&mces_seen);
1232 memset(valid_banks, 0, sizeof(valid_banks));
1233 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1238 * When no restart IP might need to kill or panic.
1239 * Assume the worst for now, but if we find the
1240 * severity is MCE_AR_SEVERITY we have other options.
1242 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1246 * Check if this MCE is signaled to only this logical processor,
1249 if (m.cpuvendor == X86_VENDOR_INTEL)
1250 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1253 * Local machine check may already know that we have to panic.
1254 * Broadcast machine check begins rendezvous in mce_start()
1255 * Go through all banks in exclusion of the other CPUs. This way we
1256 * don't report duplicated events on shared banks because the first one
1257 * to see it will clear it.
1261 mce_panic("Fatal local machine check", &m, msg);
1263 order = mce_start(&no_way_out);
1266 __mc_scan_banks(&m, final, toclear, valid_banks, no_way_out, &worst);
1269 mce_clear_state(toclear);
1272 * Do most of the synchronization with other CPUs.
1273 * When there's any problem use only local no_way_out state.
1276 if (mce_end(order) < 0)
1277 no_way_out = worst >= MCE_PANIC_SEVERITY;
1280 * If there was a fatal machine check we should have
1281 * already called mce_panic earlier in this function.
1282 * Since we re-read the banks, we might have found
1283 * something new. Check again to see if we found a
1284 * fatal error. We call "mce_severity()" again to
1285 * make sure we have the right "msg".
1287 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) {
1288 mce_severity(&m, cfg->tolerant, &msg, true);
1289 mce_panic("Local fatal machine check!", &m, msg);
1294 * If tolerant is at an insane level we drop requests to kill
1295 * processes and continue even when there is no way out.
1297 if (cfg->tolerant == 3)
1299 else if (no_way_out)
1300 mce_panic("Fatal machine check on current CPU", &m, msg);
1303 mce_report_event(regs);
1304 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1308 if (worst != MCE_AR_SEVERITY && !kill_it)
1311 /* Fault was in user mode and we need to take some action */
1312 if ((m.cs & 3) == 3) {
1313 ist_begin_non_atomic(regs);
1316 if (kill_it || do_memory_failure(&m))
1317 force_sig(SIGBUS, current);
1318 local_irq_disable();
1319 ist_end_non_atomic();
1321 if (!fixup_exception(regs, X86_TRAP_MC, error_code, 0))
1322 mce_panic("Failed kernel mode recovery", &m, NULL);
1328 EXPORT_SYMBOL_GPL(do_machine_check);
1330 #ifndef CONFIG_MEMORY_FAILURE
1331 int memory_failure(unsigned long pfn, int flags)
1333 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1334 BUG_ON(flags & MF_ACTION_REQUIRED);
1335 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1336 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1344 * Periodic polling timer for "silent" machine check errors. If the
1345 * poller finds an MCE, poll 2x faster. When the poller finds no more
1346 * errors, poll 2x slower (up to check_interval seconds).
1348 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1350 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1351 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1353 static unsigned long mce_adjust_timer_default(unsigned long interval)
1358 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1360 static void __start_timer(struct timer_list *t, unsigned long interval)
1362 unsigned long when = jiffies + interval;
1363 unsigned long flags;
1365 local_irq_save(flags);
1367 if (!timer_pending(t) || time_before(when, t->expires))
1368 mod_timer(t, round_jiffies(when));
1370 local_irq_restore(flags);
1373 static void mce_timer_fn(struct timer_list *t)
1375 struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
1378 WARN_ON(cpu_t != t);
1380 iv = __this_cpu_read(mce_next_interval);
1382 if (mce_available(this_cpu_ptr(&cpu_info))) {
1383 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1385 if (mce_intel_cmci_poll()) {
1386 iv = mce_adjust_timer(iv);
1392 * Alert userspace if needed. If we logged an MCE, reduce the polling
1393 * interval, otherwise increase the polling interval.
1395 if (mce_notify_irq())
1396 iv = max(iv / 2, (unsigned long) HZ/100);
1398 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1401 __this_cpu_write(mce_next_interval, iv);
1402 __start_timer(t, iv);
1406 * Ensure that the timer is firing in @interval from now.
1408 void mce_timer_kick(unsigned long interval)
1410 struct timer_list *t = this_cpu_ptr(&mce_timer);
1411 unsigned long iv = __this_cpu_read(mce_next_interval);
1413 __start_timer(t, interval);
1416 __this_cpu_write(mce_next_interval, interval);
1419 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1420 static void mce_timer_delete_all(void)
1424 for_each_online_cpu(cpu)
1425 del_timer_sync(&per_cpu(mce_timer, cpu));
1429 * Notify the user(s) about new machine check events.
1430 * Can be called from interrupt context, but not from machine check/NMI
1433 int mce_notify_irq(void)
1435 /* Not more than two messages every minute */
1436 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1438 if (test_and_clear_bit(0, &mce_need_notify)) {
1441 if (__ratelimit(&ratelimit))
1442 pr_info(HW_ERR "Machine check events logged\n");
1448 EXPORT_SYMBOL_GPL(mce_notify_irq);
1450 static int __mcheck_cpu_mce_banks_init(void)
1453 u8 num_banks = mca_cfg.banks;
1455 mce_banks = kcalloc(num_banks, sizeof(struct mce_bank), GFP_KERNEL);
1459 for (i = 0; i < num_banks; i++) {
1460 struct mce_bank *b = &mce_banks[i];
1469 * Initialize Machine Checks for a CPU.
1471 static int __mcheck_cpu_cap_init(void)
1476 rdmsrl(MSR_IA32_MCG_CAP, cap);
1478 b = cap & MCG_BANKCNT_MASK;
1480 pr_info("CPU supports %d MCE banks\n", b);
1482 if (b > MAX_NR_BANKS) {
1483 pr_warn("Using only %u machine check banks out of %u\n",
1488 /* Don't support asymmetric configurations today */
1489 WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks);
1493 int err = __mcheck_cpu_mce_banks_init();
1499 /* Use accurate RIP reporting if available. */
1500 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1501 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1503 if (cap & MCG_SER_P)
1509 static void __mcheck_cpu_init_generic(void)
1511 enum mcp_flags m_fl = 0;
1512 mce_banks_t all_banks;
1515 if (!mca_cfg.bootlog)
1519 * Log the machine checks left over from the previous reset.
1521 bitmap_fill(all_banks, MAX_NR_BANKS);
1522 machine_check_poll(MCP_UC | m_fl, &all_banks);
1524 cr4_set_bits(X86_CR4_MCE);
1526 rdmsrl(MSR_IA32_MCG_CAP, cap);
1527 if (cap & MCG_CTL_P)
1528 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1531 static void __mcheck_cpu_init_clear_banks(void)
1535 for (i = 0; i < mca_cfg.banks; i++) {
1536 struct mce_bank *b = &mce_banks[i];
1540 wrmsrl(msr_ops.ctl(i), b->ctl);
1541 wrmsrl(msr_ops.status(i), 0);
1546 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1547 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1548 * Vol 3B Table 15-20). But this confuses both the code that determines
1549 * whether the machine check occurred in kernel or user mode, and also
1550 * the severity assessment code. Pretend that EIPV was set, and take the
1551 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1553 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1557 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1559 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1560 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1561 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1563 (MCI_STATUS_UC|MCI_STATUS_EN|
1564 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1565 MCI_STATUS_AR|MCACOD_INSTR))
1568 m->mcgstatus |= MCG_STATUS_EIPV;
1573 /* Add per CPU specific workarounds here */
1574 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1576 struct mca_config *cfg = &mca_cfg;
1578 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1579 pr_info("unknown CPU type - not enabling MCE support\n");
1583 /* This should be disabled by the BIOS, but isn't always */
1584 if (c->x86_vendor == X86_VENDOR_AMD) {
1585 if (c->x86 == 15 && cfg->banks > 4) {
1587 * disable GART TBL walk error reporting, which
1588 * trips off incorrectly with the IOMMU & 3ware
1591 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1593 if (c->x86 < 0x11 && cfg->bootlog < 0) {
1595 * Lots of broken BIOS around that don't clear them
1596 * by default and leave crap in there. Don't log:
1601 * Various K7s with broken bank 0 around. Always disable
1604 if (c->x86 == 6 && cfg->banks > 0)
1605 mce_banks[0].ctl = 0;
1608 * overflow_recov is supported for F15h Models 00h-0fh
1609 * even though we don't have a CPUID bit for it.
1611 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1612 mce_flags.overflow_recov = 1;
1615 * Turn off MC4_MISC thresholding banks on those models since
1616 * they're not supported there.
1618 if (c->x86 == 0x15 &&
1619 (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
1624 0x00000413, /* MC4_MISC0 */
1625 0xc0000408, /* MC4_MISC1 */
1628 rdmsrl(MSR_K7_HWCR, hwcr);
1630 /* McStatusWrEn has to be set */
1631 need_toggle = !(hwcr & BIT(18));
1634 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
1636 /* Clear CntP bit safely */
1637 for (i = 0; i < ARRAY_SIZE(msrs); i++)
1638 msr_clear_bit(msrs[i], 62);
1640 /* restore old settings */
1642 wrmsrl(MSR_K7_HWCR, hwcr);
1646 if (c->x86_vendor == X86_VENDOR_INTEL) {
1648 * SDM documents that on family 6 bank 0 should not be written
1649 * because it aliases to another special BIOS controlled
1651 * But it's not aliased anymore on model 0x1a+
1652 * Don't ignore bank 0 completely because there could be a
1653 * valid event later, merely don't write CTL0.
1656 if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0)
1657 mce_banks[0].init = 0;
1660 * All newer Intel systems support MCE broadcasting. Enable
1661 * synchronization with a one second timeout.
1663 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1664 cfg->monarch_timeout < 0)
1665 cfg->monarch_timeout = USEC_PER_SEC;
1668 * There are also broken BIOSes on some Pentium M and
1671 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1674 if (c->x86 == 6 && c->x86_model == 45)
1675 quirk_no_way_out = quirk_sandybridge_ifu;
1677 if (cfg->monarch_timeout < 0)
1678 cfg->monarch_timeout = 0;
1679 if (cfg->bootlog != 0)
1680 cfg->panic_timeout = 30;
1685 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1690 switch (c->x86_vendor) {
1691 case X86_VENDOR_INTEL:
1692 intel_p5_mcheck_init(c);
1695 case X86_VENDOR_CENTAUR:
1696 winchip_mcheck_init(c);
1707 * Init basic CPU features needed for early decoding of MCEs.
1709 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1711 if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {
1712 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1713 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1714 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1716 if (mce_flags.smca) {
1717 msr_ops.ctl = smca_ctl_reg;
1718 msr_ops.status = smca_status_reg;
1719 msr_ops.addr = smca_addr_reg;
1720 msr_ops.misc = smca_misc_reg;
1725 static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
1727 struct mca_config *cfg = &mca_cfg;
1730 * All newer Centaur CPUs support MCE broadcasting. Enable
1731 * synchronization with a one second timeout.
1733 if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
1735 if (cfg->monarch_timeout < 0)
1736 cfg->monarch_timeout = USEC_PER_SEC;
1740 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1742 switch (c->x86_vendor) {
1743 case X86_VENDOR_INTEL:
1744 mce_intel_feature_init(c);
1745 mce_adjust_timer = cmci_intel_adjust_timer;
1748 case X86_VENDOR_AMD: {
1749 mce_amd_feature_init(c);
1753 case X86_VENDOR_HYGON:
1754 mce_hygon_feature_init(c);
1757 case X86_VENDOR_CENTAUR:
1758 mce_centaur_feature_init(c);
1766 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
1768 switch (c->x86_vendor) {
1769 case X86_VENDOR_INTEL:
1770 mce_intel_feature_clear(c);
1777 static void mce_start_timer(struct timer_list *t)
1779 unsigned long iv = check_interval * HZ;
1781 if (mca_cfg.ignore_ce || !iv)
1784 this_cpu_write(mce_next_interval, iv);
1785 __start_timer(t, iv);
1788 static void __mcheck_cpu_setup_timer(void)
1790 struct timer_list *t = this_cpu_ptr(&mce_timer);
1792 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1795 static void __mcheck_cpu_init_timer(void)
1797 struct timer_list *t = this_cpu_ptr(&mce_timer);
1799 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1803 /* Handle unconfigured int18 (should never happen) */
1804 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1806 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1807 smp_processor_id());
1810 /* Call the installed machine check handler for this CPU setup. */
1811 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1812 unexpected_machine_check;
1814 dotraplinkage void do_mce(struct pt_regs *regs, long error_code)
1816 machine_check_vector(regs, error_code);
1820 * Called for each booted CPU to set up machine checks.
1821 * Must be called with preempt off:
1823 void mcheck_cpu_init(struct cpuinfo_x86 *c)
1825 if (mca_cfg.disabled)
1828 if (__mcheck_cpu_ancient_init(c))
1831 if (!mce_available(c))
1834 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1835 mca_cfg.disabled = 1;
1839 if (mce_gen_pool_init()) {
1840 mca_cfg.disabled = 1;
1841 pr_emerg("Couldn't allocate MCE records pool!\n");
1845 machine_check_vector = do_machine_check;
1847 __mcheck_cpu_init_early(c);
1848 __mcheck_cpu_init_generic();
1849 __mcheck_cpu_init_vendor(c);
1850 __mcheck_cpu_init_clear_banks();
1851 __mcheck_cpu_setup_timer();
1855 * Called for each booted CPU to clear some machine checks opt-ins
1857 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
1859 if (mca_cfg.disabled)
1862 if (!mce_available(c))
1866 * Possibly to clear general settings generic to x86
1867 * __mcheck_cpu_clear_generic(c);
1869 __mcheck_cpu_clear_vendor(c);
1873 static void __mce_disable_bank(void *arg)
1875 int bank = *((int *)arg);
1876 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
1877 cmci_disable_bank(bank);
1880 void mce_disable_bank(int bank)
1882 if (bank >= mca_cfg.banks) {
1884 "Ignoring request to disable invalid MCA bank %d.\n",
1888 set_bit(bank, mce_banks_ce_disabled);
1889 on_each_cpu(__mce_disable_bank, &bank, 1);
1893 * mce=off Disables machine check
1894 * mce=no_cmci Disables CMCI
1895 * mce=no_lmce Disables LMCE
1896 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1897 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1898 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1899 * monarchtimeout is how long to wait for other CPUs on machine
1900 * check, or 0 to not wait
1901 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
1903 * mce=nobootlog Don't log MCEs from before booting.
1904 * mce=bios_cmci_threshold Don't program the CMCI threshold
1905 * mce=recovery force enable memcpy_mcsafe()
1907 static int __init mcheck_enable(char *str)
1909 struct mca_config *cfg = &mca_cfg;
1917 if (!strcmp(str, "off"))
1919 else if (!strcmp(str, "no_cmci"))
1920 cfg->cmci_disabled = true;
1921 else if (!strcmp(str, "no_lmce"))
1922 cfg->lmce_disabled = 1;
1923 else if (!strcmp(str, "dont_log_ce"))
1924 cfg->dont_log_ce = true;
1925 else if (!strcmp(str, "ignore_ce"))
1926 cfg->ignore_ce = true;
1927 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1928 cfg->bootlog = (str[0] == 'b');
1929 else if (!strcmp(str, "bios_cmci_threshold"))
1930 cfg->bios_cmci_threshold = 1;
1931 else if (!strcmp(str, "recovery"))
1933 else if (isdigit(str[0])) {
1934 if (get_option(&str, &cfg->tolerant) == 2)
1935 get_option(&str, &(cfg->monarch_timeout));
1937 pr_info("mce argument %s ignored. Please use /sys\n", str);
1942 __setup("mce", mcheck_enable);
1944 int __init mcheck_init(void)
1946 mcheck_intel_therm_init();
1947 mce_register_decode_chain(&first_nb);
1948 mce_register_decode_chain(&mce_srao_nb);
1949 mce_register_decode_chain(&mce_default_nb);
1950 mcheck_vendor_init_severity();
1952 INIT_WORK(&mce_work, mce_gen_pool_process);
1953 init_irq_work(&mce_irq_work, mce_irq_work_cb);
1959 * mce_syscore: PM support
1963 * Disable machine checks on suspend and shutdown. We can't really handle
1966 static void mce_disable_error_reporting(void)
1970 for (i = 0; i < mca_cfg.banks; i++) {
1971 struct mce_bank *b = &mce_banks[i];
1974 wrmsrl(msr_ops.ctl(i), 0);
1979 static void vendor_disable_error_reporting(void)
1982 * Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs
1984 * Disabling them for just a single offlined CPU is bad, since it will
1985 * inhibit reporting for all shared resources on the socket like the
1986 * last level cache (LLC), the integrated memory controller (iMC), etc.
1988 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
1989 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
1990 boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1993 mce_disable_error_reporting();
1996 static int mce_syscore_suspend(void)
1998 vendor_disable_error_reporting();
2002 static void mce_syscore_shutdown(void)
2004 vendor_disable_error_reporting();
2008 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2009 * Only one CPU is active at this time, the others get re-added later using
2012 static void mce_syscore_resume(void)
2014 __mcheck_cpu_init_generic();
2015 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2016 __mcheck_cpu_init_clear_banks();
2019 static struct syscore_ops mce_syscore_ops = {
2020 .suspend = mce_syscore_suspend,
2021 .shutdown = mce_syscore_shutdown,
2022 .resume = mce_syscore_resume,
2026 * mce_device: Sysfs support
2029 static void mce_cpu_restart(void *data)
2031 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2033 __mcheck_cpu_init_generic();
2034 __mcheck_cpu_init_clear_banks();
2035 __mcheck_cpu_init_timer();
2038 /* Reinit MCEs after user configuration changes */
2039 static void mce_restart(void)
2041 mce_timer_delete_all();
2042 on_each_cpu(mce_cpu_restart, NULL, 1);
2045 /* Toggle features for corrected errors */
2046 static void mce_disable_cmci(void *data)
2048 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2053 static void mce_enable_ce(void *all)
2055 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2060 __mcheck_cpu_init_timer();
2063 static struct bus_type mce_subsys = {
2064 .name = "machinecheck",
2065 .dev_name = "machinecheck",
2068 DEFINE_PER_CPU(struct device *, mce_device);
2070 static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
2072 return container_of(attr, struct mce_bank, attr);
2075 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2078 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
2081 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2082 const char *buf, size_t size)
2086 if (kstrtou64(buf, 0, &new) < 0)
2089 attr_to_bank(attr)->ctl = new;
2095 static ssize_t set_ignore_ce(struct device *s,
2096 struct device_attribute *attr,
2097 const char *buf, size_t size)
2101 if (kstrtou64(buf, 0, &new) < 0)
2104 mutex_lock(&mce_sysfs_mutex);
2105 if (mca_cfg.ignore_ce ^ !!new) {
2107 /* disable ce features */
2108 mce_timer_delete_all();
2109 on_each_cpu(mce_disable_cmci, NULL, 1);
2110 mca_cfg.ignore_ce = true;
2112 /* enable ce features */
2113 mca_cfg.ignore_ce = false;
2114 on_each_cpu(mce_enable_ce, (void *)1, 1);
2117 mutex_unlock(&mce_sysfs_mutex);
2122 static ssize_t set_cmci_disabled(struct device *s,
2123 struct device_attribute *attr,
2124 const char *buf, size_t size)
2128 if (kstrtou64(buf, 0, &new) < 0)
2131 mutex_lock(&mce_sysfs_mutex);
2132 if (mca_cfg.cmci_disabled ^ !!new) {
2135 on_each_cpu(mce_disable_cmci, NULL, 1);
2136 mca_cfg.cmci_disabled = true;
2139 mca_cfg.cmci_disabled = false;
2140 on_each_cpu(mce_enable_ce, NULL, 1);
2143 mutex_unlock(&mce_sysfs_mutex);
2148 static ssize_t store_int_with_restart(struct device *s,
2149 struct device_attribute *attr,
2150 const char *buf, size_t size)
2152 unsigned long old_check_interval = check_interval;
2153 ssize_t ret = device_store_ulong(s, attr, buf, size);
2155 if (check_interval == old_check_interval)
2158 mutex_lock(&mce_sysfs_mutex);
2160 mutex_unlock(&mce_sysfs_mutex);
2165 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2166 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2167 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2169 static struct dev_ext_attribute dev_attr_check_interval = {
2170 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2174 static struct dev_ext_attribute dev_attr_ignore_ce = {
2175 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2179 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2180 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2181 &mca_cfg.cmci_disabled
2184 static struct device_attribute *mce_device_attrs[] = {
2185 &dev_attr_tolerant.attr,
2186 &dev_attr_check_interval.attr,
2187 #ifdef CONFIG_X86_MCELOG_LEGACY
2190 &dev_attr_monarch_timeout.attr,
2191 &dev_attr_dont_log_ce.attr,
2192 &dev_attr_ignore_ce.attr,
2193 &dev_attr_cmci_disabled.attr,
2197 static cpumask_var_t mce_device_initialized;
2199 static void mce_device_release(struct device *dev)
2204 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2205 static int mce_device_create(unsigned int cpu)
2211 if (!mce_available(&boot_cpu_data))
2214 dev = per_cpu(mce_device, cpu);
2218 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2222 dev->bus = &mce_subsys;
2223 dev->release = &mce_device_release;
2225 err = device_register(dev);
2231 for (i = 0; mce_device_attrs[i]; i++) {
2232 err = device_create_file(dev, mce_device_attrs[i]);
2236 for (j = 0; j < mca_cfg.banks; j++) {
2237 err = device_create_file(dev, &mce_banks[j].attr);
2241 cpumask_set_cpu(cpu, mce_device_initialized);
2242 per_cpu(mce_device, cpu) = dev;
2247 device_remove_file(dev, &mce_banks[j].attr);
2250 device_remove_file(dev, mce_device_attrs[i]);
2252 device_unregister(dev);
2257 static void mce_device_remove(unsigned int cpu)
2259 struct device *dev = per_cpu(mce_device, cpu);
2262 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2265 for (i = 0; mce_device_attrs[i]; i++)
2266 device_remove_file(dev, mce_device_attrs[i]);
2268 for (i = 0; i < mca_cfg.banks; i++)
2269 device_remove_file(dev, &mce_banks[i].attr);
2271 device_unregister(dev);
2272 cpumask_clear_cpu(cpu, mce_device_initialized);
2273 per_cpu(mce_device, cpu) = NULL;
2276 /* Make sure there are no machine checks on offlined CPUs. */
2277 static void mce_disable_cpu(void)
2279 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2282 if (!cpuhp_tasks_frozen)
2285 vendor_disable_error_reporting();
2288 static void mce_reenable_cpu(void)
2292 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2295 if (!cpuhp_tasks_frozen)
2297 for (i = 0; i < mca_cfg.banks; i++) {
2298 struct mce_bank *b = &mce_banks[i];
2301 wrmsrl(msr_ops.ctl(i), b->ctl);
2305 static int mce_cpu_dead(unsigned int cpu)
2307 mce_intel_hcpu_update(cpu);
2309 /* intentionally ignoring frozen here */
2310 if (!cpuhp_tasks_frozen)
2315 static int mce_cpu_online(unsigned int cpu)
2317 struct timer_list *t = this_cpu_ptr(&mce_timer);
2320 mce_device_create(cpu);
2322 ret = mce_threshold_create_device(cpu);
2324 mce_device_remove(cpu);
2332 static int mce_cpu_pre_down(unsigned int cpu)
2334 struct timer_list *t = this_cpu_ptr(&mce_timer);
2338 mce_threshold_remove_device(cpu);
2339 mce_device_remove(cpu);
2343 static __init void mce_init_banks(void)
2347 for (i = 0; i < mca_cfg.banks; i++) {
2348 struct mce_bank *b = &mce_banks[i];
2349 struct device_attribute *a = &b->attr;
2351 sysfs_attr_init(&a->attr);
2352 a->attr.name = b->attrname;
2353 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2355 a->attr.mode = 0644;
2356 a->show = show_bank;
2357 a->store = set_bank;
2361 static __init int mcheck_init_device(void)
2366 * Check if we have a spare virtual bit. This will only become
2367 * a problem if/when we move beyond 5-level page tables.
2369 MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
2371 if (!mce_available(&boot_cpu_data)) {
2376 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2383 err = subsys_system_register(&mce_subsys, NULL);
2387 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2392 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2393 mce_cpu_online, mce_cpu_pre_down);
2395 goto err_out_online;
2397 register_syscore_ops(&mce_syscore_ops);
2402 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2405 free_cpumask_var(mce_device_initialized);
2408 pr_err("Unable to init MCE device (rc: %d)\n", err);
2412 device_initcall_sync(mcheck_init_device);
2415 * Old style boot options parsing. Only for compatibility.
2417 static int __init mcheck_disable(char *str)
2419 mca_cfg.disabled = 1;
2422 __setup("nomce", mcheck_disable);
2424 #ifdef CONFIG_DEBUG_FS
2425 struct dentry *mce_get_debugfs_dir(void)
2427 static struct dentry *dmce;
2430 dmce = debugfs_create_dir("mce", NULL);
2435 static void mce_reset(void)
2438 atomic_set(&mce_fake_panicked, 0);
2439 atomic_set(&mce_executing, 0);
2440 atomic_set(&mce_callin, 0);
2441 atomic_set(&global_nwo, 0);
2444 static int fake_panic_get(void *data, u64 *val)
2450 static int fake_panic_set(void *data, u64 val)
2457 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2458 fake_panic_set, "%llu\n");
2460 static int __init mcheck_debugfs_init(void)
2462 struct dentry *dmce, *ffake_panic;
2464 dmce = mce_get_debugfs_dir();
2467 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2475 static int __init mcheck_debugfs_init(void) { return -EINVAL; }
2478 DEFINE_STATIC_KEY_FALSE(mcsafe_key);
2479 EXPORT_SYMBOL_GPL(mcsafe_key);
2481 static int __init mcheck_late_init(void)
2483 if (mca_cfg.recovery)
2484 static_branch_inc(&mcsafe_key);
2486 mcheck_debugfs_init();
2490 * Flush out everything that has been logged during early boot, now that
2491 * everything has been initialized (workqueues, decoders, ...).
2493 mce_schedule_work();
2497 late_initcall(mcheck_late_init);