2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/init.h>
30 #include <linux/kmod.h>
31 #include <linux/poll.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34 #include <linux/smp.h>
37 #include <linux/debugfs.h>
39 #include <asm/processor.h>
40 #include <asm/hw_irq.h>
47 #include "mce-internal.h"
49 int mce_disabled __read_mostly;
51 #define MISC_MCELOG_MINOR 227
53 #define SPINUNIT 100 /* 100ns */
57 DEFINE_PER_CPU(unsigned, mce_exception_count);
61 * 0: always panic on uncorrected errors, log corrected errors
62 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
63 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
64 * 3: never panic or SIGBUS, log all errors (for testing only)
66 static int tolerant __read_mostly = 1;
67 static int banks __read_mostly;
68 static int rip_msr __read_mostly;
69 static int mce_bootlog __read_mostly = -1;
70 static int monarch_timeout __read_mostly = -1;
71 static int mce_panic_timeout __read_mostly;
72 static int mce_dont_log_ce __read_mostly;
73 int mce_cmci_disabled __read_mostly;
74 int mce_ignore_ce __read_mostly;
75 int mce_ser __read_mostly;
77 struct mce_bank *mce_banks __read_mostly;
79 /* User mode helper program triggered by machine check event */
80 static unsigned long mce_need_notify;
81 static char mce_helper[128];
82 static char *mce_helper_argv[2] = { mce_helper, NULL };
84 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
85 static DEFINE_PER_CPU(struct mce, mces_seen);
86 static int cpu_missing;
89 /* MCA banks polled by the period polling timer for corrected events */
90 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
91 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
94 static DEFINE_PER_CPU(struct work_struct, mce_work);
96 /* Do initial initialization of a struct mce */
97 void mce_setup(struct mce *m)
99 memset(m, 0, sizeof(struct mce));
100 m->cpu = m->extcpu = smp_processor_id();
102 /* We hope get_seconds stays lockless */
103 m->time = get_seconds();
104 m->cpuvendor = boot_cpu_data.x86_vendor;
105 m->cpuid = cpuid_eax(1);
107 m->socketid = cpu_data(m->extcpu).phys_proc_id;
109 m->apicid = cpu_data(m->extcpu).initial_apicid;
110 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
113 DEFINE_PER_CPU(struct mce, injectm);
114 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
117 * Lockless MCE logging infrastructure.
118 * This avoids deadlocks on printk locks without having to break locks. Also
119 * separate MCEs from kernel messages to avoid bogus bug reports.
122 static struct mce_log mcelog = {
123 .signature = MCE_LOG_SIGNATURE,
125 .recordlen = sizeof(struct mce),
128 void mce_log(struct mce *mce)
130 unsigned next, entry;
135 entry = rcu_dereference(mcelog.next);
138 * When the buffer fills up discard new entries.
139 * Assume that the earlier errors are the more
142 if (entry >= MCE_LOG_LEN) {
143 set_bit(MCE_OVERFLOW,
144 (unsigned long *)&mcelog.flags);
147 /* Old left over entry. Skip: */
148 if (mcelog.entry[entry].finished) {
156 if (cmpxchg(&mcelog.next, entry, next) == entry)
159 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
161 mcelog.entry[entry].finished = 1;
165 set_bit(0, &mce_need_notify);
168 void __weak decode_mce(struct mce *m)
173 static void print_mce(struct mce *m)
176 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
177 m->extcpu, m->mcgstatus, m->bank, m->status);
179 printk(KERN_EMERG "RIP%s %02x:<%016Lx> ",
180 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
182 if (m->cs == __KERNEL_CS)
183 print_symbol("{%s}", m->ip);
184 printk(KERN_CONT "\n");
186 printk(KERN_EMERG "TSC %llx ", m->tsc);
188 printk(KERN_CONT "ADDR %llx ", m->addr);
190 printk(KERN_CONT "MISC %llx ", m->misc);
191 printk(KERN_CONT "\n");
192 printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
193 m->cpuvendor, m->cpuid, m->time, m->socketid,
199 static void print_mce_head(void)
201 printk(KERN_EMERG "\nHARDWARE ERROR\n");
204 static void print_mce_tail(void)
206 printk(KERN_EMERG "This is not a software problem!\n"
207 #if (!defined(CONFIG_EDAC) || !defined(CONFIG_CPU_SUP_AMD))
208 "Run through mcelog --ascii to decode and contact your hardware vendor\n"
213 #define PANIC_TIMEOUT 5 /* 5 seconds */
215 static atomic_t mce_paniced;
217 static int fake_panic;
218 static atomic_t mce_fake_paniced;
220 /* Panic in progress. Enable interrupts and wait for final IPI */
221 static void wait_for_panic(void)
223 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
226 while (timeout-- > 0)
228 if (panic_timeout == 0)
229 panic_timeout = mce_panic_timeout;
230 panic("Panicing machine check CPU died");
233 static void mce_panic(char *msg, struct mce *final, char *exp)
239 * Make sure only one CPU runs in machine check panic
241 if (atomic_inc_return(&mce_paniced) > 1)
248 /* Don't log too much for fake panic */
249 if (atomic_inc_return(&mce_fake_paniced) > 1)
253 /* First print corrected ones that are still unlogged */
254 for (i = 0; i < MCE_LOG_LEN; i++) {
255 struct mce *m = &mcelog.entry[i];
256 if (!(m->status & MCI_STATUS_VAL))
258 if (!(m->status & MCI_STATUS_UC))
261 /* Now print uncorrected but with the final one last */
262 for (i = 0; i < MCE_LOG_LEN; i++) {
263 struct mce *m = &mcelog.entry[i];
264 if (!(m->status & MCI_STATUS_VAL))
266 if (!(m->status & MCI_STATUS_UC))
268 if (!final || memcmp(m, final, sizeof(struct mce)))
274 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
277 printk(KERN_EMERG "Machine check: %s\n", exp);
279 if (panic_timeout == 0)
280 panic_timeout = mce_panic_timeout;
283 printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
286 /* Support code for software error injection */
288 static int msr_to_offset(u32 msr)
290 unsigned bank = __get_cpu_var(injectm.bank);
292 return offsetof(struct mce, ip);
293 if (msr == MSR_IA32_MCx_STATUS(bank))
294 return offsetof(struct mce, status);
295 if (msr == MSR_IA32_MCx_ADDR(bank))
296 return offsetof(struct mce, addr);
297 if (msr == MSR_IA32_MCx_MISC(bank))
298 return offsetof(struct mce, misc);
299 if (msr == MSR_IA32_MCG_STATUS)
300 return offsetof(struct mce, mcgstatus);
304 /* MSR access wrappers used for error injection */
305 static u64 mce_rdmsrl(u32 msr)
308 if (__get_cpu_var(injectm).finished) {
309 int offset = msr_to_offset(msr);
312 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
318 static void mce_wrmsrl(u32 msr, u64 v)
320 if (__get_cpu_var(injectm).finished) {
321 int offset = msr_to_offset(msr);
323 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
330 * Simple lockless ring to communicate PFNs from the exception handler with the
331 * process context work function. This is vastly simplified because there's
332 * only a single reader and a single writer.
334 #define MCE_RING_SIZE 16 /* we use one entry less */
337 unsigned short start;
339 unsigned long ring[MCE_RING_SIZE];
341 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
343 /* Runs with CPU affinity in workqueue */
344 static int mce_ring_empty(void)
346 struct mce_ring *r = &__get_cpu_var(mce_ring);
348 return r->start == r->end;
351 static int mce_ring_get(unsigned long *pfn)
358 r = &__get_cpu_var(mce_ring);
359 if (r->start == r->end)
361 *pfn = r->ring[r->start];
362 r->start = (r->start + 1) % MCE_RING_SIZE;
369 /* Always runs in MCE context with preempt off */
370 static int mce_ring_add(unsigned long pfn)
372 struct mce_ring *r = &__get_cpu_var(mce_ring);
375 next = (r->end + 1) % MCE_RING_SIZE;
376 if (next == r->start)
378 r->ring[r->end] = pfn;
384 int mce_available(struct cpuinfo_x86 *c)
388 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
391 static void mce_schedule_work(void)
393 if (!mce_ring_empty()) {
394 struct work_struct *work = &__get_cpu_var(mce_work);
395 if (!work_pending(work))
401 * Get the address of the instruction at the time of the machine check
404 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
407 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
415 m->ip = mce_rdmsrl(rip_msr);
418 #ifdef CONFIG_X86_LOCAL_APIC
420 * Called after interrupts have been reenabled again
421 * when a MCE happened during an interrupts off region
424 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
435 static void mce_report_event(struct pt_regs *regs)
437 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
440 * Triggering the work queue here is just an insurance
441 * policy in case the syscall exit notify handler
442 * doesn't run soon enough or ends up running on the
443 * wrong CPU (can happen when audit sleeps)
449 #ifdef CONFIG_X86_LOCAL_APIC
451 * Without APIC do not notify. The event will be picked
458 * When interrupts are disabled we cannot use
459 * kernel services safely. Trigger an self interrupt
460 * through the APIC to instead do the notification
461 * after interrupts are reenabled again.
463 apic->send_IPI_self(MCE_SELF_VECTOR);
466 * Wait for idle afterwards again so that we don't leave the
467 * APIC in a non idle state because the normal APIC writes
470 apic_wait_icr_idle();
474 DEFINE_PER_CPU(unsigned, mce_poll_count);
477 * Poll for corrected events or events that happened before reset.
478 * Those are just logged through /dev/mcelog.
480 * This is executed in standard interrupt context.
482 * Note: spec recommends to panic for fatal unsignalled
483 * errors here. However this would be quite problematic --
484 * we would need to reimplement the Monarch handling and
485 * it would mess up the exclusion between exception handler
486 * and poll hander -- * so we skip this for now.
487 * These cases should not happen anyways, or only when the CPU
488 * is already totally * confused. In this case it's likely it will
489 * not fully execute the machine check handler either.
491 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
496 __get_cpu_var(mce_poll_count)++;
500 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
501 for (i = 0; i < banks; i++) {
502 if (!mce_banks[i].ctl || !test_bit(i, *b))
511 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
512 if (!(m.status & MCI_STATUS_VAL))
516 * Uncorrected or signalled events are handled by the exception
517 * handler when it is enabled, so don't process those here.
519 * TBD do the same check for MCI_STATUS_EN here?
521 if (!(flags & MCP_UC) &&
522 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
525 if (m.status & MCI_STATUS_MISCV)
526 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
527 if (m.status & MCI_STATUS_ADDRV)
528 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
530 if (!(flags & MCP_TIMESTAMP))
533 * Don't get the IP here because it's unlikely to
534 * have anything to do with the actual error location.
536 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
538 add_taint(TAINT_MACHINE_CHECK);
542 * Clear state for this bank.
544 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
548 * Don't clear MCG_STATUS here because it's only defined for
554 EXPORT_SYMBOL_GPL(machine_check_poll);
557 * Do a quick check if any of the events requires a panic.
558 * This decides if we keep the events around or clear them.
560 static int mce_no_way_out(struct mce *m, char **msg)
564 for (i = 0; i < banks; i++) {
565 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
566 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
573 * Variable to establish order between CPUs while scanning.
574 * Each CPU spins initially until executing is equal its number.
576 static atomic_t mce_executing;
579 * Defines order of CPUs on entry. First CPU becomes Monarch.
581 static atomic_t mce_callin;
584 * Check if a timeout waiting for other CPUs happened.
586 static int mce_timed_out(u64 *t)
589 * The others already did panic for some reason.
590 * Bail out like in a timeout.
591 * rmb() to tell the compiler that system_state
592 * might have been modified by someone else.
595 if (atomic_read(&mce_paniced))
597 if (!monarch_timeout)
599 if ((s64)*t < SPINUNIT) {
600 /* CHECKME: Make panic default for 1 too? */
602 mce_panic("Timeout synchronizing machine check over CPUs",
609 touch_nmi_watchdog();
614 * The Monarch's reign. The Monarch is the CPU who entered
615 * the machine check handler first. It waits for the others to
616 * raise the exception too and then grades them. When any
617 * error is fatal panic. Only then let the others continue.
619 * The other CPUs entering the MCE handler will be controlled by the
620 * Monarch. They are called Subjects.
622 * This way we prevent any potential data corruption in a unrecoverable case
623 * and also makes sure always all CPU's errors are examined.
625 * Also this detects the case of a machine check event coming from outer
626 * space (not detected by any CPUs) In this case some external agent wants
627 * us to shut down, so panic too.
629 * The other CPUs might still decide to panic if the handler happens
630 * in a unrecoverable place, but in this case the system is in a semi-stable
631 * state and won't corrupt anything by itself. It's ok to let the others
632 * continue for a bit first.
634 * All the spin loops have timeouts; when a timeout happens a CPU
635 * typically elects itself to be Monarch.
637 static void mce_reign(void)
640 struct mce *m = NULL;
641 int global_worst = 0;
646 * This CPU is the Monarch and the other CPUs have run
647 * through their handlers.
648 * Grade the severity of the errors of all the CPUs.
650 for_each_possible_cpu(cpu) {
651 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
653 if (severity > global_worst) {
655 global_worst = severity;
656 m = &per_cpu(mces_seen, cpu);
661 * Cannot recover? Panic here then.
662 * This dumps all the mces in the log buffer and stops the
665 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
666 mce_panic("Fatal Machine check", m, msg);
669 * For UC somewhere we let the CPU who detects it handle it.
670 * Also must let continue the others, otherwise the handling
671 * CPU could deadlock on a lock.
675 * No machine check event found. Must be some external
676 * source or one CPU is hung. Panic.
678 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
679 mce_panic("Machine check from unknown source", NULL, NULL);
682 * Now clear all the mces_seen so that they don't reappear on
685 for_each_possible_cpu(cpu)
686 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
689 static atomic_t global_nwo;
692 * Start of Monarch synchronization. This waits until all CPUs have
693 * entered the exception handler and then determines if any of them
694 * saw a fatal event that requires panic. Then it executes them
695 * in the entry order.
696 * TBD double check parallel CPU hotunplug
698 static int mce_start(int *no_way_out)
701 int cpus = num_online_cpus();
702 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
707 atomic_add(*no_way_out, &global_nwo);
709 * global_nwo should be updated before mce_callin
712 order = atomic_inc_return(&mce_callin);
717 while (atomic_read(&mce_callin) != cpus) {
718 if (mce_timed_out(&timeout)) {
719 atomic_set(&global_nwo, 0);
726 * mce_callin should be read before global_nwo
732 * Monarch: Starts executing now, the others wait.
734 atomic_set(&mce_executing, 1);
737 * Subject: Now start the scanning loop one by one in
738 * the original callin order.
739 * This way when there are any shared banks it will be
740 * only seen by one CPU before cleared, avoiding duplicates.
742 while (atomic_read(&mce_executing) < order) {
743 if (mce_timed_out(&timeout)) {
744 atomic_set(&global_nwo, 0);
752 * Cache the global no_way_out state.
754 *no_way_out = atomic_read(&global_nwo);
760 * Synchronize between CPUs after main scanning loop.
761 * This invokes the bulk of the Monarch processing.
763 static int mce_end(int order)
766 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
774 * Allow others to run.
776 atomic_inc(&mce_executing);
779 /* CHECKME: Can this race with a parallel hotplug? */
780 int cpus = num_online_cpus();
783 * Monarch: Wait for everyone to go through their scanning
786 while (atomic_read(&mce_executing) <= cpus) {
787 if (mce_timed_out(&timeout))
797 * Subject: Wait for Monarch to finish.
799 while (atomic_read(&mce_executing) != 0) {
800 if (mce_timed_out(&timeout))
806 * Don't reset anything. That's done by the Monarch.
812 * Reset all global state.
815 atomic_set(&global_nwo, 0);
816 atomic_set(&mce_callin, 0);
820 * Let others run again.
822 atomic_set(&mce_executing, 0);
827 * Check if the address reported by the CPU is in a format we can parse.
828 * It would be possible to add code for most other cases, but all would
829 * be somewhat complicated (e.g. segment offset would require an instruction
830 * parser). So only support physical addresses upto page granuality for now.
832 static int mce_usable_address(struct mce *m)
834 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
836 if ((m->misc & 0x3f) > PAGE_SHIFT)
838 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
843 static void mce_clear_state(unsigned long *toclear)
847 for (i = 0; i < banks; i++) {
848 if (test_bit(i, toclear))
849 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
854 * The actual machine check handler. This only handles real
855 * exceptions when something got corrupted coming in through int 18.
857 * This is executed in NMI context not subject to normal locking rules. This
858 * implies that most kernel services cannot be safely used. Don't even
859 * think about putting a printk in there!
861 * On Intel systems this is entered on all CPUs in parallel through
862 * MCE broadcast. However some CPUs might be broken beyond repair,
863 * so be always careful when synchronizing with others.
865 void do_machine_check(struct pt_regs *regs, long error_code)
867 struct mce m, *final;
872 * Establish sequential order between the CPUs entering the machine
877 * If no_way_out gets set, there is no safe way to recover from this
878 * MCE. If tolerant is cranked up, we'll try anyway.
882 * If kill_it gets set, there might be a way to recover from this
886 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
887 char *msg = "Unknown";
889 atomic_inc(&mce_entry);
891 __get_cpu_var(mce_exception_count)++;
893 if (notify_die(DIE_NMI, "machine check", regs, error_code,
894 18, SIGKILL) == NOTIFY_STOP)
901 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
902 final = &__get_cpu_var(mces_seen);
905 no_way_out = mce_no_way_out(&m, &msg);
910 * When no restart IP must always kill or panic.
912 if (!(m.mcgstatus & MCG_STATUS_RIPV))
916 * Go through all the banks in exclusion of the other CPUs.
917 * This way we don't report duplicated events on shared banks
918 * because the first one to see it will clear it.
920 order = mce_start(&no_way_out);
921 for (i = 0; i < banks; i++) {
922 __clear_bit(i, toclear);
923 if (!mce_banks[i].ctl)
930 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
931 if ((m.status & MCI_STATUS_VAL) == 0)
935 * Non uncorrected or non signaled errors are handled by
936 * machine_check_poll. Leave them alone, unless this panics.
938 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
943 * Set taint even when machine check was not enabled.
945 add_taint(TAINT_MACHINE_CHECK);
947 severity = mce_severity(&m, tolerant, NULL);
950 * When machine check was for corrected handler don't touch,
951 * unless we're panicing.
953 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
955 __set_bit(i, toclear);
956 if (severity == MCE_NO_SEVERITY) {
958 * Machine check event was not enabled. Clear, but
965 * Kill on action required.
967 if (severity == MCE_AR_SEVERITY)
970 if (m.status & MCI_STATUS_MISCV)
971 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
972 if (m.status & MCI_STATUS_ADDRV)
973 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
976 * Action optional error. Queue address for later processing.
977 * When the ring overflows we just ignore the AO error.
978 * RED-PEN add some logging mechanism when
979 * usable_address or mce_add_ring fails.
980 * RED-PEN don't ignore overflow for tolerant == 0
982 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
983 mce_ring_add(m.addr >> PAGE_SHIFT);
985 mce_get_rip(&m, regs);
988 if (severity > worst) {
995 mce_clear_state(toclear);
998 * Do most of the synchronization with other CPUs.
999 * When there's any problem use only local no_way_out state.
1001 if (mce_end(order) < 0)
1002 no_way_out = worst >= MCE_PANIC_SEVERITY;
1005 * If we have decided that we just CAN'T continue, and the user
1006 * has not set tolerant to an insane level, give up and die.
1008 * This is mainly used in the case when the system doesn't
1009 * support MCE broadcasting or it has been disabled.
1011 if (no_way_out && tolerant < 3)
1012 mce_panic("Fatal machine check on current CPU", final, msg);
1015 * If the error seems to be unrecoverable, something should be
1016 * done. Try to kill as little as possible. If we can kill just
1017 * one task, do that. If the user has set the tolerance very
1018 * high, don't try to do anything at all.
1021 if (kill_it && tolerant < 3)
1022 force_sig(SIGBUS, current);
1024 /* notify userspace ASAP */
1025 set_thread_flag(TIF_MCE_NOTIFY);
1028 mce_report_event(regs);
1029 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1031 atomic_dec(&mce_entry);
1034 EXPORT_SYMBOL_GPL(do_machine_check);
1036 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1037 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1039 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1043 * Called after mce notification in process context. This code
1044 * is allowed to sleep. Call the high level VM handler to process
1045 * any corrupted pages.
1046 * Assume that the work queue code only calls this one at a time
1048 * Note we don't disable preemption, so this code might run on the wrong
1049 * CPU. In this case the event is picked up by the scheduled work queue.
1050 * This is merely a fast path to expedite processing in some common
1053 void mce_notify_process(void)
1057 while (mce_ring_get(&pfn))
1058 memory_failure(pfn, MCE_VECTOR);
1061 static void mce_process_work(struct work_struct *dummy)
1063 mce_notify_process();
1066 #ifdef CONFIG_X86_MCE_INTEL
1068 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1069 * @cpu: The CPU on which the event occurred.
1070 * @status: Event status information
1072 * This function should be called by the thermal interrupt after the
1073 * event has been processed and the decision was made to log the event
1076 * The status parameter will be saved to the 'status' field of 'struct mce'
1077 * and historically has been the register value of the
1078 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1080 void mce_log_therm_throt_event(__u64 status)
1085 m.bank = MCE_THERMAL_BANK;
1089 #endif /* CONFIG_X86_MCE_INTEL */
1092 * Periodic polling timer for "silent" machine check errors. If the
1093 * poller finds an MCE, poll 2x faster. When the poller finds no more
1094 * errors, poll 2x slower (up to check_interval seconds).
1096 static int check_interval = 5 * 60; /* 5 minutes */
1098 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1099 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1101 static void mcheck_timer(unsigned long data)
1103 struct timer_list *t = &per_cpu(mce_timer, data);
1106 WARN_ON(smp_processor_id() != data);
1108 if (mce_available(¤t_cpu_data)) {
1109 machine_check_poll(MCP_TIMESTAMP,
1110 &__get_cpu_var(mce_poll_banks));
1114 * Alert userspace if needed. If we logged an MCE, reduce the
1115 * polling interval, otherwise increase the polling interval.
1117 n = &__get_cpu_var(mce_next_interval);
1118 if (mce_notify_irq())
1119 *n = max(*n/2, HZ/100);
1121 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1123 t->expires = jiffies + *n;
1124 add_timer_on(t, smp_processor_id());
1127 static void mce_do_trigger(struct work_struct *work)
1129 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1132 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1135 * Notify the user(s) about new machine check events.
1136 * Can be called from interrupt context, but not from machine check/NMI
1139 int mce_notify_irq(void)
1141 /* Not more than two messages every minute */
1142 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1144 clear_thread_flag(TIF_MCE_NOTIFY);
1146 if (test_and_clear_bit(0, &mce_need_notify)) {
1147 wake_up_interruptible(&mce_wait);
1150 * There is no risk of missing notifications because
1151 * work_pending is always cleared before the function is
1154 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1155 schedule_work(&mce_trigger_work);
1157 if (__ratelimit(&ratelimit))
1158 printk(KERN_INFO "Machine check events logged\n");
1164 EXPORT_SYMBOL_GPL(mce_notify_irq);
1166 static int mce_banks_init(void)
1170 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1173 for (i = 0; i < banks; i++) {
1174 struct mce_bank *b = &mce_banks[i];
1182 * Initialize Machine Checks for a CPU.
1184 static int __cpuinit mce_cap_init(void)
1189 rdmsrl(MSR_IA32_MCG_CAP, cap);
1191 b = cap & MCG_BANKCNT_MASK;
1192 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1194 if (b > MAX_NR_BANKS) {
1196 "MCE: Using only %u machine check banks out of %u\n",
1201 /* Don't support asymmetric configurations today */
1202 WARN_ON(banks != 0 && b != banks);
1205 int err = mce_banks_init();
1210 /* Use accurate RIP reporting if available. */
1211 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1212 rip_msr = MSR_IA32_MCG_EIP;
1214 if (cap & MCG_SER_P)
1220 static void mce_init(void)
1222 mce_banks_t all_banks;
1227 * Log the machine checks left over from the previous reset.
1229 bitmap_fill(all_banks, MAX_NR_BANKS);
1230 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1232 set_in_cr4(X86_CR4_MCE);
1234 rdmsrl(MSR_IA32_MCG_CAP, cap);
1235 if (cap & MCG_CTL_P)
1236 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1238 for (i = 0; i < banks; i++) {
1239 struct mce_bank *b = &mce_banks[i];
1242 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1243 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1247 /* Add per CPU specific workarounds here */
1248 static int __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c)
1250 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1251 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1255 /* This should be disabled by the BIOS, but isn't always */
1256 if (c->x86_vendor == X86_VENDOR_AMD) {
1257 if (c->x86 == 15 && banks > 4) {
1259 * disable GART TBL walk error reporting, which
1260 * trips off incorrectly with the IOMMU & 3ware
1263 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1265 if (c->x86 <= 17 && mce_bootlog < 0) {
1267 * Lots of broken BIOS around that don't clear them
1268 * by default and leave crap in there. Don't log:
1273 * Various K7s with broken bank 0 around. Always disable
1276 if (c->x86 == 6 && banks > 0)
1277 mce_banks[0].ctl = 0;
1280 if (c->x86_vendor == X86_VENDOR_INTEL) {
1282 * SDM documents that on family 6 bank 0 should not be written
1283 * because it aliases to another special BIOS controlled
1285 * But it's not aliased anymore on model 0x1a+
1286 * Don't ignore bank 0 completely because there could be a
1287 * valid event later, merely don't write CTL0.
1290 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1291 mce_banks[0].init = 0;
1294 * All newer Intel systems support MCE broadcasting. Enable
1295 * synchronization with a one second timeout.
1297 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1298 monarch_timeout < 0)
1299 monarch_timeout = USEC_PER_SEC;
1302 * There are also broken BIOSes on some Pentium M and
1305 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1308 if (monarch_timeout < 0)
1309 monarch_timeout = 0;
1310 if (mce_bootlog != 0)
1311 mce_panic_timeout = 30;
1316 static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
1320 switch (c->x86_vendor) {
1321 case X86_VENDOR_INTEL:
1322 intel_p5_mcheck_init(c);
1324 case X86_VENDOR_CENTAUR:
1325 winchip_mcheck_init(c);
1330 static void mce_cpu_features(struct cpuinfo_x86 *c)
1332 switch (c->x86_vendor) {
1333 case X86_VENDOR_INTEL:
1334 mce_intel_feature_init(c);
1336 case X86_VENDOR_AMD:
1337 mce_amd_feature_init(c);
1344 static void mce_init_timer(void)
1346 struct timer_list *t = &__get_cpu_var(mce_timer);
1347 int *n = &__get_cpu_var(mce_next_interval);
1352 *n = check_interval * HZ;
1355 setup_timer(t, mcheck_timer, smp_processor_id());
1356 t->expires = round_jiffies(jiffies + *n);
1357 add_timer_on(t, smp_processor_id());
1360 /* Handle unconfigured int18 (should never happen) */
1361 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1363 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1364 smp_processor_id());
1367 /* Call the installed machine check handler for this CPU setup. */
1368 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1369 unexpected_machine_check;
1372 * Called for each booted CPU to set up machine checks.
1373 * Must be called with preempt off:
1375 void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
1380 mce_ancient_init(c);
1382 if (!mce_available(c))
1385 if (mce_cap_init() < 0 || mce_cpu_quirks(c) < 0) {
1390 machine_check_vector = do_machine_check;
1393 mce_cpu_features(c);
1395 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1399 * Character device to read and clear the MCE log.
1402 static DEFINE_SPINLOCK(mce_state_lock);
1403 static int open_count; /* #times opened */
1404 static int open_exclu; /* already open exclusive? */
1406 static int mce_open(struct inode *inode, struct file *file)
1408 spin_lock(&mce_state_lock);
1410 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1411 spin_unlock(&mce_state_lock);
1416 if (file->f_flags & O_EXCL)
1420 spin_unlock(&mce_state_lock);
1422 return nonseekable_open(inode, file);
1425 static int mce_release(struct inode *inode, struct file *file)
1427 spin_lock(&mce_state_lock);
1432 spin_unlock(&mce_state_lock);
1437 static void collect_tscs(void *data)
1439 unsigned long *cpu_tsc = (unsigned long *)data;
1441 rdtscll(cpu_tsc[smp_processor_id()]);
1444 static DEFINE_MUTEX(mce_read_mutex);
1446 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1449 char __user *buf = ubuf;
1450 unsigned long *cpu_tsc;
1451 unsigned prev, next;
1454 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1458 mutex_lock(&mce_read_mutex);
1459 next = rcu_dereference(mcelog.next);
1461 /* Only supports full reads right now */
1462 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
1463 mutex_unlock(&mce_read_mutex);
1472 for (i = prev; i < next; i++) {
1473 unsigned long start = jiffies;
1475 while (!mcelog.entry[i].finished) {
1476 if (time_after_eq(jiffies, start + 2)) {
1477 memset(mcelog.entry + i, 0,
1478 sizeof(struct mce));
1484 err |= copy_to_user(buf, mcelog.entry + i,
1485 sizeof(struct mce));
1486 buf += sizeof(struct mce);
1491 memset(mcelog.entry + prev, 0,
1492 (next - prev) * sizeof(struct mce));
1494 next = cmpxchg(&mcelog.next, prev, 0);
1495 } while (next != prev);
1497 synchronize_sched();
1500 * Collect entries that were still getting written before the
1503 on_each_cpu(collect_tscs, cpu_tsc, 1);
1505 for (i = next; i < MCE_LOG_LEN; i++) {
1506 if (mcelog.entry[i].finished &&
1507 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1508 err |= copy_to_user(buf, mcelog.entry+i,
1509 sizeof(struct mce));
1511 buf += sizeof(struct mce);
1512 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1515 mutex_unlock(&mce_read_mutex);
1518 return err ? -EFAULT : buf - ubuf;
1521 static unsigned int mce_poll(struct file *file, poll_table *wait)
1523 poll_wait(file, &mce_wait, wait);
1524 if (rcu_dereference(mcelog.next))
1525 return POLLIN | POLLRDNORM;
1529 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1531 int __user *p = (int __user *)arg;
1533 if (!capable(CAP_SYS_ADMIN))
1537 case MCE_GET_RECORD_LEN:
1538 return put_user(sizeof(struct mce), p);
1539 case MCE_GET_LOG_LEN:
1540 return put_user(MCE_LOG_LEN, p);
1541 case MCE_GETCLEAR_FLAGS: {
1545 flags = mcelog.flags;
1546 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1548 return put_user(flags, p);
1555 /* Modified in mce-inject.c, so not static or const */
1556 struct file_operations mce_chrdev_ops = {
1558 .release = mce_release,
1561 .unlocked_ioctl = mce_ioctl,
1563 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1565 static struct miscdevice mce_log_device = {
1572 * mce=off Disables machine check
1573 * mce=no_cmci Disables CMCI
1574 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1575 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1576 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1577 * monarchtimeout is how long to wait for other CPUs on machine
1578 * check, or 0 to not wait
1579 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1580 * mce=nobootlog Don't log MCEs from before booting.
1582 static int __init mcheck_enable(char *str)
1590 if (!strcmp(str, "off"))
1592 else if (!strcmp(str, "no_cmci"))
1593 mce_cmci_disabled = 1;
1594 else if (!strcmp(str, "dont_log_ce"))
1595 mce_dont_log_ce = 1;
1596 else if (!strcmp(str, "ignore_ce"))
1598 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1599 mce_bootlog = (str[0] == 'b');
1600 else if (isdigit(str[0])) {
1601 get_option(&str, &tolerant);
1604 get_option(&str, &monarch_timeout);
1607 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1613 __setup("mce", mcheck_enable);
1620 * Disable machine checks on suspend and shutdown. We can't really handle
1623 static int mce_disable(void)
1627 for (i = 0; i < banks; i++) {
1628 struct mce_bank *b = &mce_banks[i];
1630 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1635 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1637 return mce_disable();
1640 static int mce_shutdown(struct sys_device *dev)
1642 return mce_disable();
1646 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1647 * Only one CPU is active at this time, the others get re-added later using
1650 static int mce_resume(struct sys_device *dev)
1653 mce_cpu_features(¤t_cpu_data);
1658 static void mce_cpu_restart(void *data)
1660 del_timer_sync(&__get_cpu_var(mce_timer));
1661 if (!mce_available(¤t_cpu_data))
1667 /* Reinit MCEs after user configuration changes */
1668 static void mce_restart(void)
1670 on_each_cpu(mce_cpu_restart, NULL, 1);
1673 /* Toggle features for corrected errors */
1674 static void mce_disable_ce(void *all)
1676 if (!mce_available(¤t_cpu_data))
1679 del_timer_sync(&__get_cpu_var(mce_timer));
1683 static void mce_enable_ce(void *all)
1685 if (!mce_available(¤t_cpu_data))
1693 static struct sysdev_class mce_sysclass = {
1694 .suspend = mce_suspend,
1695 .shutdown = mce_shutdown,
1696 .resume = mce_resume,
1697 .name = "machinecheck",
1700 DEFINE_PER_CPU(struct sys_device, mce_dev);
1703 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1705 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1707 return container_of(attr, struct mce_bank, attr);
1710 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1713 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1716 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1717 const char *buf, size_t size)
1721 if (strict_strtoull(buf, 0, &new) < 0)
1724 attr_to_bank(attr)->ctl = new;
1731 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1733 strcpy(buf, mce_helper);
1735 return strlen(mce_helper) + 1;
1738 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1739 const char *buf, size_t siz)
1743 strncpy(mce_helper, buf, sizeof(mce_helper));
1744 mce_helper[sizeof(mce_helper)-1] = 0;
1745 p = strchr(mce_helper, '\n');
1750 return strlen(mce_helper) + !!p;
1753 static ssize_t set_ignore_ce(struct sys_device *s,
1754 struct sysdev_attribute *attr,
1755 const char *buf, size_t size)
1759 if (strict_strtoull(buf, 0, &new) < 0)
1762 if (mce_ignore_ce ^ !!new) {
1764 /* disable ce features */
1765 on_each_cpu(mce_disable_ce, (void *)1, 1);
1768 /* enable ce features */
1770 on_each_cpu(mce_enable_ce, (void *)1, 1);
1776 static ssize_t set_cmci_disabled(struct sys_device *s,
1777 struct sysdev_attribute *attr,
1778 const char *buf, size_t size)
1782 if (strict_strtoull(buf, 0, &new) < 0)
1785 if (mce_cmci_disabled ^ !!new) {
1788 on_each_cpu(mce_disable_ce, NULL, 1);
1789 mce_cmci_disabled = 1;
1792 mce_cmci_disabled = 0;
1793 on_each_cpu(mce_enable_ce, NULL, 1);
1799 static ssize_t store_int_with_restart(struct sys_device *s,
1800 struct sysdev_attribute *attr,
1801 const char *buf, size_t size)
1803 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1808 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1809 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1810 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1811 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1813 static struct sysdev_ext_attribute attr_check_interval = {
1814 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1815 store_int_with_restart),
1819 static struct sysdev_ext_attribute attr_ignore_ce = {
1820 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1824 static struct sysdev_ext_attribute attr_cmci_disabled = {
1825 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1829 static struct sysdev_attribute *mce_attrs[] = {
1830 &attr_tolerant.attr,
1831 &attr_check_interval.attr,
1833 &attr_monarch_timeout.attr,
1834 &attr_dont_log_ce.attr,
1835 &attr_ignore_ce.attr,
1836 &attr_cmci_disabled.attr,
1840 static cpumask_var_t mce_dev_initialized;
1842 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1843 static __cpuinit int mce_create_device(unsigned int cpu)
1848 if (!mce_available(&boot_cpu_data))
1851 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1852 per_cpu(mce_dev, cpu).id = cpu;
1853 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1855 err = sysdev_register(&per_cpu(mce_dev, cpu));
1859 for (i = 0; mce_attrs[i]; i++) {
1860 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1864 for (j = 0; j < banks; j++) {
1865 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1866 &mce_banks[j].attr);
1870 cpumask_set_cpu(cpu, mce_dev_initialized);
1875 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
1878 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1880 sysdev_unregister(&per_cpu(mce_dev, cpu));
1885 static __cpuinit void mce_remove_device(unsigned int cpu)
1889 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1892 for (i = 0; mce_attrs[i]; i++)
1893 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1895 for (i = 0; i < banks; i++)
1896 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1898 sysdev_unregister(&per_cpu(mce_dev, cpu));
1899 cpumask_clear_cpu(cpu, mce_dev_initialized);
1902 /* Make sure there are no machine checks on offlined CPUs. */
1903 static void mce_disable_cpu(void *h)
1905 unsigned long action = *(unsigned long *)h;
1908 if (!mce_available(¤t_cpu_data))
1910 if (!(action & CPU_TASKS_FROZEN))
1912 for (i = 0; i < banks; i++) {
1913 struct mce_bank *b = &mce_banks[i];
1915 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1919 static void mce_reenable_cpu(void *h)
1921 unsigned long action = *(unsigned long *)h;
1924 if (!mce_available(¤t_cpu_data))
1927 if (!(action & CPU_TASKS_FROZEN))
1929 for (i = 0; i < banks; i++) {
1930 struct mce_bank *b = &mce_banks[i];
1932 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1936 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1937 static int __cpuinit
1938 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
1940 unsigned int cpu = (unsigned long)hcpu;
1941 struct timer_list *t = &per_cpu(mce_timer, cpu);
1945 case CPU_ONLINE_FROZEN:
1946 mce_create_device(cpu);
1947 if (threshold_cpu_callback)
1948 threshold_cpu_callback(action, cpu);
1951 case CPU_DEAD_FROZEN:
1952 if (threshold_cpu_callback)
1953 threshold_cpu_callback(action, cpu);
1954 mce_remove_device(cpu);
1956 case CPU_DOWN_PREPARE:
1957 case CPU_DOWN_PREPARE_FROZEN:
1959 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
1961 case CPU_DOWN_FAILED:
1962 case CPU_DOWN_FAILED_FROZEN:
1963 t->expires = round_jiffies(jiffies +
1964 __get_cpu_var(mce_next_interval));
1965 add_timer_on(t, cpu);
1966 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
1969 /* intentionally ignoring frozen here */
1970 cmci_rediscover(cpu);
1976 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
1977 .notifier_call = mce_cpu_callback,
1980 static __init void mce_init_banks(void)
1984 for (i = 0; i < banks; i++) {
1985 struct mce_bank *b = &mce_banks[i];
1986 struct sysdev_attribute *a = &b->attr;
1988 a->attr.name = b->attrname;
1989 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
1991 a->attr.mode = 0644;
1992 a->show = show_bank;
1993 a->store = set_bank;
1997 static __init int mce_init_device(void)
2002 if (!mce_available(&boot_cpu_data))
2005 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2009 err = sysdev_class_register(&mce_sysclass);
2013 for_each_online_cpu(i) {
2014 err = mce_create_device(i);
2019 register_hotcpu_notifier(&mce_cpu_notifier);
2020 misc_register(&mce_log_device);
2025 device_initcall(mce_init_device);
2028 * Old style boot options parsing. Only for compatibility.
2030 static int __init mcheck_disable(char *str)
2035 __setup("nomce", mcheck_disable);
2037 #ifdef CONFIG_DEBUG_FS
2038 struct dentry *mce_get_debugfs_dir(void)
2040 static struct dentry *dmce;
2043 dmce = debugfs_create_dir("mce", NULL);
2048 static void mce_reset(void)
2051 atomic_set(&mce_fake_paniced, 0);
2052 atomic_set(&mce_executing, 0);
2053 atomic_set(&mce_callin, 0);
2054 atomic_set(&global_nwo, 0);
2057 static int fake_panic_get(void *data, u64 *val)
2063 static int fake_panic_set(void *data, u64 val)
2070 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2071 fake_panic_set, "%llu\n");
2073 static int __init mce_debugfs_init(void)
2075 struct dentry *dmce, *ffake_panic;
2077 dmce = mce_get_debugfs_dir();
2080 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2087 late_initcall(mce_debugfs_init);