2 * Routines to indentify caches on Intel CPU.
5 * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
6 * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
7 * Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/compiler.h>
14 #include <linux/cpu.h>
15 #include <linux/sched.h>
16 #include <linux/pci.h>
18 #include <asm/processor.h>
30 unsigned char descriptor;
35 /* all the cache descriptor types we care about (no TLB or trace cache entries) */
36 static const struct _cache_table __cpuinitconst cache_table[] =
38 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
39 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
40 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
41 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
42 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
43 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
44 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
45 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
46 { 0x23, LVL_3, 1024 }, /* 8-way set assoc, sectored cache, 64 byte line size */
47 { 0x25, LVL_3, 2048 }, /* 8-way set assoc, sectored cache, 64 byte line size */
48 { 0x29, LVL_3, 4096 }, /* 8-way set assoc, sectored cache, 64 byte line size */
49 { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
50 { 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
51 { 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
52 { 0x3a, LVL_2, 192 }, /* 6-way set assoc, sectored cache, 64 byte line size */
53 { 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */
54 { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
55 { 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */
56 { 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
57 { 0x3f, LVL_2, 256 }, /* 2-way set assoc, 64 byte line size */
58 { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
59 { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
60 { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
61 { 0x44, LVL_2, 1024 }, /* 4-way set assoc, 32 byte line size */
62 { 0x45, LVL_2, 2048 }, /* 4-way set assoc, 32 byte line size */
63 { 0x46, LVL_3, 4096 }, /* 4-way set assoc, 64 byte line size */
64 { 0x47, LVL_3, 8192 }, /* 8-way set assoc, 64 byte line size */
65 { 0x49, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */
66 { 0x4a, LVL_3, 6144 }, /* 12-way set assoc, 64 byte line size */
67 { 0x4b, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
68 { 0x4c, LVL_3, 12288 }, /* 12-way set assoc, 64 byte line size */
69 { 0x4d, LVL_3, 16384 }, /* 16-way set assoc, 64 byte line size */
70 { 0x4e, LVL_2, 6144 }, /* 24-way set assoc, 64 byte line size */
71 { 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
72 { 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
73 { 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
74 { 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
75 { 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */
76 { 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */
77 { 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */
78 { 0x73, LVL_TRACE, 64 }, /* 8-way set assoc */
79 { 0x78, LVL_2, 1024 }, /* 4-way set assoc, 64 byte line size */
80 { 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */
81 { 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */
82 { 0x7b, LVL_2, 512 }, /* 8-way set assoc, sectored cache, 64 byte line size */
83 { 0x7c, LVL_2, 1024 }, /* 8-way set assoc, sectored cache, 64 byte line size */
84 { 0x7d, LVL_2, 2048 }, /* 8-way set assoc, 64 byte line size */
85 { 0x7f, LVL_2, 512 }, /* 2-way set assoc, 64 byte line size */
86 { 0x82, LVL_2, 256 }, /* 8-way set assoc, 32 byte line size */
87 { 0x83, LVL_2, 512 }, /* 8-way set assoc, 32 byte line size */
88 { 0x84, LVL_2, 1024 }, /* 8-way set assoc, 32 byte line size */
89 { 0x85, LVL_2, 2048 }, /* 8-way set assoc, 32 byte line size */
90 { 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */
91 { 0x87, LVL_2, 1024 }, /* 8-way set assoc, 64 byte line size */
92 { 0xd0, LVL_3, 512 }, /* 4-way set assoc, 64 byte line size */
93 { 0xd1, LVL_3, 1024 }, /* 4-way set assoc, 64 byte line size */
94 { 0xd2, LVL_3, 2048 }, /* 4-way set assoc, 64 byte line size */
95 { 0xd6, LVL_3, 1024 }, /* 8-way set assoc, 64 byte line size */
96 { 0xd7, LVL_3, 2038 }, /* 8-way set assoc, 64 byte line size */
97 { 0xd8, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */
98 { 0xdc, LVL_3, 2048 }, /* 12-way set assoc, 64 byte line size */
99 { 0xdd, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */
100 { 0xde, LVL_3, 8192 }, /* 12-way set assoc, 64 byte line size */
101 { 0xe2, LVL_3, 2048 }, /* 16-way set assoc, 64 byte line size */
102 { 0xe3, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */
103 { 0xe4, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
113 CACHE_TYPE_UNIFIED = 3
116 union _cpuid4_leaf_eax {
118 enum _cache_type type:5;
119 unsigned int level:3;
120 unsigned int is_self_initializing:1;
121 unsigned int is_fully_associative:1;
122 unsigned int reserved:4;
123 unsigned int num_threads_sharing:12;
124 unsigned int num_cores_on_die:6;
129 union _cpuid4_leaf_ebx {
131 unsigned int coherency_line_size:12;
132 unsigned int physical_line_partition:10;
133 unsigned int ways_of_associativity:10;
138 union _cpuid4_leaf_ecx {
140 unsigned int number_of_sets:32;
145 struct _cpuid4_info {
146 union _cpuid4_leaf_eax eax;
147 union _cpuid4_leaf_ebx ebx;
148 union _cpuid4_leaf_ecx ecx;
150 unsigned long can_disable;
151 DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
154 /* subset of above _cpuid4_info w/o shared_cpu_map */
155 struct _cpuid4_info_regs {
156 union _cpuid4_leaf_eax eax;
157 union _cpuid4_leaf_ebx ebx;
158 union _cpuid4_leaf_ecx ecx;
160 unsigned long can_disable;
163 unsigned short num_cache_leaves;
165 /* AMD doesn't have CPUID4. Emulate it here to report the same
166 information to the user. This makes some assumptions about the machine:
167 L2 not shared, no SMT etc. that is currently true on AMD CPUs.
169 In theory the TLBs could be reported as fake type (they are in "dummy").
173 unsigned line_size : 8;
174 unsigned lines_per_tag : 8;
176 unsigned size_in_kb : 8;
183 unsigned line_size : 8;
184 unsigned lines_per_tag : 4;
186 unsigned size_in_kb : 16;
193 unsigned line_size : 8;
194 unsigned lines_per_tag : 4;
197 unsigned size_encoded : 14;
202 static const unsigned short __cpuinitconst assocs[] = {
203 [1] = 1, [2] = 2, [4] = 4, [6] = 8,
204 [8] = 16, [0xa] = 32, [0xb] = 48,
209 static const unsigned char __cpuinitconst levels[] = { 1, 1, 2, 3 };
210 static const unsigned char __cpuinitconst types[] = { 1, 2, 3, 3 };
212 static void __cpuinit
213 amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
214 union _cpuid4_leaf_ebx *ebx,
215 union _cpuid4_leaf_ecx *ecx)
218 unsigned line_size, lines_per_tag, assoc, size_in_kb;
219 union l1_cache l1i, l1d;
222 union l1_cache *l1 = &l1d;
228 cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val);
229 cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val);
238 line_size = l1->line_size;
239 lines_per_tag = l1->lines_per_tag;
240 size_in_kb = l1->size_in_kb;
246 line_size = l2.line_size;
247 lines_per_tag = l2.lines_per_tag;
248 /* cpu_data has errata corrections for K7 applied */
249 size_in_kb = current_cpu_data.x86_cache_size;
255 line_size = l3.line_size;
256 lines_per_tag = l3.lines_per_tag;
257 size_in_kb = l3.size_encoded * 512;
263 eax->split.is_self_initializing = 1;
264 eax->split.type = types[leaf];
265 eax->split.level = levels[leaf];
267 eax->split.num_threads_sharing = current_cpu_data.x86_max_cores - 1;
269 eax->split.num_threads_sharing = 0;
270 eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
274 eax->split.is_fully_associative = 1;
275 ebx->split.coherency_line_size = line_size - 1;
276 ebx->split.ways_of_associativity = assocs[assoc] - 1;
277 ebx->split.physical_line_partition = lines_per_tag - 1;
278 ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
279 (ebx->split.ways_of_associativity + 1) - 1;
282 static void __cpuinit
283 amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
288 if (boot_cpu_data.x86 == 0x11)
291 /* see erratum #382 */
292 if ((boot_cpu_data.x86 == 0x10) && (boot_cpu_data.x86_model < 0x8))
295 this_leaf->can_disable = 1;
299 __cpuinit cpuid4_cache_lookup_regs(int index,
300 struct _cpuid4_info_regs *this_leaf)
302 union _cpuid4_leaf_eax eax;
303 union _cpuid4_leaf_ebx ebx;
304 union _cpuid4_leaf_ecx ecx;
307 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
308 amd_cpuid4(index, &eax, &ebx, &ecx);
309 if (boot_cpu_data.x86 >= 0x10)
310 amd_check_l3_disable(index, this_leaf);
312 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
315 if (eax.split.type == CACHE_TYPE_NULL)
316 return -EIO; /* better error ? */
318 this_leaf->eax = eax;
319 this_leaf->ebx = ebx;
320 this_leaf->ecx = ecx;
321 this_leaf->size = (ecx.split.number_of_sets + 1) *
322 (ebx.split.coherency_line_size + 1) *
323 (ebx.split.physical_line_partition + 1) *
324 (ebx.split.ways_of_associativity + 1);
328 static int __cpuinit find_num_cache_leaves(void)
330 unsigned int eax, ebx, ecx, edx;
331 union _cpuid4_leaf_eax cache_eax;
336 /* Do cpuid(4) loop to find out num_cache_leaves */
337 cpuid_count(4, i, &eax, &ebx, &ecx, &edx);
338 cache_eax.full = eax;
339 } while (cache_eax.split.type != CACHE_TYPE_NULL);
343 unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
345 unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */
346 unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
347 unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
348 unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
350 unsigned int cpu = c->cpu_index;
353 if (c->cpuid_level > 3) {
354 static int is_initialized;
356 if (is_initialized == 0) {
357 /* Init num_cache_leaves from boot CPU */
358 num_cache_leaves = find_num_cache_leaves();
363 * Whenever possible use cpuid(4), deterministic cache
364 * parameters cpuid leaf to find the cache details
366 for (i = 0; i < num_cache_leaves; i++) {
367 struct _cpuid4_info_regs this_leaf;
370 retval = cpuid4_cache_lookup_regs(i, &this_leaf);
372 switch(this_leaf.eax.split.level) {
374 if (this_leaf.eax.split.type ==
376 new_l1d = this_leaf.size/1024;
377 else if (this_leaf.eax.split.type ==
379 new_l1i = this_leaf.size/1024;
382 new_l2 = this_leaf.size/1024;
383 num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
384 index_msb = get_count_order(num_threads_sharing);
385 l2_id = c->apicid >> index_msb;
388 new_l3 = this_leaf.size/1024;
389 num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
390 index_msb = get_count_order(num_threads_sharing);
391 l3_id = c->apicid >> index_msb;
400 * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for
403 if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) {
404 /* supports eax=2 call */
406 unsigned int regs[4];
407 unsigned char *dp = (unsigned char *)regs;
410 if (num_cache_leaves != 0 && c->x86 == 15)
413 /* Number of times to iterate */
414 n = cpuid_eax(2) & 0xFF;
416 for ( i = 0 ; i < n ; i++ ) {
417 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
419 /* If bit 31 is set, this is an unknown format */
420 for ( j = 0 ; j < 3 ; j++ ) {
421 if (regs[j] & (1 << 31)) regs[j] = 0;
424 /* Byte 0 is level count, not a descriptor */
425 for ( j = 1 ; j < 16 ; j++ ) {
426 unsigned char des = dp[j];
429 /* look up this descriptor in the table */
430 while (cache_table[k].descriptor != 0)
432 if (cache_table[k].descriptor == des) {
433 if (only_trace && cache_table[k].cache_type != LVL_TRACE)
435 switch (cache_table[k].cache_type) {
437 l1i += cache_table[k].size;
440 l1d += cache_table[k].size;
443 l2 += cache_table[k].size;
446 l3 += cache_table[k].size;
449 trace += cache_table[k].size;
471 per_cpu(cpu_llc_id, cpu) = l2_id;
478 per_cpu(cpu_llc_id, cpu) = l3_id;
483 printk (KERN_INFO "CPU: Trace cache: %dK uops", trace);
485 printk (KERN_INFO "CPU: L1 I cache: %dK", l1i);
488 printk(", L1 D cache: %dK\n", l1d);
493 printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);
496 printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
498 c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
505 /* pointer to _cpuid4_info array (for each cache leaf) */
506 static DEFINE_PER_CPU(struct _cpuid4_info *, cpuid4_info);
507 #define CPUID4_INFO_IDX(x, y) (&((per_cpu(cpuid4_info, x))[y]))
510 static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
512 struct _cpuid4_info *this_leaf, *sibling_leaf;
513 unsigned long num_threads_sharing;
515 struct cpuinfo_x86 *c = &cpu_data(cpu);
517 this_leaf = CPUID4_INFO_IDX(cpu, index);
518 num_threads_sharing = 1 + this_leaf->eax.split.num_threads_sharing;
520 if (num_threads_sharing == 1)
521 cpumask_set_cpu(cpu, to_cpumask(this_leaf->shared_cpu_map));
523 index_msb = get_count_order(num_threads_sharing);
525 for_each_online_cpu(i) {
526 if (cpu_data(i).apicid >> index_msb ==
527 c->apicid >> index_msb) {
529 to_cpumask(this_leaf->shared_cpu_map));
530 if (i != cpu && per_cpu(cpuid4_info, i)) {
532 CPUID4_INFO_IDX(i, index);
533 cpumask_set_cpu(cpu, to_cpumask(
534 sibling_leaf->shared_cpu_map));
540 static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
542 struct _cpuid4_info *this_leaf, *sibling_leaf;
545 this_leaf = CPUID4_INFO_IDX(cpu, index);
546 for_each_cpu(sibling, to_cpumask(this_leaf->shared_cpu_map)) {
547 sibling_leaf = CPUID4_INFO_IDX(sibling, index);
548 cpumask_clear_cpu(cpu,
549 to_cpumask(sibling_leaf->shared_cpu_map));
553 static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index) {}
554 static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index) {}
557 static void __cpuinit free_cache_attributes(unsigned int cpu)
561 for (i = 0; i < num_cache_leaves; i++)
562 cache_remove_shared_cpu_map(cpu, i);
564 kfree(per_cpu(cpuid4_info, cpu));
565 per_cpu(cpuid4_info, cpu) = NULL;
569 __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
571 struct _cpuid4_info_regs *leaf_regs =
572 (struct _cpuid4_info_regs *)this_leaf;
574 return cpuid4_cache_lookup_regs(index, leaf_regs);
577 static void __cpuinit get_cpu_leaves(void *_retval)
579 int j, *retval = _retval, cpu = smp_processor_id();
581 /* Do cpuid and store the results */
582 for (j = 0; j < num_cache_leaves; j++) {
583 struct _cpuid4_info *this_leaf;
584 this_leaf = CPUID4_INFO_IDX(cpu, j);
585 *retval = cpuid4_cache_lookup(j, this_leaf);
586 if (unlikely(*retval < 0)) {
589 for (i = 0; i < j; i++)
590 cache_remove_shared_cpu_map(cpu, i);
593 cache_shared_cpu_map_setup(cpu, j);
597 static int __cpuinit detect_cache_attributes(unsigned int cpu)
601 if (num_cache_leaves == 0)
604 per_cpu(cpuid4_info, cpu) = kzalloc(
605 sizeof(struct _cpuid4_info) * num_cache_leaves, GFP_KERNEL);
606 if (per_cpu(cpuid4_info, cpu) == NULL)
609 smp_call_function_single(cpu, get_cpu_leaves, &retval, true);
611 kfree(per_cpu(cpuid4_info, cpu));
612 per_cpu(cpuid4_info, cpu) = NULL;
618 #include <linux/kobject.h>
619 #include <linux/sysfs.h>
621 extern struct sysdev_class cpu_sysdev_class; /* from drivers/base/cpu.c */
623 /* pointer to kobject for cpuX/cache */
624 static DEFINE_PER_CPU(struct kobject *, cache_kobject);
626 struct _index_kobject {
629 unsigned short index;
632 /* pointer to array of kobjects for cpuX/cache/indexY */
633 static DEFINE_PER_CPU(struct _index_kobject *, index_kobject);
634 #define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(index_kobject, x))[y]))
636 #define show_one_plus(file_name, object, val) \
637 static ssize_t show_##file_name \
638 (struct _cpuid4_info *this_leaf, char *buf) \
640 return sprintf (buf, "%lu\n", (unsigned long)this_leaf->object + val); \
643 show_one_plus(level, eax.split.level, 0);
644 show_one_plus(coherency_line_size, ebx.split.coherency_line_size, 1);
645 show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1);
646 show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1);
647 show_one_plus(number_of_sets, ecx.split.number_of_sets, 1);
649 static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf)
651 return sprintf (buf, "%luK\n", this_leaf->size / 1024);
654 static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
657 ptrdiff_t len = PTR_ALIGN(buf + PAGE_SIZE - 1, PAGE_SIZE) - buf;
661 const struct cpumask *mask;
663 mask = to_cpumask(this_leaf->shared_cpu_map);
665 cpulist_scnprintf(buf, len-2, mask) :
666 cpumask_scnprintf(buf, len-2, mask);
673 static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf)
675 return show_shared_cpu_map_func(leaf, 0, buf);
678 static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf)
680 return show_shared_cpu_map_func(leaf, 1, buf);
683 static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
685 switch (this_leaf->eax.split.type) {
686 case CACHE_TYPE_DATA:
687 return sprintf(buf, "Data\n");
688 case CACHE_TYPE_INST:
689 return sprintf(buf, "Instruction\n");
690 case CACHE_TYPE_UNIFIED:
691 return sprintf(buf, "Unified\n");
693 return sprintf(buf, "Unknown\n");
697 #define to_object(k) container_of(k, struct _index_kobject, kobj)
698 #define to_attr(a) container_of(a, struct _cache_attr, attr)
700 static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
702 const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
703 int node = cpu_to_node(cpumask_first(mask));
704 struct pci_dev *dev = NULL;
708 if (!this_leaf->can_disable)
709 return sprintf(buf, "Feature not enabled\n");
711 dev = node_to_k8_nb_misc(node);
713 printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
717 for (i = 0; i < 2; i++) {
720 pci_read_config_dword(dev, 0x1BC + i * 4, ®);
722 ret += sprintf(buf, "%sEntry: %d\n", buf, i);
723 ret += sprintf(buf, "%sReads: %s\tNew Entries: %s\n",
725 reg & 0x80000000 ? "Disabled" : "Allowed",
726 reg & 0x40000000 ? "Disabled" : "Allowed");
727 ret += sprintf(buf, "%sSubCache: %x\tIndex: %x\n",
728 buf, (reg & 0x30000) >> 16, reg & 0xfff);
734 store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
737 const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
738 int node = cpu_to_node(cpumask_first(mask));
739 struct pci_dev *dev = NULL;
740 unsigned int ret, index, val;
742 if (!this_leaf->can_disable)
745 if (strlen(buf) > 15)
748 ret = sscanf(buf, "%x %x", &index, &val);
755 dev = node_to_k8_nb_misc(node);
757 printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
761 pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
763 pci_write_config_dword(dev, 0x1BC + index * 4, val);
769 struct attribute attr;
770 ssize_t (*show)(struct _cpuid4_info *, char *);
771 ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
774 #define define_one_ro(_name) \
775 static struct _cache_attr _name = \
776 __ATTR(_name, 0444, show_##_name, NULL)
778 define_one_ro(level);
780 define_one_ro(coherency_line_size);
781 define_one_ro(physical_line_partition);
782 define_one_ro(ways_of_associativity);
783 define_one_ro(number_of_sets);
785 define_one_ro(shared_cpu_map);
786 define_one_ro(shared_cpu_list);
788 static struct _cache_attr cache_disable = __ATTR(cache_disable, 0644, show_cache_disable, store_cache_disable);
790 static struct attribute * default_attrs[] = {
793 &coherency_line_size.attr,
794 &physical_line_partition.attr,
795 &ways_of_associativity.attr,
796 &number_of_sets.attr,
798 &shared_cpu_map.attr,
799 &shared_cpu_list.attr,
804 static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf)
806 struct _cache_attr *fattr = to_attr(attr);
807 struct _index_kobject *this_leaf = to_object(kobj);
811 fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
817 static ssize_t store(struct kobject * kobj, struct attribute * attr,
818 const char * buf, size_t count)
820 struct _cache_attr *fattr = to_attr(attr);
821 struct _index_kobject *this_leaf = to_object(kobj);
825 fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
831 static struct sysfs_ops sysfs_ops = {
836 static struct kobj_type ktype_cache = {
837 .sysfs_ops = &sysfs_ops,
838 .default_attrs = default_attrs,
841 static struct kobj_type ktype_percpu_entry = {
842 .sysfs_ops = &sysfs_ops,
845 static void __cpuinit cpuid4_cache_sysfs_exit(unsigned int cpu)
847 kfree(per_cpu(cache_kobject, cpu));
848 kfree(per_cpu(index_kobject, cpu));
849 per_cpu(cache_kobject, cpu) = NULL;
850 per_cpu(index_kobject, cpu) = NULL;
851 free_cache_attributes(cpu);
854 static int __cpuinit cpuid4_cache_sysfs_init(unsigned int cpu)
858 if (num_cache_leaves == 0)
861 err = detect_cache_attributes(cpu);
865 /* Allocate all required memory */
866 per_cpu(cache_kobject, cpu) =
867 kzalloc(sizeof(struct kobject), GFP_KERNEL);
868 if (unlikely(per_cpu(cache_kobject, cpu) == NULL))
871 per_cpu(index_kobject, cpu) = kzalloc(
872 sizeof(struct _index_kobject ) * num_cache_leaves, GFP_KERNEL);
873 if (unlikely(per_cpu(index_kobject, cpu) == NULL))
879 cpuid4_cache_sysfs_exit(cpu);
883 static DECLARE_BITMAP(cache_dev_map, NR_CPUS);
885 /* Add/Remove cache interface for CPU device */
886 static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
888 unsigned int cpu = sys_dev->id;
890 struct _index_kobject *this_object;
893 retval = cpuid4_cache_sysfs_init(cpu);
894 if (unlikely(retval < 0))
897 retval = kobject_init_and_add(per_cpu(cache_kobject, cpu),
899 &sys_dev->kobj, "%s", "cache");
901 cpuid4_cache_sysfs_exit(cpu);
905 for (i = 0; i < num_cache_leaves; i++) {
906 this_object = INDEX_KOBJECT_PTR(cpu,i);
907 this_object->cpu = cpu;
908 this_object->index = i;
909 retval = kobject_init_and_add(&(this_object->kobj),
911 per_cpu(cache_kobject, cpu),
913 if (unlikely(retval)) {
914 for (j = 0; j < i; j++) {
915 kobject_put(&(INDEX_KOBJECT_PTR(cpu,j)->kobj));
917 kobject_put(per_cpu(cache_kobject, cpu));
918 cpuid4_cache_sysfs_exit(cpu);
921 kobject_uevent(&(this_object->kobj), KOBJ_ADD);
923 cpumask_set_cpu(cpu, to_cpumask(cache_dev_map));
925 kobject_uevent(per_cpu(cache_kobject, cpu), KOBJ_ADD);
929 static void __cpuinit cache_remove_dev(struct sys_device * sys_dev)
931 unsigned int cpu = sys_dev->id;
934 if (per_cpu(cpuid4_info, cpu) == NULL)
936 if (!cpumask_test_cpu(cpu, to_cpumask(cache_dev_map)))
938 cpumask_clear_cpu(cpu, to_cpumask(cache_dev_map));
940 for (i = 0; i < num_cache_leaves; i++)
941 kobject_put(&(INDEX_KOBJECT_PTR(cpu,i)->kobj));
942 kobject_put(per_cpu(cache_kobject, cpu));
943 cpuid4_cache_sysfs_exit(cpu);
946 static int __cpuinit cacheinfo_cpu_callback(struct notifier_block *nfb,
947 unsigned long action, void *hcpu)
949 unsigned int cpu = (unsigned long)hcpu;
950 struct sys_device *sys_dev;
952 sys_dev = get_cpu_sysdev(cpu);
955 case CPU_ONLINE_FROZEN:
956 cache_add_dev(sys_dev);
959 case CPU_DEAD_FROZEN:
960 cache_remove_dev(sys_dev);
966 static struct notifier_block __cpuinitdata cacheinfo_cpu_notifier =
968 .notifier_call = cacheinfo_cpu_callback,
971 static int __cpuinit cache_sysfs_init(void)
975 if (num_cache_leaves == 0)
978 for_each_online_cpu(i) {
980 struct sys_device *sys_dev = get_cpu_sysdev(i);
982 err = cache_add_dev(sys_dev);
986 register_hotcpu_notifier(&cacheinfo_cpu_notifier);
990 device_initcall(cache_sysfs_init);