1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
4 #include <linux/string.h>
5 #include <linux/bitops.h>
7 #include <linux/sched.h>
8 #include <linux/sched/clock.h>
9 #include <linux/thread_info.h>
10 #include <linux/init.h>
11 #include <linux/uaccess.h>
13 #include <asm/cpufeature.h>
14 #include <asm/pgtable.h>
18 #include <asm/intel-family.h>
19 #include <asm/microcode_intel.h>
20 #include <asm/hwcap2.h>
24 #include <linux/topology.h>
29 #ifdef CONFIG_X86_LOCAL_APIC
30 #include <asm/mpspec.h>
35 * Just in case our CPU detection goes bad, or you have a weird system,
36 * allow a way to override the automatic disabling of MPX.
40 static int __init forcempx_setup(char *__unused)
46 __setup("intel-skd-046-workaround=disable", forcempx_setup);
48 void check_mpx_erratum(struct cpuinfo_x86 *c)
53 * Turn off the MPX feature on CPUs where SMEP is not
54 * available or disabled.
56 * Works around Intel Erratum SKD046: "Branch Instructions
57 * May Initialize MPX Bound Registers Incorrectly".
59 * This might falsely disable MPX on systems without
60 * SMEP, like Atom processors without SMEP. But there
61 * is no such hardware known at the moment.
63 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) {
64 setup_clear_cpu_cap(X86_FEATURE_MPX);
65 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n");
69 static bool ring3mwait_disabled __read_mostly;
71 static int __init ring3mwait_disable(char *__unused)
73 ring3mwait_disabled = true;
76 __setup("ring3mwait=disable", ring3mwait_disable);
78 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
81 * Ring 3 MONITOR/MWAIT feature cannot be detected without
82 * cpu model and family comparison.
86 switch (c->x86_model) {
87 case INTEL_FAM6_XEON_PHI_KNL:
88 case INTEL_FAM6_XEON_PHI_KNM:
94 if (ring3mwait_disabled)
97 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
98 this_cpu_or(msr_misc_features_shadow,
99 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
101 if (c == &boot_cpu_data)
102 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
106 * Early microcode releases for the Spectre v2 mitigation were broken.
107 * Information taken from;
108 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
109 * - https://kb.vmware.com/s/article/52345
110 * - Microcode revisions observed in the wild
111 * - Release note from 20180108 microcode release
113 struct sku_microcode {
118 static const struct sku_microcode spectre_bad_microcodes[] = {
119 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0B, 0x80 },
120 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0A, 0x80 },
121 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x09, 0x80 },
122 { INTEL_FAM6_KABYLAKE_MOBILE, 0x0A, 0x80 },
123 { INTEL_FAM6_KABYLAKE_MOBILE, 0x09, 0x80 },
124 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
125 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
126 { INTEL_FAM6_BROADWELL_CORE, 0x04, 0x28 },
127 { INTEL_FAM6_BROADWELL_GT3E, 0x01, 0x1b },
128 { INTEL_FAM6_BROADWELL_XEON_D, 0x02, 0x14 },
129 { INTEL_FAM6_BROADWELL_XEON_D, 0x03, 0x07000011 },
130 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
131 { INTEL_FAM6_HASWELL_ULT, 0x01, 0x21 },
132 { INTEL_FAM6_HASWELL_GT3E, 0x01, 0x18 },
133 { INTEL_FAM6_HASWELL_CORE, 0x03, 0x23 },
134 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
135 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
136 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
137 /* Observed in the wild */
138 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
139 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
142 static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
147 * We know that the hypervisor lie to us on the microcode version so
148 * we may as well hope that it is running the correct version.
150 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
153 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
154 if (c->x86_model == spectre_bad_microcodes[i].model &&
155 c->x86_stepping == spectre_bad_microcodes[i].stepping)
156 return (c->microcode <= spectre_bad_microcodes[i].microcode);
161 static void early_init_intel(struct cpuinfo_x86 *c)
165 /* Unmask CPUID levels if masked: */
166 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
167 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
168 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
169 c->cpuid_level = cpuid_eax(0);
174 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
175 (c->x86 == 0x6 && c->x86_model >= 0x0e))
176 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
178 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
179 c->microcode = intel_get_microcode_revision();
181 /* Now if any of them are set, check the blacklist and clear the lot */
182 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
183 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
184 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
185 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
186 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
187 setup_clear_cpu_cap(X86_FEATURE_IBRS);
188 setup_clear_cpu_cap(X86_FEATURE_IBPB);
189 setup_clear_cpu_cap(X86_FEATURE_STIBP);
190 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
191 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
195 * Atom erratum AAE44/AAF40/AAG38/AAH41:
197 * A race condition between speculative fetches and invalidating
198 * a large page. This is worked around in microcode, but we
199 * need the microcode to have already been loaded... so if it is
200 * not, recommend a BIOS update and disable large pages.
202 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
203 c->microcode < 0x20e) {
204 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
205 clear_cpu_cap(c, X86_FEATURE_PSE);
209 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
211 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
212 if (c->x86 == 15 && c->x86_cache_alignment == 64)
213 c->x86_cache_alignment = 128;
216 /* CPUID workaround for 0F33/0F34 CPU */
217 if (c->x86 == 0xF && c->x86_model == 0x3
218 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
219 c->x86_phys_bits = 36;
222 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
223 * with P/T states and does not stop in deep C-states.
225 * It is also reliable across cores and sockets. (but not across
226 * cabinets - we turn it off in that case explicitly.)
228 if (c->x86_power & (1 << 8)) {
229 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
230 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
233 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
235 switch (c->x86_model) {
236 case 0x27: /* Penwell */
237 case 0x35: /* Cloverview */
238 case 0x4a: /* Merrifield */
239 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
247 * There is a known erratum on Pentium III and Core Solo
249 * " Page with PAT set to WC while associated MTRR is UC
250 * may consolidate to UC "
251 * Because of this erratum, it is better to stick with
252 * setting WC in MTRR rather than using PAT on these CPUs.
254 * Enable PAT WC only on P4, Core 2 or later CPUs.
256 if (c->x86 == 6 && c->x86_model < 15)
257 clear_cpu_cap(c, X86_FEATURE_PAT);
260 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
261 * clear the fast string and enhanced fast string CPU capabilities.
263 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
264 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
265 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
266 pr_info("Disabled fast string operations\n");
267 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
268 setup_clear_cpu_cap(X86_FEATURE_ERMS);
273 * Intel Quark Core DevMan_001.pdf section 6.4.11
274 * "The operating system also is required to invalidate (i.e., flush)
275 * the TLB when any changes are made to any of the page table entries.
276 * The operating system must reload CR3 to cause the TLB to be flushed"
278 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
279 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
282 if (c->x86 == 5 && c->x86_model == 9) {
283 pr_info("Disabling PGE capability bit\n");
284 setup_clear_cpu_cap(X86_FEATURE_PGE);
287 if (c->cpuid_level >= 0x00000001) {
288 u32 eax, ebx, ecx, edx;
290 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
292 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
293 * apicids which are reserved per package. Store the resulting
294 * shift value for the package management code.
296 if (edx & (1U << 28))
297 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
300 check_mpx_erratum(c);
305 * Early probe support logic for ppro memory erratum #50
307 * This is called before we do cpu ident work
310 int ppro_with_ram_bug(void)
312 /* Uses data from early_cpu_detect now */
313 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
314 boot_cpu_data.x86 == 6 &&
315 boot_cpu_data.x86_model == 1 &&
316 boot_cpu_data.x86_stepping < 8) {
317 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
323 static void intel_smp_check(struct cpuinfo_x86 *c)
325 /* calling is from identify_secondary_cpu() ? */
330 * Mask B, Pentium, but not Pentium MMX
333 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
336 * Remember we have B step Pentia with bugs
338 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
339 "with B stepping processors.\n");
344 static int __init forcepae_setup(char *__unused)
349 __setup("forcepae", forcepae_setup);
351 static void intel_workarounds(struct cpuinfo_x86 *c)
353 #ifdef CONFIG_X86_F00F_BUG
355 * All models of Pentium and Pentium with MMX technology CPUs
356 * have the F0 0F bug, which lets nonprivileged users lock up the
357 * system. Announce that the fault handler will be checking for it.
358 * The Quark is also family 5, but does not have the same bug.
360 clear_cpu_bug(c, X86_BUG_F00F);
361 if (c->x86 == 5 && c->x86_model < 9) {
362 static int f00f_workaround_enabled;
364 set_cpu_bug(c, X86_BUG_F00F);
365 if (!f00f_workaround_enabled) {
366 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
367 f00f_workaround_enabled = 1;
373 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
376 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
377 clear_cpu_cap(c, X86_FEATURE_SEP);
380 * PAE CPUID issue: many Pentium M report no PAE but may have a
381 * functionally usable PAE implementation.
382 * Forcefully enable PAE if kernel parameter "forcepae" is present.
385 pr_warn("PAE forced!\n");
386 set_cpu_cap(c, X86_FEATURE_PAE);
387 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
391 * P4 Xeon erratum 037 workaround.
392 * Hardware prefetcher may cause stale data to be loaded into the cache.
394 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
395 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
396 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
397 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
398 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
403 * See if we have a good local APIC by checking for buggy Pentia,
404 * i.e. all B steppings and the C2 stepping of P54C when using their
405 * integrated APIC (see 11AP erratum in "Pentium Processor
406 * Specification Update").
408 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
409 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
410 set_cpu_bug(c, X86_BUG_11AP);
413 #ifdef CONFIG_X86_INTEL_USERCOPY
415 * Set up the preferred alignment for movsl bulk memory moves
418 case 4: /* 486: untested */
420 case 5: /* Old Pentia: untested */
422 case 6: /* PII/PIII only like movsl with 8-byte alignment */
425 case 15: /* P4 is OK down to 8-byte alignment */
434 static void intel_workarounds(struct cpuinfo_x86 *c)
439 static void srat_detect_node(struct cpuinfo_x86 *c)
443 int cpu = smp_processor_id();
445 /* Don't do the funky fallback heuristics the AMD version employs
447 node = numa_cpu_node(cpu);
448 if (node == NUMA_NO_NODE || !node_online(node)) {
449 /* reuse the value from init_cpu_to_node() */
450 node = cpu_to_node(cpu);
452 numa_set_node(cpu, node);
457 * find out the number of processor cores on the die
459 static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
461 unsigned int eax, ebx, ecx, edx;
463 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
466 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
467 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
469 return (eax >> 26) + 1;
474 static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
476 /* Intel VMX MSR indicated features */
477 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
478 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
479 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
480 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
481 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
482 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
484 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
486 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
487 clear_cpu_cap(c, X86_FEATURE_VNMI);
488 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
489 clear_cpu_cap(c, X86_FEATURE_EPT);
490 clear_cpu_cap(c, X86_FEATURE_VPID);
492 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
493 msr_ctl = vmx_msr_high | vmx_msr_low;
494 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
495 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
496 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
497 set_cpu_cap(c, X86_FEATURE_VNMI);
498 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
499 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
500 vmx_msr_low, vmx_msr_high);
501 msr_ctl2 = vmx_msr_high | vmx_msr_low;
502 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
503 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
504 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
505 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
506 set_cpu_cap(c, X86_FEATURE_EPT);
507 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
508 set_cpu_cap(c, X86_FEATURE_VPID);
512 static void init_intel_energy_perf(struct cpuinfo_x86 *c)
517 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized.
518 * (x86_energy_perf_policy(8) is available to change it at run-time.)
520 if (!cpu_has(c, X86_FEATURE_EPB))
523 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
524 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE)
527 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
528 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n");
529 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
530 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
533 static void intel_bsp_resume(struct cpuinfo_x86 *c)
536 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume,
537 * so reinitialize it properly like during bootup:
539 init_intel_energy_perf(c);
542 static void init_cpuid_fault(struct cpuinfo_x86 *c)
546 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
547 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
548 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
552 static void init_intel_misc_features(struct cpuinfo_x86 *c)
556 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
559 /* Clear all MISC features */
560 this_cpu_write(msr_misc_features_shadow, 0);
562 /* Check features and update capabilities and shadow control bits */
564 probe_xeon_phi_r3mwait(c);
566 msr = this_cpu_read(msr_misc_features_shadow);
567 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
570 static void init_intel(struct cpuinfo_x86 *c)
576 intel_workarounds(c);
579 * Detect the extended topology information if available. This
580 * will reinitialise the initial_apicid which will be used
581 * in init_intel_cacheinfo()
583 detect_extended_topology(c);
585 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
587 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
590 c->x86_max_cores = intel_num_cpu_cores(c);
596 l2 = init_intel_cacheinfo(c);
598 /* Detect legacy cache sizes if init_intel_cacheinfo did not */
600 cpu_detect_cache_sizes(c);
601 l2 = c->x86_cache_size;
604 if (c->cpuid_level > 9) {
605 unsigned eax = cpuid_eax(10);
606 /* Check for version and the number of counters */
607 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
608 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
611 if (cpu_has(c, X86_FEATURE_XMM2))
612 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
614 if (boot_cpu_has(X86_FEATURE_DS)) {
616 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
618 set_cpu_cap(c, X86_FEATURE_BTS);
620 set_cpu_cap(c, X86_FEATURE_PEBS);
623 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
624 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
625 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
627 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
628 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
629 set_cpu_bug(c, X86_BUG_MONITOR);
633 c->x86_cache_alignment = c->x86_clflush_size * 2;
635 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
638 * Names for the Pentium II/Celeron processors
639 * detectable only by also checking the cache size.
640 * Dixon is NOT a Celeron.
645 switch (c->x86_model) {
648 p = "Celeron (Covington)";
650 p = "Mobile Pentium II (Dixon)";
655 p = "Celeron (Mendocino)";
656 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
662 p = "Celeron (Coppermine)";
667 strcpy(c->x86_model_id, p);
671 set_cpu_cap(c, X86_FEATURE_P4);
673 set_cpu_cap(c, X86_FEATURE_P3);
676 /* Work around errata */
679 if (cpu_has(c, X86_FEATURE_VMX))
680 detect_vmx_virtcap(c);
682 init_intel_energy_perf(c);
684 init_intel_misc_features(c);
688 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
691 * Intel PIII Tualatin. This comes in two flavours.
692 * One has 256kb of cache, the other 512. We have no way
693 * to determine which, so we use a boottime override
694 * for the 512kb model, and assume 256 otherwise.
696 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
700 * Intel Quark SoC X1000 contains a 4-way set associative
701 * 16K cache with a 16 byte cache line and 256 lines per tag
703 if ((c->x86 == 5) && (c->x86_model == 9))
709 #define TLB_INST_4K 0x01
710 #define TLB_INST_4M 0x02
711 #define TLB_INST_2M_4M 0x03
713 #define TLB_INST_ALL 0x05
714 #define TLB_INST_1G 0x06
716 #define TLB_DATA_4K 0x11
717 #define TLB_DATA_4M 0x12
718 #define TLB_DATA_2M_4M 0x13
719 #define TLB_DATA_4K_4M 0x14
721 #define TLB_DATA_1G 0x16
723 #define TLB_DATA0_4K 0x21
724 #define TLB_DATA0_4M 0x22
725 #define TLB_DATA0_2M_4M 0x23
728 #define STLB_4K_2M 0x42
730 static const struct _tlb_table intel_tlb_table[] = {
731 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
732 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
733 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
734 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
735 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
736 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
737 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
738 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
739 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
740 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
741 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
742 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
743 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
744 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
745 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
746 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
747 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
748 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
749 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
750 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
751 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
752 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
753 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
754 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
755 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
756 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
757 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
758 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
759 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
760 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
761 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
762 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
763 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
767 static void intel_tlb_lookup(const unsigned char desc)
773 /* look up this descriptor in the table */
774 for (k = 0; intel_tlb_table[k].descriptor != desc && \
775 intel_tlb_table[k].descriptor != 0; k++)
778 if (intel_tlb_table[k].tlb_type == 0)
781 switch (intel_tlb_table[k].tlb_type) {
783 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
784 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
785 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
786 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
789 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
790 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
791 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
792 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
793 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
794 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
795 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
796 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
797 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
798 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
799 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
800 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
803 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
804 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
805 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
806 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
807 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
808 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
811 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
812 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
815 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
816 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
819 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
820 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
821 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
822 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
826 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
827 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
831 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
832 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
835 case TLB_DATA0_2M_4M:
836 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
837 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
838 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
839 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
842 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
843 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
844 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
845 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
848 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
849 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
854 static void intel_detect_tlb(struct cpuinfo_x86 *c)
857 unsigned int regs[4];
858 unsigned char *desc = (unsigned char *)regs;
860 if (c->cpuid_level < 2)
863 /* Number of times to iterate */
864 n = cpuid_eax(2) & 0xFF;
866 for (i = 0 ; i < n ; i++) {
867 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
869 /* If bit 31 is set, this is an unknown format */
870 for (j = 0 ; j < 3 ; j++)
871 if (regs[j] & (1 << 31))
874 /* Byte 0 is level count, not a descriptor */
875 for (j = 1 ; j < 16 ; j++)
876 intel_tlb_lookup(desc[j]);
880 static const struct cpu_dev intel_cpu_dev = {
882 .c_ident = { "GenuineIntel" },
885 { .family = 4, .model_names =
887 [0] = "486 DX-25/33",
898 { .family = 5, .model_names =
900 [0] = "Pentium 60/66 A-step",
901 [1] = "Pentium 60/66",
902 [2] = "Pentium 75 - 200",
903 [3] = "OverDrive PODP5V83",
905 [7] = "Mobile Pentium 75 - 200",
906 [8] = "Mobile Pentium MMX",
907 [9] = "Quark SoC X1000",
910 { .family = 6, .model_names =
912 [0] = "Pentium Pro A-step",
914 [3] = "Pentium II (Klamath)",
915 [4] = "Pentium II (Deschutes)",
916 [5] = "Pentium II (Deschutes)",
917 [6] = "Mobile Pentium II",
918 [7] = "Pentium III (Katmai)",
919 [8] = "Pentium III (Coppermine)",
920 [10] = "Pentium III (Cascades)",
921 [11] = "Pentium III (Tualatin)",
924 { .family = 15, .model_names =
926 [0] = "Pentium 4 (Unknown)",
927 [1] = "Pentium 4 (Willamette)",
928 [2] = "Pentium 4 (Northwood)",
929 [4] = "Pentium 4 (Foster)",
930 [5] = "Pentium 4 (Foster)",
934 .legacy_cache_size = intel_size_cache,
936 .c_detect_tlb = intel_detect_tlb,
937 .c_early_init = early_init_intel,
938 .c_init = init_intel,
939 .c_bsp_resume = intel_bsp_resume,
940 .c_x86_vendor = X86_VENDOR_INTEL,
943 cpu_dev_register(intel_cpu_dev);