1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/init.h>
18 #include <linux/kprobes.h>
19 #include <linux/kgdb.h>
20 #include <linux/smp.h>
22 #include <linux/syscore_ops.h>
24 #include <asm/stackprotector.h>
25 #include <asm/perf_event.h>
26 #include <asm/mmu_context.h>
27 #include <asm/archrandom.h>
28 #include <asm/hypervisor.h>
29 #include <asm/processor.h>
30 #include <asm/tlbflush.h>
31 #include <asm/debugreg.h>
32 #include <asm/sections.h>
33 #include <asm/vsyscall.h>
34 #include <linux/topology.h>
35 #include <linux/cpumask.h>
36 #include <asm/pgtable.h>
37 #include <linux/atomic.h>
38 #include <asm/proto.h>
39 #include <asm/setup.h>
42 #include <asm/fpu/internal.h>
44 #include <asm/hwcap2.h>
45 #include <linux/numa.h>
52 #include <asm/microcode.h>
53 #include <asm/microcode_intel.h>
54 #include <asm/intel-family.h>
55 #include <asm/cpu_device_id.h>
57 #ifdef CONFIG_X86_LOCAL_APIC
58 #include <asm/uv/uv.h>
63 u32 elf_hwcap2 __read_mostly;
65 /* all of these masks are initialized in setup_cpu_local_masks() */
66 cpumask_var_t cpu_initialized_mask;
67 cpumask_var_t cpu_callout_mask;
68 cpumask_var_t cpu_callin_mask;
70 /* representing cpus for which sibling maps can be computed */
71 cpumask_var_t cpu_sibling_setup_mask;
73 /* Number of siblings per CPU package */
74 int smp_num_siblings = 1;
75 EXPORT_SYMBOL(smp_num_siblings);
77 /* Last level cache ID of each logical CPU */
78 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
80 /* correctly size the local cpu masks */
81 void __init setup_cpu_local_masks(void)
83 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
84 alloc_bootmem_cpumask_var(&cpu_callin_mask);
85 alloc_bootmem_cpumask_var(&cpu_callout_mask);
86 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
89 static void default_init(struct cpuinfo_x86 *c)
92 cpu_detect_cache_sizes(c);
94 /* Not much we can do here... */
95 /* Check if at least it has cpuid */
96 if (c->cpuid_level == -1) {
97 /* No cpuid. It must be an ancient CPU */
99 strcpy(c->x86_model_id, "486");
100 else if (c->x86 == 3)
101 strcpy(c->x86_model_id, "386");
106 static const struct cpu_dev default_cpu = {
107 .c_init = default_init,
108 .c_vendor = "Unknown",
109 .c_x86_vendor = X86_VENDOR_UNKNOWN,
112 static const struct cpu_dev *this_cpu = &default_cpu;
114 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
117 * We need valid kernel segments for data and code in long mode too
118 * IRET will check the segment types kkeil 2000/10/28
119 * Also sysret mandates a special GDT layout
121 * TLS descriptors are currently at a different place compared to i386.
122 * Hopefully nobody expects them at a fixed place (Wine?)
124 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
125 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
126 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
127 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
128 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
129 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
131 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
132 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
133 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
134 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
136 * Segments used for calling PnP BIOS have byte granularity.
137 * They code segments and data segments have fixed 64k limits,
138 * the transfer segment sizes are set at run time.
141 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
143 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
145 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
147 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
149 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
151 * The APM segments have byte granularity and their bases
152 * are set at run time. All have 64k limits.
155 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
157 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
159 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
161 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
162 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
163 GDT_STACK_CANARY_INIT
166 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
168 static int __init x86_mpx_setup(char *s)
170 /* require an exact match without trailing characters */
174 /* do not emit a message if the feature is not present */
175 if (!boot_cpu_has(X86_FEATURE_MPX))
178 setup_clear_cpu_cap(X86_FEATURE_MPX);
179 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
182 __setup("nompx", x86_mpx_setup);
185 static int __init x86_nopcid_setup(char *s)
187 /* nopcid doesn't accept parameters */
191 /* do not emit a message if the feature is not present */
192 if (!boot_cpu_has(X86_FEATURE_PCID))
195 setup_clear_cpu_cap(X86_FEATURE_PCID);
196 pr_info("nopcid: PCID feature disabled\n");
199 early_param("nopcid", x86_nopcid_setup);
202 static int __init x86_noinvpcid_setup(char *s)
204 /* noinvpcid doesn't accept parameters */
208 /* do not emit a message if the feature is not present */
209 if (!boot_cpu_has(X86_FEATURE_INVPCID))
212 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
213 pr_info("noinvpcid: INVPCID feature disabled\n");
216 early_param("noinvpcid", x86_noinvpcid_setup);
219 static int cachesize_override = -1;
220 static int disable_x86_serial_nr = 1;
222 static int __init cachesize_setup(char *str)
224 get_option(&str, &cachesize_override);
227 __setup("cachesize=", cachesize_setup);
229 static int __init x86_sep_setup(char *s)
231 setup_clear_cpu_cap(X86_FEATURE_SEP);
234 __setup("nosep", x86_sep_setup);
236 /* Standard macro to see if a specific flag is changeable */
237 static inline int flag_is_changeable_p(u32 flag)
242 * Cyrix and IDT cpus allow disabling of CPUID
243 * so the code below may return different results
244 * when it is executed before and after enabling
245 * the CPUID. Add "volatile" to not allow gcc to
246 * optimize the subsequent calls to this function.
248 asm volatile ("pushfl \n\t"
259 : "=&r" (f1), "=&r" (f2)
262 return ((f1^f2) & flag) != 0;
265 /* Probe for the CPUID instruction */
266 int have_cpuid_p(void)
268 return flag_is_changeable_p(X86_EFLAGS_ID);
271 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
273 unsigned long lo, hi;
275 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
278 /* Disable processor serial number: */
280 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
282 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
284 pr_notice("CPU serial number disabled.\n");
285 clear_cpu_cap(c, X86_FEATURE_PN);
287 /* Disabling the serial number may affect the cpuid level */
288 c->cpuid_level = cpuid_eax(0);
291 static int __init x86_serial_nr_setup(char *s)
293 disable_x86_serial_nr = 0;
296 __setup("serialnumber", x86_serial_nr_setup);
298 static inline int flag_is_changeable_p(u32 flag)
302 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
307 static __init int setup_disable_smep(char *arg)
309 setup_clear_cpu_cap(X86_FEATURE_SMEP);
310 /* Check for things that depend on SMEP being enabled: */
311 check_mpx_erratum(&boot_cpu_data);
314 __setup("nosmep", setup_disable_smep);
316 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
318 if (cpu_has(c, X86_FEATURE_SMEP))
319 cr4_set_bits(X86_CR4_SMEP);
322 static __init int setup_disable_smap(char *arg)
324 setup_clear_cpu_cap(X86_FEATURE_SMAP);
327 __setup("nosmap", setup_disable_smap);
329 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
331 unsigned long eflags = native_save_fl();
333 /* This should have been cleared long ago */
334 BUG_ON(eflags & X86_EFLAGS_AC);
336 if (cpu_has(c, X86_FEATURE_SMAP)) {
337 #ifdef CONFIG_X86_SMAP
338 cr4_set_bits(X86_CR4_SMAP);
340 cr4_clear_bits(X86_CR4_SMAP);
345 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
347 /* Check the boot processor, plus build option for UMIP. */
348 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
351 /* Check the current processor's cpuid bits. */
352 if (!cpu_has(c, X86_FEATURE_UMIP))
355 cr4_set_bits(X86_CR4_UMIP);
357 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
363 * Make sure UMIP is disabled in case it was enabled in a
364 * previous boot (e.g., via kexec).
366 cr4_clear_bits(X86_CR4_UMIP);
369 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
370 static unsigned long cr4_pinned_bits __ro_after_init;
372 void native_write_cr0(unsigned long val)
374 unsigned long bits_missing = 0;
377 asm volatile("mov %0,%%cr0": "+r" (val), "+m" (__force_order));
379 if (static_branch_likely(&cr_pinning)) {
380 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
381 bits_missing = X86_CR0_WP;
385 /* Warn after we've set the missing bits. */
386 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
389 EXPORT_SYMBOL(native_write_cr0);
391 void native_write_cr4(unsigned long val)
393 unsigned long bits_missing = 0;
396 asm volatile("mov %0,%%cr4": "+r" (val), "+m" (cr4_pinned_bits));
398 if (static_branch_likely(&cr_pinning)) {
399 if (unlikely((val & cr4_pinned_bits) != cr4_pinned_bits)) {
400 bits_missing = ~val & cr4_pinned_bits;
404 /* Warn after we've set the missing bits. */
405 WARN_ONCE(bits_missing, "CR4 bits went missing: %lx!?\n",
409 EXPORT_SYMBOL(native_write_cr4);
413 unsigned long cr4 = __read_cr4();
415 if (boot_cpu_has(X86_FEATURE_PCID))
416 cr4 |= X86_CR4_PCIDE;
417 if (static_branch_likely(&cr_pinning))
418 cr4 |= cr4_pinned_bits;
422 /* Initialize cr4 shadow for this CPU. */
423 this_cpu_write(cpu_tlbstate.cr4, cr4);
427 * Once CPU feature detection is finished (and boot params have been
428 * parsed), record any of the sensitive CR bits that are set, and
431 static void __init setup_cr_pinning(void)
435 mask = (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP);
436 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & mask;
437 static_key_enable(&cr_pinning.key);
441 * Protection Keys are not available in 32-bit mode.
443 static bool pku_disabled;
445 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
447 struct pkru_state *pk;
449 /* check the boot processor, plus compile options for PKU: */
450 if (!cpu_feature_enabled(X86_FEATURE_PKU))
452 /* checks the actual processor's cpuid bits: */
453 if (!cpu_has(c, X86_FEATURE_PKU))
458 cr4_set_bits(X86_CR4_PKE);
459 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU);
461 pk->pkru = init_pkru_value;
463 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
464 * cpuid bit to be set. We need to ensure that we
465 * update that bit in this CPU's "cpu_info".
470 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
471 static __init int setup_disable_pku(char *arg)
474 * Do not clear the X86_FEATURE_PKU bit. All of the
475 * runtime checks are against OSPKE so clearing the
478 * This way, we will see "pku" in cpuinfo, but not
479 * "ospke", which is exactly what we want. It shows
480 * that the CPU has PKU, but the OS has not enabled it.
481 * This happens to be exactly how a system would look
482 * if we disabled the config option.
484 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
488 __setup("nopku", setup_disable_pku);
489 #endif /* CONFIG_X86_64 */
492 * Some CPU features depend on higher CPUID levels, which may not always
493 * be available due to CPUID level capping or broken virtualization
494 * software. Add those features to this table to auto-disable them.
496 struct cpuid_dependent_feature {
501 static const struct cpuid_dependent_feature
502 cpuid_dependent_features[] = {
503 { X86_FEATURE_MWAIT, 0x00000005 },
504 { X86_FEATURE_DCA, 0x00000009 },
505 { X86_FEATURE_XSAVE, 0x0000000d },
509 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
511 const struct cpuid_dependent_feature *df;
513 for (df = cpuid_dependent_features; df->feature; df++) {
515 if (!cpu_has(c, df->feature))
518 * Note: cpuid_level is set to -1 if unavailable, but
519 * extended_extended_level is set to 0 if unavailable
520 * and the legitimate extended levels are all negative
521 * when signed; hence the weird messing around with
524 if (!((s32)df->level < 0 ?
525 (u32)df->level > (u32)c->extended_cpuid_level :
526 (s32)df->level > (s32)c->cpuid_level))
529 clear_cpu_cap(c, df->feature);
533 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
534 x86_cap_flag(df->feature), df->level);
539 * Naming convention should be: <Name> [(<Codename>)]
540 * This table only is used unless init_<vendor>() below doesn't set it;
541 * in particular, if CPUID levels 0x80000002..4 are supported, this
545 /* Look up CPU names by table lookup. */
546 static const char *table_lookup_model(struct cpuinfo_x86 *c)
549 const struct legacy_cpu_model_info *info;
551 if (c->x86_model >= 16)
552 return NULL; /* Range check */
557 info = this_cpu->legacy_models;
559 while (info->family) {
560 if (info->family == c->x86)
561 return info->model_names[c->x86_model];
565 return NULL; /* Not found */
568 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
569 __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
571 void load_percpu_segment(int cpu)
574 loadsegment(fs, __KERNEL_PERCPU);
576 __loadsegment_simple(gs, 0);
577 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
579 load_stack_canary_segment();
583 /* The 32-bit entry code needs to find cpu_entry_area. */
584 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
587 /* Load the original GDT from the per-cpu structure */
588 void load_direct_gdt(int cpu)
590 struct desc_ptr gdt_descr;
592 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
593 gdt_descr.size = GDT_SIZE - 1;
594 load_gdt(&gdt_descr);
596 EXPORT_SYMBOL_GPL(load_direct_gdt);
598 /* Load a fixmap remapping of the per-cpu GDT */
599 void load_fixmap_gdt(int cpu)
601 struct desc_ptr gdt_descr;
603 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
604 gdt_descr.size = GDT_SIZE - 1;
605 load_gdt(&gdt_descr);
607 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
610 * Current gdt points %fs at the "master" per-cpu area: after this,
611 * it's on the real one.
613 void switch_to_new_gdt(int cpu)
615 /* Load the original GDT */
616 load_direct_gdt(cpu);
617 /* Reload the per-cpu base */
618 load_percpu_segment(cpu);
621 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
623 static void get_model_name(struct cpuinfo_x86 *c)
628 if (c->extended_cpuid_level < 0x80000004)
631 v = (unsigned int *)c->x86_model_id;
632 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
633 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
634 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
635 c->x86_model_id[48] = 0;
637 /* Trim whitespace */
638 p = q = s = &c->x86_model_id[0];
644 /* Note the last non-whitespace index */
654 void detect_num_cpu_cores(struct cpuinfo_x86 *c)
656 unsigned int eax, ebx, ecx, edx;
658 c->x86_max_cores = 1;
659 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
662 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
664 c->x86_max_cores = (eax >> 26) + 1;
667 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
669 unsigned int n, dummy, ebx, ecx, edx, l2size;
671 n = c->extended_cpuid_level;
673 if (n >= 0x80000005) {
674 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
675 c->x86_cache_size = (ecx>>24) + (edx>>24);
677 /* On K8 L1 TLB is inclusive, so don't count it */
682 if (n < 0x80000006) /* Some chips just has a large L1. */
685 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
689 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
691 /* do processor-specific cache resizing */
692 if (this_cpu->legacy_cache_size)
693 l2size = this_cpu->legacy_cache_size(c, l2size);
695 /* Allow user to override all this if necessary. */
696 if (cachesize_override != -1)
697 l2size = cachesize_override;
700 return; /* Again, no L2 cache is possible */
703 c->x86_cache_size = l2size;
706 u16 __read_mostly tlb_lli_4k[NR_INFO];
707 u16 __read_mostly tlb_lli_2m[NR_INFO];
708 u16 __read_mostly tlb_lli_4m[NR_INFO];
709 u16 __read_mostly tlb_lld_4k[NR_INFO];
710 u16 __read_mostly tlb_lld_2m[NR_INFO];
711 u16 __read_mostly tlb_lld_4m[NR_INFO];
712 u16 __read_mostly tlb_lld_1g[NR_INFO];
714 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
716 if (this_cpu->c_detect_tlb)
717 this_cpu->c_detect_tlb(c);
719 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
720 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
721 tlb_lli_4m[ENTRIES]);
723 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
724 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
725 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
728 int detect_ht_early(struct cpuinfo_x86 *c)
731 u32 eax, ebx, ecx, edx;
733 if (!cpu_has(c, X86_FEATURE_HT))
736 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
739 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
742 cpuid(1, &eax, &ebx, &ecx, &edx);
744 smp_num_siblings = (ebx & 0xff0000) >> 16;
745 if (smp_num_siblings == 1)
746 pr_info_once("CPU0: Hyper-Threading is disabled\n");
751 void detect_ht(struct cpuinfo_x86 *c)
754 int index_msb, core_bits;
756 if (detect_ht_early(c) < 0)
759 index_msb = get_count_order(smp_num_siblings);
760 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
762 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
764 index_msb = get_count_order(smp_num_siblings);
766 core_bits = get_count_order(c->x86_max_cores);
768 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
769 ((1 << core_bits) - 1);
773 static void get_cpu_vendor(struct cpuinfo_x86 *c)
775 char *v = c->x86_vendor_id;
778 for (i = 0; i < X86_VENDOR_NUM; i++) {
782 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
783 (cpu_devs[i]->c_ident[1] &&
784 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
786 this_cpu = cpu_devs[i];
787 c->x86_vendor = this_cpu->c_x86_vendor;
792 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
793 "CPU: Your system may be unstable.\n", v);
795 c->x86_vendor = X86_VENDOR_UNKNOWN;
796 this_cpu = &default_cpu;
799 void cpu_detect(struct cpuinfo_x86 *c)
801 /* Get vendor name */
802 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
803 (unsigned int *)&c->x86_vendor_id[0],
804 (unsigned int *)&c->x86_vendor_id[8],
805 (unsigned int *)&c->x86_vendor_id[4]);
808 /* Intel-defined flags: level 0x00000001 */
809 if (c->cpuid_level >= 0x00000001) {
810 u32 junk, tfms, cap0, misc;
812 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
813 c->x86 = x86_family(tfms);
814 c->x86_model = x86_model(tfms);
815 c->x86_stepping = x86_stepping(tfms);
817 if (cap0 & (1<<19)) {
818 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
819 c->x86_cache_alignment = c->x86_clflush_size;
824 static void apply_forced_caps(struct cpuinfo_x86 *c)
828 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
829 c->x86_capability[i] &= ~cpu_caps_cleared[i];
830 c->x86_capability[i] |= cpu_caps_set[i];
834 static void init_speculation_control(struct cpuinfo_x86 *c)
837 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
838 * and they also have a different bit for STIBP support. Also,
839 * a hypervisor might have set the individual AMD bits even on
840 * Intel CPUs, for finer-grained selection of what's available.
842 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
843 set_cpu_cap(c, X86_FEATURE_IBRS);
844 set_cpu_cap(c, X86_FEATURE_IBPB);
845 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
848 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
849 set_cpu_cap(c, X86_FEATURE_STIBP);
851 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
852 cpu_has(c, X86_FEATURE_VIRT_SSBD))
853 set_cpu_cap(c, X86_FEATURE_SSBD);
855 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
856 set_cpu_cap(c, X86_FEATURE_IBRS);
857 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
860 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
861 set_cpu_cap(c, X86_FEATURE_IBPB);
863 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
864 set_cpu_cap(c, X86_FEATURE_STIBP);
865 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
868 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
869 set_cpu_cap(c, X86_FEATURE_SSBD);
870 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
871 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
875 static void init_cqm(struct cpuinfo_x86 *c)
877 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) {
878 c->x86_cache_max_rmid = -1;
879 c->x86_cache_occ_scale = -1;
883 /* will be overridden if occupancy monitoring exists */
884 c->x86_cache_max_rmid = cpuid_ebx(0xf);
886 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) ||
887 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) ||
888 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) {
889 u32 eax, ebx, ecx, edx;
891 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
892 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx);
894 c->x86_cache_max_rmid = ecx;
895 c->x86_cache_occ_scale = ebx;
899 void get_cpu_cap(struct cpuinfo_x86 *c)
901 u32 eax, ebx, ecx, edx;
903 /* Intel-defined flags: level 0x00000001 */
904 if (c->cpuid_level >= 0x00000001) {
905 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
907 c->x86_capability[CPUID_1_ECX] = ecx;
908 c->x86_capability[CPUID_1_EDX] = edx;
911 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
912 if (c->cpuid_level >= 0x00000006)
913 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
915 /* Additional Intel-defined flags: level 0x00000007 */
916 if (c->cpuid_level >= 0x00000007) {
917 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
918 c->x86_capability[CPUID_7_0_EBX] = ebx;
919 c->x86_capability[CPUID_7_ECX] = ecx;
920 c->x86_capability[CPUID_7_EDX] = edx;
922 /* Check valid sub-leaf index before accessing it */
924 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
925 c->x86_capability[CPUID_7_1_EAX] = eax;
929 /* Extended state features: level 0x0000000d */
930 if (c->cpuid_level >= 0x0000000d) {
931 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
933 c->x86_capability[CPUID_D_1_EAX] = eax;
936 /* AMD-defined flags: level 0x80000001 */
937 eax = cpuid_eax(0x80000000);
938 c->extended_cpuid_level = eax;
940 if ((eax & 0xffff0000) == 0x80000000) {
941 if (eax >= 0x80000001) {
942 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
944 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
945 c->x86_capability[CPUID_8000_0001_EDX] = edx;
949 if (c->extended_cpuid_level >= 0x80000007) {
950 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
952 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
956 if (c->extended_cpuid_level >= 0x80000008) {
957 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
958 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
961 if (c->extended_cpuid_level >= 0x8000000a)
962 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
964 init_scattered_cpuid_features(c);
965 init_speculation_control(c);
969 * Clear/Set all flags overridden by options, after probe.
970 * This needs to happen each time we re-probe, which may happen
971 * several times during CPU initialization.
973 apply_forced_caps(c);
976 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
978 u32 eax, ebx, ecx, edx;
980 if (c->extended_cpuid_level >= 0x80000008) {
981 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
983 c->x86_virt_bits = (eax >> 8) & 0xff;
984 c->x86_phys_bits = eax & 0xff;
987 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
988 c->x86_phys_bits = 36;
990 c->x86_cache_bits = c->x86_phys_bits;
993 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
999 * First of all, decide if this is a 486 or higher
1000 * It's a 486 if we can modify the AC flag
1002 if (flag_is_changeable_p(X86_EFLAGS_AC))
1007 for (i = 0; i < X86_VENDOR_NUM; i++)
1008 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1009 c->x86_vendor_id[0] = 0;
1010 cpu_devs[i]->c_identify(c);
1011 if (c->x86_vendor_id[0]) {
1019 #define NO_SPECULATION BIT(0)
1020 #define NO_MELTDOWN BIT(1)
1021 #define NO_SSB BIT(2)
1022 #define NO_L1TF BIT(3)
1023 #define NO_MDS BIT(4)
1024 #define MSBDS_ONLY BIT(5)
1025 #define NO_SWAPGS BIT(6)
1027 #define VULNWL(_vendor, _family, _model, _whitelist) \
1028 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
1030 #define VULNWL_INTEL(model, whitelist) \
1031 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1033 #define VULNWL_AMD(family, whitelist) \
1034 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1036 #define VULNWL_HYGON(family, whitelist) \
1037 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1039 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1040 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1041 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1042 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1043 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1045 /* Intel Family 6 */
1046 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION),
1047 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION),
1048 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION),
1049 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION),
1050 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION),
1052 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
1053 VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
1054 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
1055 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
1056 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
1057 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
1059 VULNWL_INTEL(CORE_YONAH, NO_SSB),
1061 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
1063 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS),
1064 VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF | NO_SWAPGS),
1065 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS),
1068 * Technically, swapgs isn't serializing on AMD (despite it previously
1069 * being documented as such in the APM). But according to AMD, %gs is
1070 * updated non-speculatively, and the issuing of %gs-relative memory
1071 * operands will be blocked until the %gs update completes, which is
1072 * good enough for our purposes.
1075 /* AMD Family 0xf - 0x12 */
1076 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS),
1077 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS),
1078 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS),
1079 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS),
1081 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1082 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS),
1083 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS),
1087 static bool __init cpu_matches(unsigned long which)
1089 const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist);
1091 return m && !!(m->driver_data & which);
1094 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1098 if (cpu_matches(NO_SPECULATION))
1101 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1102 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1104 if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
1105 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1107 if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) &&
1108 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1109 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1111 if (ia32_cap & ARCH_CAP_IBRS_ALL)
1112 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1114 if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) {
1115 setup_force_cpu_bug(X86_BUG_MDS);
1116 if (cpu_matches(MSBDS_ONLY))
1117 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1120 if (!cpu_matches(NO_SWAPGS))
1121 setup_force_cpu_bug(X86_BUG_SWAPGS);
1123 if (cpu_matches(NO_MELTDOWN))
1126 /* Rogue Data Cache Load? No! */
1127 if (ia32_cap & ARCH_CAP_RDCL_NO)
1130 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1132 if (cpu_matches(NO_L1TF))
1135 setup_force_cpu_bug(X86_BUG_L1TF);
1139 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1140 * unfortunately, that's not true in practice because of early VIA
1141 * chips and (more importantly) broken virtualizers that are not easy
1142 * to detect. In the latter case it doesn't even *fail* reliably, so
1143 * probing for it doesn't even work. Disable it completely on 32-bit
1144 * unless we can find a reliable way to detect all the broken cases.
1145 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1147 static void detect_nopl(void)
1149 #ifdef CONFIG_X86_32
1150 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1152 setup_force_cpu_cap(X86_FEATURE_NOPL);
1157 * Do minimum CPU detection early.
1158 * Fields really needed: vendor, cpuid_level, family, model, mask,
1160 * The others are not touched to avoid unwanted side effects.
1162 * WARNING: this function is only called on the boot CPU. Don't add code
1163 * here that is supposed to run on all CPUs.
1165 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1167 #ifdef CONFIG_X86_64
1168 c->x86_clflush_size = 64;
1169 c->x86_phys_bits = 36;
1170 c->x86_virt_bits = 48;
1172 c->x86_clflush_size = 32;
1173 c->x86_phys_bits = 32;
1174 c->x86_virt_bits = 32;
1176 c->x86_cache_alignment = c->x86_clflush_size;
1178 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1179 c->extended_cpuid_level = 0;
1181 if (!have_cpuid_p())
1182 identify_cpu_without_cpuid(c);
1184 /* cyrix could have cpuid enabled via c_identify()*/
1185 if (have_cpuid_p()) {
1189 get_cpu_address_sizes(c);
1190 setup_force_cpu_cap(X86_FEATURE_CPUID);
1192 if (this_cpu->c_early_init)
1193 this_cpu->c_early_init(c);
1196 filter_cpuid_features(c, false);
1198 if (this_cpu->c_bsp_init)
1199 this_cpu->c_bsp_init(c);
1201 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1204 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1206 cpu_set_bug_bits(c);
1208 fpu__init_system(c);
1210 #ifdef CONFIG_X86_32
1212 * Regardless of whether PCID is enumerated, the SDM says
1213 * that it can't be enabled in 32-bit mode.
1215 setup_clear_cpu_cap(X86_FEATURE_PCID);
1219 * Later in the boot process pgtable_l5_enabled() relies on
1220 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1221 * enabled by this point we need to clear the feature bit to avoid
1222 * false-positives at the later stage.
1224 * pgtable_l5_enabled() can be false here for several reasons:
1225 * - 5-level paging is disabled compile-time;
1226 * - it's 32-bit kernel;
1227 * - machine doesn't support 5-level paging;
1228 * - user specified 'no5lvl' in kernel command line.
1230 if (!pgtable_l5_enabled())
1231 setup_clear_cpu_cap(X86_FEATURE_LA57);
1236 void __init early_cpu_init(void)
1238 const struct cpu_dev *const *cdev;
1241 #ifdef CONFIG_PROCESSOR_SELECT
1242 pr_info("KERNEL supported cpus:\n");
1245 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1246 const struct cpu_dev *cpudev = *cdev;
1248 if (count >= X86_VENDOR_NUM)
1250 cpu_devs[count] = cpudev;
1253 #ifdef CONFIG_PROCESSOR_SELECT
1257 for (j = 0; j < 2; j++) {
1258 if (!cpudev->c_ident[j])
1260 pr_info(" %s %s\n", cpudev->c_vendor,
1261 cpudev->c_ident[j]);
1266 early_identify_cpu(&boot_cpu_data);
1269 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
1271 #ifdef CONFIG_X86_64
1273 * Empirically, writing zero to a segment selector on AMD does
1274 * not clear the base, whereas writing zero to a segment
1275 * selector on Intel does clear the base. Intel's behavior
1276 * allows slightly faster context switches in the common case
1277 * where GS is unused by the prev and next threads.
1279 * Since neither vendor documents this anywhere that I can see,
1280 * detect it directly instead of hardcoding the choice by
1283 * I've designated AMD's behavior as the "bug" because it's
1284 * counterintuitive and less friendly.
1287 unsigned long old_base, tmp;
1288 rdmsrl(MSR_FS_BASE, old_base);
1289 wrmsrl(MSR_FS_BASE, 1);
1291 rdmsrl(MSR_FS_BASE, tmp);
1293 set_cpu_bug(c, X86_BUG_NULL_SEG);
1294 wrmsrl(MSR_FS_BASE, old_base);
1298 static void generic_identify(struct cpuinfo_x86 *c)
1300 c->extended_cpuid_level = 0;
1302 if (!have_cpuid_p())
1303 identify_cpu_without_cpuid(c);
1305 /* cyrix could have cpuid enabled via c_identify()*/
1306 if (!have_cpuid_p())
1315 get_cpu_address_sizes(c);
1317 if (c->cpuid_level >= 0x00000001) {
1318 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1319 #ifdef CONFIG_X86_32
1321 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1323 c->apicid = c->initial_apicid;
1326 c->phys_proc_id = c->initial_apicid;
1329 get_model_name(c); /* Default name */
1331 detect_null_seg_behavior(c);
1334 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1335 * systems that run Linux at CPL > 0 may or may not have the
1336 * issue, but, even if they have the issue, there's absolutely
1337 * nothing we can do about it because we can't use the real IRET
1340 * NB: For the time being, only 32-bit kernels support
1341 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1342 * whether to apply espfix using paravirt hooks. If any
1343 * non-paravirt system ever shows up that does *not* have the
1344 * ESPFIX issue, we can change this.
1346 #ifdef CONFIG_X86_32
1347 # ifdef CONFIG_PARAVIRT_XXL
1349 extern void native_iret(void);
1350 if (pv_ops.cpu.iret == native_iret)
1351 set_cpu_bug(c, X86_BUG_ESPFIX);
1354 set_cpu_bug(c, X86_BUG_ESPFIX);
1359 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
1362 * The heavy lifting of max_rmid and cache_occ_scale are handled
1363 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1364 * in case CQM bits really aren't there in this CPU.
1366 if (c != &boot_cpu_data) {
1367 boot_cpu_data.x86_cache_max_rmid =
1368 min(boot_cpu_data.x86_cache_max_rmid,
1369 c->x86_cache_max_rmid);
1374 * Validate that ACPI/mptables have the same information about the
1375 * effective APIC id and update the package map.
1377 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1380 unsigned int apicid, cpu = smp_processor_id();
1382 apicid = apic->cpu_present_to_apicid(cpu);
1384 if (apicid != c->apicid) {
1385 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1386 cpu, apicid, c->initial_apicid);
1388 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1389 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu));
1391 c->logical_proc_id = 0;
1396 * This does the hard work of actually picking apart the CPU stuff...
1398 static void identify_cpu(struct cpuinfo_x86 *c)
1402 c->loops_per_jiffy = loops_per_jiffy;
1403 c->x86_cache_size = 0;
1404 c->x86_vendor = X86_VENDOR_UNKNOWN;
1405 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1406 c->x86_vendor_id[0] = '\0'; /* Unset */
1407 c->x86_model_id[0] = '\0'; /* Unset */
1408 c->x86_max_cores = 1;
1409 c->x86_coreid_bits = 0;
1411 #ifdef CONFIG_X86_64
1412 c->x86_clflush_size = 64;
1413 c->x86_phys_bits = 36;
1414 c->x86_virt_bits = 48;
1416 c->cpuid_level = -1; /* CPUID not detected */
1417 c->x86_clflush_size = 32;
1418 c->x86_phys_bits = 32;
1419 c->x86_virt_bits = 32;
1421 c->x86_cache_alignment = c->x86_clflush_size;
1422 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1424 generic_identify(c);
1426 if (this_cpu->c_identify)
1427 this_cpu->c_identify(c);
1429 /* Clear/Set all flags overridden by options, after probe */
1430 apply_forced_caps(c);
1432 #ifdef CONFIG_X86_64
1433 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1437 * Vendor-specific initialization. In this section we
1438 * canonicalize the feature flags, meaning if there are
1439 * features a certain CPU supports which CPUID doesn't
1440 * tell us, CPUID claiming incorrect flags, or other bugs,
1441 * we handle them here.
1443 * At the end of this section, c->x86_capability better
1444 * indicate the features this CPU genuinely supports!
1446 if (this_cpu->c_init)
1447 this_cpu->c_init(c);
1449 /* Disable the PN if appropriate */
1450 squash_the_stupid_serial_number(c);
1452 /* Set up SMEP/SMAP/UMIP */
1458 * The vendor-specific functions might have changed features.
1459 * Now we do "generic changes."
1462 /* Filter out anything that depends on CPUID levels we don't have */
1463 filter_cpuid_features(c, true);
1465 /* If the model name is still unset, do table lookup. */
1466 if (!c->x86_model_id[0]) {
1468 p = table_lookup_model(c);
1470 strcpy(c->x86_model_id, p);
1472 /* Last resort... */
1473 sprintf(c->x86_model_id, "%02x/%02x",
1474 c->x86, c->x86_model);
1477 #ifdef CONFIG_X86_64
1482 x86_init_cache_qos(c);
1486 * Clear/Set all flags overridden by options, need do it
1487 * before following smp all cpus cap AND.
1489 apply_forced_caps(c);
1492 * On SMP, boot_cpu_data holds the common feature set between
1493 * all CPUs; so make sure that we indicate which features are
1494 * common between the CPUs. The first time this routine gets
1495 * executed, c == &boot_cpu_data.
1497 if (c != &boot_cpu_data) {
1498 /* AND the already accumulated flags with these */
1499 for (i = 0; i < NCAPINTS; i++)
1500 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1502 /* OR, i.e. replicate the bug flags */
1503 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1504 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1507 /* Init Machine Check Exception if available. */
1510 select_idle_routine(c);
1513 numa_add_cpu(smp_processor_id());
1518 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1519 * on 32-bit kernels:
1521 #ifdef CONFIG_X86_32
1522 void enable_sep_cpu(void)
1524 struct tss_struct *tss;
1527 if (!boot_cpu_has(X86_FEATURE_SEP))
1531 tss = &per_cpu(cpu_tss_rw, cpu);
1534 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1535 * see the big comment in struct x86_hw_tss's definition.
1538 tss->x86_tss.ss1 = __KERNEL_CS;
1539 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1540 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1541 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1547 void __init identify_boot_cpu(void)
1549 identify_cpu(&boot_cpu_data);
1550 #ifdef CONFIG_X86_32
1554 cpu_detect_tlb(&boot_cpu_data);
1558 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1560 BUG_ON(c == &boot_cpu_data);
1562 #ifdef CONFIG_X86_32
1566 validate_apic_and_package_id(c);
1567 x86_spec_ctrl_setup_ap();
1570 static __init int setup_noclflush(char *arg)
1572 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1573 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1576 __setup("noclflush", setup_noclflush);
1578 void print_cpu_info(struct cpuinfo_x86 *c)
1580 const char *vendor = NULL;
1582 if (c->x86_vendor < X86_VENDOR_NUM) {
1583 vendor = this_cpu->c_vendor;
1585 if (c->cpuid_level >= 0)
1586 vendor = c->x86_vendor_id;
1589 if (vendor && !strstr(c->x86_model_id, vendor))
1590 pr_cont("%s ", vendor);
1592 if (c->x86_model_id[0])
1593 pr_cont("%s", c->x86_model_id);
1595 pr_cont("%d86", c->x86);
1597 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1599 if (c->x86_stepping || c->cpuid_level >= 0)
1600 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1606 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1607 * But we need to keep a dummy __setup around otherwise it would
1608 * show up as an environment variable for init.
1610 static __init int setup_clearcpuid(char *arg)
1614 __setup("clearcpuid=", setup_clearcpuid);
1616 #ifdef CONFIG_X86_64
1617 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
1618 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
1619 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
1622 * The following percpu variables are hot. Align current_task to
1623 * cacheline size such that they fall in the same cacheline.
1625 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1627 EXPORT_PER_CPU_SYMBOL(current_task);
1629 DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
1630 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1632 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1633 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1635 /* May not be marked __init: used by software suspend */
1636 void syscall_init(void)
1638 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1639 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1641 #ifdef CONFIG_IA32_EMULATION
1642 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1644 * This only works on Intel CPUs.
1645 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1646 * This does not cause SYSENTER to jump to the wrong location, because
1647 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1649 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1650 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
1651 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1652 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1654 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1655 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1656 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1657 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1660 /* Flags to clear on syscall */
1661 wrmsrl(MSR_SYSCALL_MASK,
1662 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1663 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1666 DEFINE_PER_CPU(int, debug_stack_usage);
1667 DEFINE_PER_CPU(u32, debug_idt_ctr);
1669 void debug_stack_set_zero(void)
1671 this_cpu_inc(debug_idt_ctr);
1674 NOKPROBE_SYMBOL(debug_stack_set_zero);
1676 void debug_stack_reset(void)
1678 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1680 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1683 NOKPROBE_SYMBOL(debug_stack_reset);
1685 #else /* CONFIG_X86_64 */
1687 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1688 EXPORT_PER_CPU_SYMBOL(current_task);
1689 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1690 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1693 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1694 * the top of the kernel stack. Use an extra percpu variable to track the
1695 * top of the kernel stack directly.
1697 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1698 (unsigned long)&init_thread_union + THREAD_SIZE;
1699 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1701 #ifdef CONFIG_STACKPROTECTOR
1702 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1705 #endif /* CONFIG_X86_64 */
1708 * Clear all 6 debug registers:
1710 static void clear_all_debug_regs(void)
1714 for (i = 0; i < 8; i++) {
1715 /* Ignore db4, db5 */
1716 if ((i == 4) || (i == 5))
1725 * Restore debug regs if using kgdbwait and you have a kernel debugger
1726 * connection established.
1728 static void dbg_restore_debug_regs(void)
1730 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1731 arch_kgdb_ops.correct_hw_break();
1733 #else /* ! CONFIG_KGDB */
1734 #define dbg_restore_debug_regs()
1735 #endif /* ! CONFIG_KGDB */
1737 static void wait_for_master_cpu(int cpu)
1741 * wait for ACK from master CPU before continuing
1742 * with AP initialization
1744 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1745 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1750 #ifdef CONFIG_X86_64
1751 static void setup_getcpu(int cpu)
1753 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
1754 struct desc_struct d = { };
1756 if (boot_cpu_has(X86_FEATURE_RDTSCP))
1757 write_rdtscp_aux(cpudata);
1759 /* Store CPU and node number in limit. */
1761 d.limit1 = cpudata >> 16;
1763 d.type = 5; /* RO data, expand down, accessed */
1764 d.dpl = 3; /* Visible to user code */
1765 d.s = 1; /* Not a system segment */
1766 d.p = 1; /* Present */
1767 d.d = 1; /* 32-bit */
1769 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
1774 * cpu_init() initializes state that is per-CPU. Some data is already
1775 * initialized (naturally) in the bootstrap process, such as the GDT
1776 * and IDT. We reload them nevertheless, this function acts as a
1777 * 'CPU state barrier', nothing should get across.
1779 #ifdef CONFIG_X86_64
1783 int cpu = raw_smp_processor_id();
1784 struct task_struct *me;
1785 struct tss_struct *t;
1788 wait_for_master_cpu(cpu);
1793 t = &per_cpu(cpu_tss_rw, cpu);
1796 if (this_cpu_read(numa_node) == 0 &&
1797 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1798 set_numa_node(early_cpu_to_node(cpu));
1804 pr_debug("Initializing CPU#%d\n", cpu);
1806 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1809 * Initialize the per-CPU GDT with the boot GDT,
1810 * and set up the GDT descriptor:
1813 switch_to_new_gdt(cpu);
1818 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1821 wrmsrl(MSR_FS_BASE, 0);
1822 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1829 * set up and load the per-CPU TSS
1831 if (!t->x86_tss.ist[0]) {
1832 t->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
1833 t->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
1834 t->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
1835 t->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
1838 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1841 * <= is required because the CPU will access up to
1842 * 8 bits beyond the end of the IO permission bitmap.
1844 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1845 t->io_bitmap[i] = ~0UL;
1848 me->active_mm = &init_mm;
1850 initialize_tlbstate_and_flush();
1851 enter_lazy_tlb(&init_mm, me);
1854 * Initialize the TSS. sp0 points to the entry trampoline stack
1855 * regardless of what task is running.
1857 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1859 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1861 load_mm_ldt(&init_mm);
1863 clear_all_debug_regs();
1864 dbg_restore_debug_regs();
1871 load_fixmap_gdt(cpu);
1878 int cpu = smp_processor_id();
1879 struct task_struct *curr = current;
1880 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu);
1882 wait_for_master_cpu(cpu);
1884 show_ucode_info_early();
1886 pr_info("Initializing CPU#%d\n", cpu);
1888 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1889 boot_cpu_has(X86_FEATURE_TSC) ||
1890 boot_cpu_has(X86_FEATURE_DE))
1891 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1894 switch_to_new_gdt(cpu);
1897 * Set up and load the per-CPU TSS and LDT
1900 curr->active_mm = &init_mm;
1902 initialize_tlbstate_and_flush();
1903 enter_lazy_tlb(&init_mm, curr);
1906 * Initialize the TSS. sp0 points to the entry trampoline stack
1907 * regardless of what task is running.
1909 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1911 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1913 load_mm_ldt(&init_mm);
1915 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1917 #ifdef CONFIG_DOUBLEFAULT
1918 /* Set up doublefault TSS pointer in the GDT */
1919 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1922 clear_all_debug_regs();
1923 dbg_restore_debug_regs();
1927 load_fixmap_gdt(cpu);
1932 * The microcode loader calls this upon late microcode load to recheck features,
1933 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1936 void microcode_check(void)
1938 struct cpuinfo_x86 info;
1940 perf_check_microcode();
1942 /* Reload CPUID max function as it might've changed. */
1943 info.cpuid_level = cpuid_eax(0);
1946 * Copy all capability leafs to pick up the synthetic ones so that
1947 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1948 * get overwritten in get_cpu_cap().
1950 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability));
1954 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)))
1957 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1958 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");