1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/delay.h>
9 #include <linux/sched.h>
10 #include <linux/init.h>
11 #include <linux/kprobes.h>
12 #include <linux/kgdb.h>
13 #include <linux/smp.h>
16 #include <asm/stackprotector.h>
17 #include <asm/perf_event.h>
18 #include <asm/mmu_context.h>
19 #include <asm/archrandom.h>
20 #include <asm/hypervisor.h>
21 #include <asm/processor.h>
22 #include <asm/tlbflush.h>
23 #include <asm/debugreg.h>
24 #include <asm/sections.h>
25 #include <asm/vsyscall.h>
26 #include <linux/topology.h>
27 #include <linux/cpumask.h>
28 #include <asm/pgtable.h>
29 #include <linux/atomic.h>
30 #include <asm/proto.h>
31 #include <asm/setup.h>
35 #include <asm/fpu-internal.h>
37 #include <linux/numa.h>
43 #include <asm/microcode.h>
44 #include <asm/microcode_intel.h>
46 #ifdef CONFIG_X86_LOCAL_APIC
47 #include <asm/uv/uv.h>
52 /* all of these masks are initialized in setup_cpu_local_masks() */
53 cpumask_var_t cpu_initialized_mask;
54 cpumask_var_t cpu_callout_mask;
55 cpumask_var_t cpu_callin_mask;
57 /* representing cpus for which sibling maps can be computed */
58 cpumask_var_t cpu_sibling_setup_mask;
60 /* correctly size the local cpu masks */
61 void __init setup_cpu_local_masks(void)
63 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
64 alloc_bootmem_cpumask_var(&cpu_callin_mask);
65 alloc_bootmem_cpumask_var(&cpu_callout_mask);
66 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
69 static void default_init(struct cpuinfo_x86 *c)
72 cpu_detect_cache_sizes(c);
74 /* Not much we can do here... */
75 /* Check if at least it has cpuid */
76 if (c->cpuid_level == -1) {
77 /* No cpuid. It must be an ancient CPU */
79 strcpy(c->x86_model_id, "486");
81 strcpy(c->x86_model_id, "386");
86 static const struct cpu_dev default_cpu = {
87 .c_init = default_init,
88 .c_vendor = "Unknown",
89 .c_x86_vendor = X86_VENDOR_UNKNOWN,
92 static const struct cpu_dev *this_cpu = &default_cpu;
94 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
97 * We need valid kernel segments for data and code in long mode too
98 * IRET will check the segment types kkeil 2000/10/28
99 * Also sysret mandates a special GDT layout
101 * TLS descriptors are currently at a different place compared to i386.
102 * Hopefully nobody expects them at a fixed place (Wine?)
104 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
105 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
106 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
107 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
108 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
109 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
111 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
112 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
113 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
114 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
116 * Segments used for calling PnP BIOS have byte granularity.
117 * They code segments and data segments have fixed 64k limits,
118 * the transfer segment sizes are set at run time.
121 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
123 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
125 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
127 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
129 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
131 * The APM segments have byte granularity and their bases
132 * are set at run time. All have 64k limits.
135 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
137 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
139 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
141 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
142 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
143 GDT_STACK_CANARY_INIT
146 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
148 static int __init x86_xsave_setup(char *s)
152 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
153 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
154 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
155 setup_clear_cpu_cap(X86_FEATURE_AVX);
156 setup_clear_cpu_cap(X86_FEATURE_AVX2);
159 __setup("noxsave", x86_xsave_setup);
161 static int __init x86_xsaveopt_setup(char *s)
163 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
166 __setup("noxsaveopt", x86_xsaveopt_setup);
168 static int __init x86_xsaves_setup(char *s)
170 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
173 __setup("noxsaves", x86_xsaves_setup);
176 static int cachesize_override = -1;
177 static int disable_x86_serial_nr = 1;
179 static int __init cachesize_setup(char *str)
181 get_option(&str, &cachesize_override);
184 __setup("cachesize=", cachesize_setup);
186 static int __init x86_fxsr_setup(char *s)
188 setup_clear_cpu_cap(X86_FEATURE_FXSR);
189 setup_clear_cpu_cap(X86_FEATURE_XMM);
192 __setup("nofxsr", x86_fxsr_setup);
194 static int __init x86_sep_setup(char *s)
196 setup_clear_cpu_cap(X86_FEATURE_SEP);
199 __setup("nosep", x86_sep_setup);
201 /* Standard macro to see if a specific flag is changeable */
202 static inline int flag_is_changeable_p(u32 flag)
207 * Cyrix and IDT cpus allow disabling of CPUID
208 * so the code below may return different results
209 * when it is executed before and after enabling
210 * the CPUID. Add "volatile" to not allow gcc to
211 * optimize the subsequent calls to this function.
213 asm volatile ("pushfl \n\t"
224 : "=&r" (f1), "=&r" (f2)
227 return ((f1^f2) & flag) != 0;
230 /* Probe for the CPUID instruction */
231 int have_cpuid_p(void)
233 return flag_is_changeable_p(X86_EFLAGS_ID);
236 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
238 unsigned long lo, hi;
240 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
243 /* Disable processor serial number: */
245 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
247 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
249 printk(KERN_NOTICE "CPU serial number disabled.\n");
250 clear_cpu_cap(c, X86_FEATURE_PN);
252 /* Disabling the serial number may affect the cpuid level */
253 c->cpuid_level = cpuid_eax(0);
256 static int __init x86_serial_nr_setup(char *s)
258 disable_x86_serial_nr = 0;
261 __setup("serialnumber", x86_serial_nr_setup);
263 static inline int flag_is_changeable_p(u32 flag)
267 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
272 static __init int setup_disable_smep(char *arg)
274 setup_clear_cpu_cap(X86_FEATURE_SMEP);
277 __setup("nosmep", setup_disable_smep);
279 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
281 if (cpu_has(c, X86_FEATURE_SMEP))
282 cr4_set_bits(X86_CR4_SMEP);
285 static __init int setup_disable_smap(char *arg)
287 setup_clear_cpu_cap(X86_FEATURE_SMAP);
290 __setup("nosmap", setup_disable_smap);
292 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
294 unsigned long eflags;
296 /* This should have been cleared long ago */
297 raw_local_save_flags(eflags);
298 BUG_ON(eflags & X86_EFLAGS_AC);
300 if (cpu_has(c, X86_FEATURE_SMAP)) {
301 #ifdef CONFIG_X86_SMAP
302 cr4_set_bits(X86_CR4_SMAP);
304 cr4_clear_bits(X86_CR4_SMAP);
310 * Some CPU features depend on higher CPUID levels, which may not always
311 * be available due to CPUID level capping or broken virtualization
312 * software. Add those features to this table to auto-disable them.
314 struct cpuid_dependent_feature {
319 static const struct cpuid_dependent_feature
320 cpuid_dependent_features[] = {
321 { X86_FEATURE_MWAIT, 0x00000005 },
322 { X86_FEATURE_DCA, 0x00000009 },
323 { X86_FEATURE_XSAVE, 0x0000000d },
327 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
329 const struct cpuid_dependent_feature *df;
331 for (df = cpuid_dependent_features; df->feature; df++) {
333 if (!cpu_has(c, df->feature))
336 * Note: cpuid_level is set to -1 if unavailable, but
337 * extended_extended_level is set to 0 if unavailable
338 * and the legitimate extended levels are all negative
339 * when signed; hence the weird messing around with
342 if (!((s32)df->level < 0 ?
343 (u32)df->level > (u32)c->extended_cpuid_level :
344 (s32)df->level > (s32)c->cpuid_level))
347 clear_cpu_cap(c, df->feature);
352 "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
353 x86_cap_flag(df->feature), df->level);
358 * Naming convention should be: <Name> [(<Codename>)]
359 * This table only is used unless init_<vendor>() below doesn't set it;
360 * in particular, if CPUID levels 0x80000002..4 are supported, this
364 /* Look up CPU names by table lookup. */
365 static const char *table_lookup_model(struct cpuinfo_x86 *c)
368 const struct legacy_cpu_model_info *info;
370 if (c->x86_model >= 16)
371 return NULL; /* Range check */
376 info = this_cpu->legacy_models;
378 while (info->family) {
379 if (info->family == c->x86)
380 return info->model_names[c->x86_model];
384 return NULL; /* Not found */
387 __u32 cpu_caps_cleared[NCAPINTS];
388 __u32 cpu_caps_set[NCAPINTS];
390 void load_percpu_segment(int cpu)
393 loadsegment(fs, __KERNEL_PERCPU);
396 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
398 load_stack_canary_segment();
402 * Current gdt points %fs at the "master" per-cpu area: after this,
403 * it's on the real one.
405 void switch_to_new_gdt(int cpu)
407 struct desc_ptr gdt_descr;
409 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
410 gdt_descr.size = GDT_SIZE - 1;
411 load_gdt(&gdt_descr);
412 /* Reload the per-cpu base */
414 load_percpu_segment(cpu);
417 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
419 static void get_model_name(struct cpuinfo_x86 *c)
424 if (c->extended_cpuid_level < 0x80000004)
427 v = (unsigned int *)c->x86_model_id;
428 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
429 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
430 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
431 c->x86_model_id[48] = 0;
434 * Intel chips right-justify this string for some dumb reason;
435 * undo that brain damage:
437 p = q = &c->x86_model_id[0];
443 while (q <= &c->x86_model_id[48])
444 *q++ = '\0'; /* Zero-pad the rest */
448 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
450 unsigned int n, dummy, ebx, ecx, edx, l2size;
452 n = c->extended_cpuid_level;
454 if (n >= 0x80000005) {
455 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
456 c->x86_cache_size = (ecx>>24) + (edx>>24);
458 /* On K8 L1 TLB is inclusive, so don't count it */
463 if (n < 0x80000006) /* Some chips just has a large L1. */
466 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
470 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
472 /* do processor-specific cache resizing */
473 if (this_cpu->legacy_cache_size)
474 l2size = this_cpu->legacy_cache_size(c, l2size);
476 /* Allow user to override all this if necessary. */
477 if (cachesize_override != -1)
478 l2size = cachesize_override;
481 return; /* Again, no L2 cache is possible */
484 c->x86_cache_size = l2size;
487 u16 __read_mostly tlb_lli_4k[NR_INFO];
488 u16 __read_mostly tlb_lli_2m[NR_INFO];
489 u16 __read_mostly tlb_lli_4m[NR_INFO];
490 u16 __read_mostly tlb_lld_4k[NR_INFO];
491 u16 __read_mostly tlb_lld_2m[NR_INFO];
492 u16 __read_mostly tlb_lld_4m[NR_INFO];
493 u16 __read_mostly tlb_lld_1g[NR_INFO];
495 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
497 if (this_cpu->c_detect_tlb)
498 this_cpu->c_detect_tlb(c);
500 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
501 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
502 tlb_lli_4m[ENTRIES]);
504 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
505 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
506 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
509 void detect_ht(struct cpuinfo_x86 *c)
512 u32 eax, ebx, ecx, edx;
513 int index_msb, core_bits;
516 if (!cpu_has(c, X86_FEATURE_HT))
519 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
522 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
525 cpuid(1, &eax, &ebx, &ecx, &edx);
527 smp_num_siblings = (ebx & 0xff0000) >> 16;
529 if (smp_num_siblings == 1) {
530 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
534 if (smp_num_siblings <= 1)
537 index_msb = get_count_order(smp_num_siblings);
538 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
540 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
542 index_msb = get_count_order(smp_num_siblings);
544 core_bits = get_count_order(c->x86_max_cores);
546 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
547 ((1 << core_bits) - 1);
550 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
551 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
553 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
560 static void get_cpu_vendor(struct cpuinfo_x86 *c)
562 char *v = c->x86_vendor_id;
565 for (i = 0; i < X86_VENDOR_NUM; i++) {
569 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
570 (cpu_devs[i]->c_ident[1] &&
571 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
573 this_cpu = cpu_devs[i];
574 c->x86_vendor = this_cpu->c_x86_vendor;
580 "CPU: vendor_id '%s' unknown, using generic init.\n" \
581 "CPU: Your system may be unstable.\n", v);
583 c->x86_vendor = X86_VENDOR_UNKNOWN;
584 this_cpu = &default_cpu;
587 void cpu_detect(struct cpuinfo_x86 *c)
589 /* Get vendor name */
590 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
591 (unsigned int *)&c->x86_vendor_id[0],
592 (unsigned int *)&c->x86_vendor_id[8],
593 (unsigned int *)&c->x86_vendor_id[4]);
596 /* Intel-defined flags: level 0x00000001 */
597 if (c->cpuid_level >= 0x00000001) {
598 u32 junk, tfms, cap0, misc;
600 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
601 c->x86 = (tfms >> 8) & 0xf;
602 c->x86_model = (tfms >> 4) & 0xf;
603 c->x86_mask = tfms & 0xf;
606 c->x86 += (tfms >> 20) & 0xff;
608 c->x86_model += ((tfms >> 16) & 0xf) << 4;
610 if (cap0 & (1<<19)) {
611 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
612 c->x86_cache_alignment = c->x86_clflush_size;
617 void get_cpu_cap(struct cpuinfo_x86 *c)
622 /* Intel-defined flags: level 0x00000001 */
623 if (c->cpuid_level >= 0x00000001) {
624 u32 capability, excap;
626 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
627 c->x86_capability[0] = capability;
628 c->x86_capability[4] = excap;
631 /* Additional Intel-defined flags: level 0x00000007 */
632 if (c->cpuid_level >= 0x00000007) {
633 u32 eax, ebx, ecx, edx;
635 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
637 c->x86_capability[9] = ebx;
640 /* Extended state features: level 0x0000000d */
641 if (c->cpuid_level >= 0x0000000d) {
642 u32 eax, ebx, ecx, edx;
644 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
646 c->x86_capability[10] = eax;
649 /* AMD-defined flags: level 0x80000001 */
650 xlvl = cpuid_eax(0x80000000);
651 c->extended_cpuid_level = xlvl;
653 if ((xlvl & 0xffff0000) == 0x80000000) {
654 if (xlvl >= 0x80000001) {
655 c->x86_capability[1] = cpuid_edx(0x80000001);
656 c->x86_capability[6] = cpuid_ecx(0x80000001);
660 if (c->extended_cpuid_level >= 0x80000008) {
661 u32 eax = cpuid_eax(0x80000008);
663 c->x86_virt_bits = (eax >> 8) & 0xff;
664 c->x86_phys_bits = eax & 0xff;
667 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
668 c->x86_phys_bits = 36;
671 if (c->extended_cpuid_level >= 0x80000007)
672 c->x86_power = cpuid_edx(0x80000007);
674 init_scattered_cpuid_features(c);
677 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
683 * First of all, decide if this is a 486 or higher
684 * It's a 486 if we can modify the AC flag
686 if (flag_is_changeable_p(X86_EFLAGS_AC))
691 for (i = 0; i < X86_VENDOR_NUM; i++)
692 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
693 c->x86_vendor_id[0] = 0;
694 cpu_devs[i]->c_identify(c);
695 if (c->x86_vendor_id[0]) {
704 * Do minimum CPU detection early.
705 * Fields really needed: vendor, cpuid_level, family, model, mask,
707 * The others are not touched to avoid unwanted side effects.
709 * WARNING: this function is only called on the BP. Don't add code here
710 * that is supposed to run on all CPUs.
712 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
715 c->x86_clflush_size = 64;
716 c->x86_phys_bits = 36;
717 c->x86_virt_bits = 48;
719 c->x86_clflush_size = 32;
720 c->x86_phys_bits = 32;
721 c->x86_virt_bits = 32;
723 c->x86_cache_alignment = c->x86_clflush_size;
725 memset(&c->x86_capability, 0, sizeof c->x86_capability);
726 c->extended_cpuid_level = 0;
729 identify_cpu_without_cpuid(c);
731 /* cyrix could have cpuid enabled via c_identify()*/
740 if (this_cpu->c_early_init)
741 this_cpu->c_early_init(c);
744 filter_cpuid_features(c, false);
746 if (this_cpu->c_bsp_init)
747 this_cpu->c_bsp_init(c);
749 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
752 void __init early_cpu_init(void)
754 const struct cpu_dev *const *cdev;
757 #ifdef CONFIG_PROCESSOR_SELECT
758 printk(KERN_INFO "KERNEL supported cpus:\n");
761 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
762 const struct cpu_dev *cpudev = *cdev;
764 if (count >= X86_VENDOR_NUM)
766 cpu_devs[count] = cpudev;
769 #ifdef CONFIG_PROCESSOR_SELECT
773 for (j = 0; j < 2; j++) {
774 if (!cpudev->c_ident[j])
776 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
782 early_identify_cpu(&boot_cpu_data);
786 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
787 * unfortunately, that's not true in practice because of early VIA
788 * chips and (more importantly) broken virtualizers that are not easy
789 * to detect. In the latter case it doesn't even *fail* reliably, so
790 * probing for it doesn't even work. Disable it completely on 32-bit
791 * unless we can find a reliable way to detect all the broken cases.
792 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
794 static void detect_nopl(struct cpuinfo_x86 *c)
797 clear_cpu_cap(c, X86_FEATURE_NOPL);
799 set_cpu_cap(c, X86_FEATURE_NOPL);
803 static void generic_identify(struct cpuinfo_x86 *c)
805 c->extended_cpuid_level = 0;
808 identify_cpu_without_cpuid(c);
810 /* cyrix could have cpuid enabled via c_identify()*/
820 if (c->cpuid_level >= 0x00000001) {
821 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
823 # ifdef CONFIG_X86_HT
824 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
826 c->apicid = c->initial_apicid;
829 c->phys_proc_id = c->initial_apicid;
832 get_model_name(c); /* Default name */
838 * This does the hard work of actually picking apart the CPU stuff...
840 static void identify_cpu(struct cpuinfo_x86 *c)
844 c->loops_per_jiffy = loops_per_jiffy;
845 c->x86_cache_size = -1;
846 c->x86_vendor = X86_VENDOR_UNKNOWN;
847 c->x86_model = c->x86_mask = 0; /* So far unknown... */
848 c->x86_vendor_id[0] = '\0'; /* Unset */
849 c->x86_model_id[0] = '\0'; /* Unset */
850 c->x86_max_cores = 1;
851 c->x86_coreid_bits = 0;
853 c->x86_clflush_size = 64;
854 c->x86_phys_bits = 36;
855 c->x86_virt_bits = 48;
857 c->cpuid_level = -1; /* CPUID not detected */
858 c->x86_clflush_size = 32;
859 c->x86_phys_bits = 32;
860 c->x86_virt_bits = 32;
862 c->x86_cache_alignment = c->x86_clflush_size;
863 memset(&c->x86_capability, 0, sizeof c->x86_capability);
867 if (this_cpu->c_identify)
868 this_cpu->c_identify(c);
870 /* Clear/Set all flags overriden by options, after probe */
871 for (i = 0; i < NCAPINTS; i++) {
872 c->x86_capability[i] &= ~cpu_caps_cleared[i];
873 c->x86_capability[i] |= cpu_caps_set[i];
877 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
881 * Vendor-specific initialization. In this section we
882 * canonicalize the feature flags, meaning if there are
883 * features a certain CPU supports which CPUID doesn't
884 * tell us, CPUID claiming incorrect flags, or other bugs,
885 * we handle them here.
887 * At the end of this section, c->x86_capability better
888 * indicate the features this CPU genuinely supports!
890 if (this_cpu->c_init)
893 /* Disable the PN if appropriate */
894 squash_the_stupid_serial_number(c);
896 /* Set up SMEP/SMAP */
901 * The vendor-specific functions might have changed features.
902 * Now we do "generic changes."
905 /* Filter out anything that depends on CPUID levels we don't have */
906 filter_cpuid_features(c, true);
908 /* If the model name is still unset, do table lookup. */
909 if (!c->x86_model_id[0]) {
911 p = table_lookup_model(c);
913 strcpy(c->x86_model_id, p);
916 sprintf(c->x86_model_id, "%02x/%02x",
917 c->x86, c->x86_model);
928 * Clear/Set all flags overriden by options, need do it
929 * before following smp all cpus cap AND.
931 for (i = 0; i < NCAPINTS; i++) {
932 c->x86_capability[i] &= ~cpu_caps_cleared[i];
933 c->x86_capability[i] |= cpu_caps_set[i];
937 * On SMP, boot_cpu_data holds the common feature set between
938 * all CPUs; so make sure that we indicate which features are
939 * common between the CPUs. The first time this routine gets
940 * executed, c == &boot_cpu_data.
942 if (c != &boot_cpu_data) {
943 /* AND the already accumulated flags with these */
944 for (i = 0; i < NCAPINTS; i++)
945 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
947 /* OR, i.e. replicate the bug flags */
948 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
949 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
952 /* Init Machine Check Exception if available. */
955 select_idle_routine(c);
958 numa_add_cpu(smp_processor_id());
963 #ifdef CONFIG_IA32_EMULATION
964 /* May not be __init: called during resume */
965 static void syscall32_cpu_init(void)
967 /* Load these always in case some future AMD CPU supports
968 SYSENTER from compat mode too. */
969 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
970 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
971 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target);
973 wrmsrl(MSR_CSTAR, ia32_cstar_target);
975 #endif /* CONFIG_IA32_EMULATION */
976 #endif /* CONFIG_X86_64 */
979 void enable_sep_cpu(void)
982 struct tss_struct *tss = &per_cpu(init_tss, cpu);
984 if (!boot_cpu_has(X86_FEATURE_SEP)) {
989 tss->x86_tss.ss1 = __KERNEL_CS;
990 tss->x86_tss.sp1 = sizeof(struct tss_struct) + (unsigned long) tss;
991 wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0);
992 wrmsr(MSR_IA32_SYSENTER_ESP, tss->x86_tss.sp1, 0);
993 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long) ia32_sysenter_target, 0);
998 void __init identify_boot_cpu(void)
1000 identify_cpu(&boot_cpu_data);
1001 init_amd_e400_c1e_mask();
1002 #ifdef CONFIG_X86_32
1006 cpu_detect_tlb(&boot_cpu_data);
1009 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1011 BUG_ON(c == &boot_cpu_data);
1013 #ifdef CONFIG_X86_32
1024 static const struct msr_range msr_range_array[] = {
1025 { 0x00000000, 0x00000418},
1026 { 0xc0000000, 0xc000040b},
1027 { 0xc0010000, 0xc0010142},
1028 { 0xc0011000, 0xc001103b},
1031 static void __print_cpu_msr(void)
1033 unsigned index_min, index_max;
1038 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1039 index_min = msr_range_array[i].min;
1040 index_max = msr_range_array[i].max;
1042 for (index = index_min; index < index_max; index++) {
1043 if (rdmsrl_safe(index, &val))
1045 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
1050 static int show_msr;
1052 static __init int setup_show_msr(char *arg)
1056 get_option(&arg, &num);
1062 __setup("show_msr=", setup_show_msr);
1064 static __init int setup_noclflush(char *arg)
1066 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1067 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1070 __setup("noclflush", setup_noclflush);
1072 void print_cpu_info(struct cpuinfo_x86 *c)
1074 const char *vendor = NULL;
1076 if (c->x86_vendor < X86_VENDOR_NUM) {
1077 vendor = this_cpu->c_vendor;
1079 if (c->cpuid_level >= 0)
1080 vendor = c->x86_vendor_id;
1083 if (vendor && !strstr(c->x86_model_id, vendor))
1084 printk(KERN_CONT "%s ", vendor);
1086 if (c->x86_model_id[0])
1087 printk(KERN_CONT "%s", strim(c->x86_model_id));
1089 printk(KERN_CONT "%d86", c->x86);
1091 printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model);
1093 if (c->x86_mask || c->cpuid_level >= 0)
1094 printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask);
1096 printk(KERN_CONT ")\n");
1101 void print_cpu_msr(struct cpuinfo_x86 *c)
1103 if (c->cpu_index < show_msr)
1107 static __init int setup_disablecpuid(char *arg)
1111 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1112 setup_clear_cpu_cap(bit);
1118 __setup("clearcpuid=", setup_disablecpuid);
1120 DEFINE_PER_CPU(unsigned long, kernel_stack) =
1121 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1122 EXPORT_PER_CPU_SYMBOL(kernel_stack);
1124 #ifdef CONFIG_X86_64
1125 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1126 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
1127 (unsigned long) debug_idt_table };
1129 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1130 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1133 * The following four percpu variables are hot. Align current_task to
1134 * cacheline size such that all four fall in the same cacheline.
1136 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1138 EXPORT_PER_CPU_SYMBOL(current_task);
1140 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1141 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1143 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1145 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1146 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1148 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1151 * Special IST stacks which the CPU switches to when it calls
1152 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1153 * limit), all of them are 4K, except the debug stack which
1156 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1157 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1158 [DEBUG_STACK - 1] = DEBUG_STKSZ
1161 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1162 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1164 /* May not be marked __init: used by software suspend */
1165 void syscall_init(void)
1168 * LSTAR and STAR live in a bit strange symbiosis.
1169 * They both write to the same internal register. STAR allows to
1170 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1172 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1173 wrmsrl(MSR_LSTAR, system_call);
1174 wrmsrl(MSR_CSTAR, ignore_sysret);
1176 #ifdef CONFIG_IA32_EMULATION
1177 syscall32_cpu_init();
1180 /* Flags to clear on syscall */
1181 wrmsrl(MSR_SYSCALL_MASK,
1182 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1183 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1187 * Copies of the original ist values from the tss are only accessed during
1188 * debugging, no special alignment required.
1190 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1192 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1193 DEFINE_PER_CPU(int, debug_stack_usage);
1195 int is_debug_stack(unsigned long addr)
1197 return __this_cpu_read(debug_stack_usage) ||
1198 (addr <= __this_cpu_read(debug_stack_addr) &&
1199 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1201 NOKPROBE_SYMBOL(is_debug_stack);
1203 DEFINE_PER_CPU(u32, debug_idt_ctr);
1205 void debug_stack_set_zero(void)
1207 this_cpu_inc(debug_idt_ctr);
1210 NOKPROBE_SYMBOL(debug_stack_set_zero);
1212 void debug_stack_reset(void)
1214 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1216 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1219 NOKPROBE_SYMBOL(debug_stack_reset);
1221 #else /* CONFIG_X86_64 */
1223 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1224 EXPORT_PER_CPU_SYMBOL(current_task);
1225 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1226 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1227 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1229 #ifdef CONFIG_CC_STACKPROTECTOR
1230 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1233 #endif /* CONFIG_X86_64 */
1236 * Clear all 6 debug registers:
1238 static void clear_all_debug_regs(void)
1242 for (i = 0; i < 8; i++) {
1243 /* Ignore db4, db5 */
1244 if ((i == 4) || (i == 5))
1253 * Restore debug regs if using kgdbwait and you have a kernel debugger
1254 * connection established.
1256 static void dbg_restore_debug_regs(void)
1258 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1259 arch_kgdb_ops.correct_hw_break();
1261 #else /* ! CONFIG_KGDB */
1262 #define dbg_restore_debug_regs()
1263 #endif /* ! CONFIG_KGDB */
1265 static void wait_for_master_cpu(int cpu)
1269 * wait for ACK from master CPU before continuing
1270 * with AP initialization
1272 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1273 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1279 * cpu_init() initializes state that is per-CPU. Some data is already
1280 * initialized (naturally) in the bootstrap process, such as the GDT
1281 * and IDT. We reload them nevertheless, this function acts as a
1282 * 'CPU state barrier', nothing should get across.
1283 * A lot of state is already set up in PDA init for 64 bit
1285 #ifdef CONFIG_X86_64
1289 struct orig_ist *oist;
1290 struct task_struct *me;
1291 struct tss_struct *t;
1293 int cpu = stack_smp_processor_id();
1296 wait_for_master_cpu(cpu);
1299 * Initialize the CR4 shadow before doing anything that could
1305 * Load microcode on this cpu if a valid microcode is available.
1306 * This is early microcode loading procedure.
1310 t = &per_cpu(init_tss, cpu);
1311 oist = &per_cpu(orig_ist, cpu);
1314 if (this_cpu_read(numa_node) == 0 &&
1315 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1316 set_numa_node(early_cpu_to_node(cpu));
1321 pr_debug("Initializing CPU#%d\n", cpu);
1323 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1326 * Initialize the per-CPU GDT with the boot GDT,
1327 * and set up the GDT descriptor:
1330 switch_to_new_gdt(cpu);
1335 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1338 wrmsrl(MSR_FS_BASE, 0);
1339 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1346 * set up and load the per-CPU TSS
1348 if (!oist->ist[0]) {
1349 char *estacks = per_cpu(exception_stacks, cpu);
1351 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1352 estacks += exception_stack_sizes[v];
1353 oist->ist[v] = t->x86_tss.ist[v] =
1354 (unsigned long)estacks;
1355 if (v == DEBUG_STACK-1)
1356 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1360 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1363 * <= is required because the CPU will access up to
1364 * 8 bits beyond the end of the IO permission bitmap.
1366 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1367 t->io_bitmap[i] = ~0UL;
1369 atomic_inc(&init_mm.mm_count);
1370 me->active_mm = &init_mm;
1372 enter_lazy_tlb(&init_mm, me);
1374 load_sp0(t, ¤t->thread);
1375 set_tss_desc(cpu, t);
1377 load_LDT(&init_mm.context);
1379 clear_all_debug_regs();
1380 dbg_restore_debug_regs();
1392 int cpu = smp_processor_id();
1393 struct task_struct *curr = current;
1394 struct tss_struct *t = &per_cpu(init_tss, cpu);
1395 struct thread_struct *thread = &curr->thread;
1397 wait_for_master_cpu(cpu);
1399 show_ucode_info_early();
1401 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1403 if (cpu_feature_enabled(X86_FEATURE_VME) || cpu_has_tsc || cpu_has_de)
1404 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1407 switch_to_new_gdt(cpu);
1410 * Set up and load the per-CPU TSS and LDT
1412 atomic_inc(&init_mm.mm_count);
1413 curr->active_mm = &init_mm;
1415 enter_lazy_tlb(&init_mm, curr);
1417 load_sp0(t, thread);
1418 set_tss_desc(cpu, t);
1420 load_LDT(&init_mm.context);
1422 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1424 #ifdef CONFIG_DOUBLEFAULT
1425 /* Set up doublefault TSS pointer in the GDT */
1426 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1429 clear_all_debug_regs();
1430 dbg_restore_debug_regs();
1436 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
1437 void warn_pre_alternatives(void)
1439 WARN(1, "You're using static_cpu_has before alternatives have run!\n");
1441 EXPORT_SYMBOL_GPL(warn_pre_alternatives);
1444 inline bool __static_cpu_has_safe(u16 bit)
1446 return boot_cpu_has(bit);
1448 EXPORT_SYMBOL_GPL(__static_cpu_has_safe);