1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/delay.h>
9 #include <linux/sched.h>
10 #include <linux/init.h>
11 #include <linux/kgdb.h>
12 #include <linux/smp.h>
15 #include <asm/stackprotector.h>
16 #include <asm/perf_event.h>
17 #include <asm/mmu_context.h>
18 #include <asm/archrandom.h>
19 #include <asm/hypervisor.h>
20 #include <asm/processor.h>
21 #include <asm/sections.h>
22 #include <linux/topology.h>
23 #include <linux/cpumask.h>
24 #include <asm/pgtable.h>
25 #include <linux/atomic.h>
26 #include <asm/proto.h>
27 #include <asm/setup.h>
31 #include <asm/fpu-internal.h>
33 #include <linux/numa.h>
40 #ifdef CONFIG_X86_LOCAL_APIC
41 #include <asm/uv/uv.h>
46 /* all of these masks are initialized in setup_cpu_local_masks() */
47 cpumask_var_t cpu_initialized_mask;
48 cpumask_var_t cpu_callout_mask;
49 cpumask_var_t cpu_callin_mask;
51 /* representing cpus for which sibling maps can be computed */
52 cpumask_var_t cpu_sibling_setup_mask;
54 /* correctly size the local cpu masks */
55 void __init setup_cpu_local_masks(void)
57 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
58 alloc_bootmem_cpumask_var(&cpu_callin_mask);
59 alloc_bootmem_cpumask_var(&cpu_callout_mask);
60 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
63 static void __cpuinit default_init(struct cpuinfo_x86 *c)
66 cpu_detect_cache_sizes(c);
68 /* Not much we can do here... */
69 /* Check if at least it has cpuid */
70 if (c->cpuid_level == -1) {
71 /* No cpuid. It must be an ancient CPU */
73 strcpy(c->x86_model_id, "486");
75 strcpy(c->x86_model_id, "386");
80 static const struct cpu_dev __cpuinitconst default_cpu = {
81 .c_init = default_init,
82 .c_vendor = "Unknown",
83 .c_x86_vendor = X86_VENDOR_UNKNOWN,
86 static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
88 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
91 * We need valid kernel segments for data and code in long mode too
92 * IRET will check the segment types kkeil 2000/10/28
93 * Also sysret mandates a special GDT layout
95 * TLS descriptors are currently at a different place compared to i386.
96 * Hopefully nobody expects them at a fixed place (Wine?)
98 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
99 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
100 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
101 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
102 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
103 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
105 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
106 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
107 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
108 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
110 * Segments used for calling PnP BIOS have byte granularity.
111 * They code segments and data segments have fixed 64k limits,
112 * the transfer segment sizes are set at run time.
115 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
117 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
119 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
121 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
123 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
125 * The APM segments have byte granularity and their bases
126 * are set at run time. All have 64k limits.
129 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
131 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
133 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
135 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
136 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
137 GDT_STACK_CANARY_INIT
140 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
142 static int __init x86_xsave_setup(char *s)
144 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
145 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
148 __setup("noxsave", x86_xsave_setup);
150 static int __init x86_xsaveopt_setup(char *s)
152 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
155 __setup("noxsaveopt", x86_xsaveopt_setup);
158 static int cachesize_override __cpuinitdata = -1;
159 static int disable_x86_serial_nr __cpuinitdata = 1;
161 static int __init cachesize_setup(char *str)
163 get_option(&str, &cachesize_override);
166 __setup("cachesize=", cachesize_setup);
168 static int __init x86_fxsr_setup(char *s)
170 setup_clear_cpu_cap(X86_FEATURE_FXSR);
171 setup_clear_cpu_cap(X86_FEATURE_XMM);
174 __setup("nofxsr", x86_fxsr_setup);
176 static int __init x86_sep_setup(char *s)
178 setup_clear_cpu_cap(X86_FEATURE_SEP);
181 __setup("nosep", x86_sep_setup);
183 /* Standard macro to see if a specific flag is changeable */
184 static inline int flag_is_changeable_p(u32 flag)
189 * Cyrix and IDT cpus allow disabling of CPUID
190 * so the code below may return different results
191 * when it is executed before and after enabling
192 * the CPUID. Add "volatile" to not allow gcc to
193 * optimize the subsequent calls to this function.
195 asm volatile ("pushfl \n\t"
206 : "=&r" (f1), "=&r" (f2)
209 return ((f1^f2) & flag) != 0;
212 /* Probe for the CPUID instruction */
213 static int __cpuinit have_cpuid_p(void)
215 return flag_is_changeable_p(X86_EFLAGS_ID);
218 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
220 unsigned long lo, hi;
222 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
225 /* Disable processor serial number: */
227 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
229 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
231 printk(KERN_NOTICE "CPU serial number disabled.\n");
232 clear_cpu_cap(c, X86_FEATURE_PN);
234 /* Disabling the serial number may affect the cpuid level */
235 c->cpuid_level = cpuid_eax(0);
238 static int __init x86_serial_nr_setup(char *s)
240 disable_x86_serial_nr = 0;
243 __setup("serialnumber", x86_serial_nr_setup);
245 static inline int flag_is_changeable_p(u32 flag)
249 /* Probe for the CPUID instruction */
250 static inline int have_cpuid_p(void)
254 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
259 static int disable_smep __cpuinitdata;
260 static __init int setup_disable_smep(char *arg)
265 __setup("nosmep", setup_disable_smep);
267 static __cpuinit void setup_smep(struct cpuinfo_x86 *c)
269 if (cpu_has(c, X86_FEATURE_SMEP)) {
270 if (unlikely(disable_smep)) {
271 setup_clear_cpu_cap(X86_FEATURE_SMEP);
272 clear_in_cr4(X86_CR4_SMEP);
274 set_in_cr4(X86_CR4_SMEP);
279 * Some CPU features depend on higher CPUID levels, which may not always
280 * be available due to CPUID level capping or broken virtualization
281 * software. Add those features to this table to auto-disable them.
283 struct cpuid_dependent_feature {
288 static const struct cpuid_dependent_feature __cpuinitconst
289 cpuid_dependent_features[] = {
290 { X86_FEATURE_MWAIT, 0x00000005 },
291 { X86_FEATURE_DCA, 0x00000009 },
292 { X86_FEATURE_XSAVE, 0x0000000d },
296 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
298 const struct cpuid_dependent_feature *df;
300 for (df = cpuid_dependent_features; df->feature; df++) {
302 if (!cpu_has(c, df->feature))
305 * Note: cpuid_level is set to -1 if unavailable, but
306 * extended_extended_level is set to 0 if unavailable
307 * and the legitimate extended levels are all negative
308 * when signed; hence the weird messing around with
311 if (!((s32)df->level < 0 ?
312 (u32)df->level > (u32)c->extended_cpuid_level :
313 (s32)df->level > (s32)c->cpuid_level))
316 clear_cpu_cap(c, df->feature);
321 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
322 x86_cap_flags[df->feature], df->level);
327 * Naming convention should be: <Name> [(<Codename>)]
328 * This table only is used unless init_<vendor>() below doesn't set it;
329 * in particular, if CPUID levels 0x80000002..4 are supported, this
333 /* Look up CPU names by table lookup. */
334 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c)
336 const struct cpu_model_info *info;
338 if (c->x86_model >= 16)
339 return NULL; /* Range check */
344 info = this_cpu->c_models;
346 while (info && info->family) {
347 if (info->family == c->x86)
348 return info->model_names[c->x86_model];
351 return NULL; /* Not found */
354 __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata;
355 __u32 cpu_caps_set[NCAPINTS] __cpuinitdata;
357 void load_percpu_segment(int cpu)
360 loadsegment(fs, __KERNEL_PERCPU);
363 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
365 load_stack_canary_segment();
369 * Current gdt points %fs at the "master" per-cpu area: after this,
370 * it's on the real one.
372 void switch_to_new_gdt(int cpu)
374 struct desc_ptr gdt_descr;
376 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
377 gdt_descr.size = GDT_SIZE - 1;
378 load_gdt(&gdt_descr);
379 /* Reload the per-cpu base */
381 load_percpu_segment(cpu);
384 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {};
386 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
391 if (c->extended_cpuid_level < 0x80000004)
394 v = (unsigned int *)c->x86_model_id;
395 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
396 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
397 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
398 c->x86_model_id[48] = 0;
401 * Intel chips right-justify this string for some dumb reason;
402 * undo that brain damage:
404 p = q = &c->x86_model_id[0];
410 while (q <= &c->x86_model_id[48])
411 *q++ = '\0'; /* Zero-pad the rest */
415 void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
417 unsigned int n, dummy, ebx, ecx, edx, l2size;
419 n = c->extended_cpuid_level;
421 if (n >= 0x80000005) {
422 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
423 c->x86_cache_size = (ecx>>24) + (edx>>24);
425 /* On K8 L1 TLB is inclusive, so don't count it */
430 if (n < 0x80000006) /* Some chips just has a large L1. */
433 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
437 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
439 /* do processor-specific cache resizing */
440 if (this_cpu->c_size_cache)
441 l2size = this_cpu->c_size_cache(c, l2size);
443 /* Allow user to override all this if necessary. */
444 if (cachesize_override != -1)
445 l2size = cachesize_override;
448 return; /* Again, no L2 cache is possible */
451 c->x86_cache_size = l2size;
454 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
457 u32 eax, ebx, ecx, edx;
458 int index_msb, core_bits;
461 if (!cpu_has(c, X86_FEATURE_HT))
464 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
467 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
470 cpuid(1, &eax, &ebx, &ecx, &edx);
472 smp_num_siblings = (ebx & 0xff0000) >> 16;
474 if (smp_num_siblings == 1) {
475 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
479 if (smp_num_siblings <= 1)
482 index_msb = get_count_order(smp_num_siblings);
483 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
485 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
487 index_msb = get_count_order(smp_num_siblings);
489 core_bits = get_count_order(c->x86_max_cores);
491 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
492 ((1 << core_bits) - 1);
495 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
496 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
498 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
505 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
507 char *v = c->x86_vendor_id;
510 for (i = 0; i < X86_VENDOR_NUM; i++) {
514 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
515 (cpu_devs[i]->c_ident[1] &&
516 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
518 this_cpu = cpu_devs[i];
519 c->x86_vendor = this_cpu->c_x86_vendor;
525 "CPU: vendor_id '%s' unknown, using generic init.\n" \
526 "CPU: Your system may be unstable.\n", v);
528 c->x86_vendor = X86_VENDOR_UNKNOWN;
529 this_cpu = &default_cpu;
532 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
534 /* Get vendor name */
535 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
536 (unsigned int *)&c->x86_vendor_id[0],
537 (unsigned int *)&c->x86_vendor_id[8],
538 (unsigned int *)&c->x86_vendor_id[4]);
541 /* Intel-defined flags: level 0x00000001 */
542 if (c->cpuid_level >= 0x00000001) {
543 u32 junk, tfms, cap0, misc;
545 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
546 c->x86 = (tfms >> 8) & 0xf;
547 c->x86_model = (tfms >> 4) & 0xf;
548 c->x86_mask = tfms & 0xf;
551 c->x86 += (tfms >> 20) & 0xff;
553 c->x86_model += ((tfms >> 16) & 0xf) << 4;
555 if (cap0 & (1<<19)) {
556 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
557 c->x86_cache_alignment = c->x86_clflush_size;
562 void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
567 /* Intel-defined flags: level 0x00000001 */
568 if (c->cpuid_level >= 0x00000001) {
569 u32 capability, excap;
571 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
572 c->x86_capability[0] = capability;
573 c->x86_capability[4] = excap;
576 /* Additional Intel-defined flags: level 0x00000007 */
577 if (c->cpuid_level >= 0x00000007) {
578 u32 eax, ebx, ecx, edx;
580 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
582 c->x86_capability[9] = ebx;
585 /* AMD-defined flags: level 0x80000001 */
586 xlvl = cpuid_eax(0x80000000);
587 c->extended_cpuid_level = xlvl;
589 if ((xlvl & 0xffff0000) == 0x80000000) {
590 if (xlvl >= 0x80000001) {
591 c->x86_capability[1] = cpuid_edx(0x80000001);
592 c->x86_capability[6] = cpuid_ecx(0x80000001);
596 if (c->extended_cpuid_level >= 0x80000008) {
597 u32 eax = cpuid_eax(0x80000008);
599 c->x86_virt_bits = (eax >> 8) & 0xff;
600 c->x86_phys_bits = eax & 0xff;
603 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
604 c->x86_phys_bits = 36;
607 if (c->extended_cpuid_level >= 0x80000007)
608 c->x86_power = cpuid_edx(0x80000007);
610 init_scattered_cpuid_features(c);
613 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
619 * First of all, decide if this is a 486 or higher
620 * It's a 486 if we can modify the AC flag
622 if (flag_is_changeable_p(X86_EFLAGS_AC))
627 for (i = 0; i < X86_VENDOR_NUM; i++)
628 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
629 c->x86_vendor_id[0] = 0;
630 cpu_devs[i]->c_identify(c);
631 if (c->x86_vendor_id[0]) {
640 * Do minimum CPU detection early.
641 * Fields really needed: vendor, cpuid_level, family, model, mask,
643 * The others are not touched to avoid unwanted side effects.
645 * WARNING: this function is only called on the BP. Don't add code here
646 * that is supposed to run on all CPUs.
648 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
651 c->x86_clflush_size = 64;
652 c->x86_phys_bits = 36;
653 c->x86_virt_bits = 48;
655 c->x86_clflush_size = 32;
656 c->x86_phys_bits = 32;
657 c->x86_virt_bits = 32;
659 c->x86_cache_alignment = c->x86_clflush_size;
661 memset(&c->x86_capability, 0, sizeof c->x86_capability);
662 c->extended_cpuid_level = 0;
665 identify_cpu_without_cpuid(c);
667 /* cyrix could have cpuid enabled via c_identify()*/
677 if (this_cpu->c_early_init)
678 this_cpu->c_early_init(c);
681 filter_cpuid_features(c, false);
685 if (this_cpu->c_bsp_init)
686 this_cpu->c_bsp_init(c);
689 void __init early_cpu_init(void)
691 const struct cpu_dev *const *cdev;
694 #ifdef CONFIG_PROCESSOR_SELECT
695 printk(KERN_INFO "KERNEL supported cpus:\n");
698 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
699 const struct cpu_dev *cpudev = *cdev;
701 if (count >= X86_VENDOR_NUM)
703 cpu_devs[count] = cpudev;
706 #ifdef CONFIG_PROCESSOR_SELECT
710 for (j = 0; j < 2; j++) {
711 if (!cpudev->c_ident[j])
713 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
719 early_identify_cpu(&boot_cpu_data);
723 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
724 * unfortunately, that's not true in practice because of early VIA
725 * chips and (more importantly) broken virtualizers that are not easy
726 * to detect. In the latter case it doesn't even *fail* reliably, so
727 * probing for it doesn't even work. Disable it completely on 32-bit
728 * unless we can find a reliable way to detect all the broken cases.
729 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
731 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
734 clear_cpu_cap(c, X86_FEATURE_NOPL);
736 set_cpu_cap(c, X86_FEATURE_NOPL);
740 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
742 c->extended_cpuid_level = 0;
745 identify_cpu_without_cpuid(c);
747 /* cyrix could have cpuid enabled via c_identify()*/
757 if (c->cpuid_level >= 0x00000001) {
758 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
760 # ifdef CONFIG_X86_HT
761 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
763 c->apicid = c->initial_apicid;
766 c->phys_proc_id = c->initial_apicid;
771 get_model_name(c); /* Default name */
777 * This does the hard work of actually picking apart the CPU stuff...
779 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
783 c->loops_per_jiffy = loops_per_jiffy;
784 c->x86_cache_size = -1;
785 c->x86_vendor = X86_VENDOR_UNKNOWN;
786 c->x86_model = c->x86_mask = 0; /* So far unknown... */
787 c->x86_vendor_id[0] = '\0'; /* Unset */
788 c->x86_model_id[0] = '\0'; /* Unset */
789 c->x86_max_cores = 1;
790 c->x86_coreid_bits = 0;
792 c->x86_clflush_size = 64;
793 c->x86_phys_bits = 36;
794 c->x86_virt_bits = 48;
796 c->cpuid_level = -1; /* CPUID not detected */
797 c->x86_clflush_size = 32;
798 c->x86_phys_bits = 32;
799 c->x86_virt_bits = 32;
801 c->x86_cache_alignment = c->x86_clflush_size;
802 memset(&c->x86_capability, 0, sizeof c->x86_capability);
806 if (this_cpu->c_identify)
807 this_cpu->c_identify(c);
809 /* Clear/Set all flags overriden by options, after probe */
810 for (i = 0; i < NCAPINTS; i++) {
811 c->x86_capability[i] &= ~cpu_caps_cleared[i];
812 c->x86_capability[i] |= cpu_caps_set[i];
816 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
820 * Vendor-specific initialization. In this section we
821 * canonicalize the feature flags, meaning if there are
822 * features a certain CPU supports which CPUID doesn't
823 * tell us, CPUID claiming incorrect flags, or other bugs,
824 * we handle them here.
826 * At the end of this section, c->x86_capability better
827 * indicate the features this CPU genuinely supports!
829 if (this_cpu->c_init)
832 /* Disable the PN if appropriate */
833 squash_the_stupid_serial_number(c);
836 * The vendor-specific functions might have changed features.
837 * Now we do "generic changes."
840 /* Filter out anything that depends on CPUID levels we don't have */
841 filter_cpuid_features(c, true);
843 /* If the model name is still unset, do table lookup. */
844 if (!c->x86_model_id[0]) {
846 p = table_lookup_model(c);
848 strcpy(c->x86_model_id, p);
851 sprintf(c->x86_model_id, "%02x/%02x",
852 c->x86, c->x86_model);
863 * Clear/Set all flags overriden by options, need do it
864 * before following smp all cpus cap AND.
866 for (i = 0; i < NCAPINTS; i++) {
867 c->x86_capability[i] &= ~cpu_caps_cleared[i];
868 c->x86_capability[i] |= cpu_caps_set[i];
872 * On SMP, boot_cpu_data holds the common feature set between
873 * all CPUs; so make sure that we indicate which features are
874 * common between the CPUs. The first time this routine gets
875 * executed, c == &boot_cpu_data.
877 if (c != &boot_cpu_data) {
878 /* AND the already accumulated flags with these */
879 for (i = 0; i < NCAPINTS; i++)
880 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
883 /* Init Machine Check Exception if available. */
886 select_idle_routine(c);
889 numa_add_cpu(smp_processor_id());
894 static void vgetcpu_set_mode(void)
896 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
897 vgetcpu_mode = VGETCPU_RDTSCP;
899 vgetcpu_mode = VGETCPU_LSL;
903 void __init identify_boot_cpu(void)
905 identify_cpu(&boot_cpu_data);
906 init_amd_e400_c1e_mask();
915 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
917 BUG_ON(c == &boot_cpu_data);
930 static const struct msr_range msr_range_array[] __cpuinitconst = {
931 { 0x00000000, 0x00000418},
932 { 0xc0000000, 0xc000040b},
933 { 0xc0010000, 0xc0010142},
934 { 0xc0011000, 0xc001103b},
937 static void __cpuinit print_cpu_msr(void)
939 unsigned index_min, index_max;
944 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
945 index_min = msr_range_array[i].min;
946 index_max = msr_range_array[i].max;
948 for (index = index_min; index < index_max; index++) {
949 if (rdmsrl_amd_safe(index, &val))
951 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
956 static int show_msr __cpuinitdata;
958 static __init int setup_show_msr(char *arg)
962 get_option(&arg, &num);
968 __setup("show_msr=", setup_show_msr);
970 static __init int setup_noclflush(char *arg)
972 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
975 __setup("noclflush", setup_noclflush);
977 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
979 const char *vendor = NULL;
981 if (c->x86_vendor < X86_VENDOR_NUM) {
982 vendor = this_cpu->c_vendor;
984 if (c->cpuid_level >= 0)
985 vendor = c->x86_vendor_id;
988 if (vendor && !strstr(c->x86_model_id, vendor))
989 printk(KERN_CONT "%s ", vendor);
991 if (c->x86_model_id[0])
992 printk(KERN_CONT "%s", c->x86_model_id);
994 printk(KERN_CONT "%d86", c->x86);
996 if (c->x86_mask || c->cpuid_level >= 0)
997 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
999 printk(KERN_CONT "\n");
1002 if (c->cpu_index < show_msr)
1010 static __init int setup_disablecpuid(char *arg)
1014 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1015 setup_clear_cpu_cap(bit);
1021 __setup("clearcpuid=", setup_disablecpuid);
1023 #ifdef CONFIG_X86_64
1024 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1025 struct desc_ptr nmi_idt_descr = { NR_VECTORS * 16 - 1,
1026 (unsigned long) nmi_idt_table };
1028 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1029 irq_stack_union) __aligned(PAGE_SIZE);
1032 * The following four percpu variables are hot. Align current_task to
1033 * cacheline size such that all four fall in the same cacheline.
1035 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1037 EXPORT_PER_CPU_SYMBOL(current_task);
1039 DEFINE_PER_CPU(unsigned long, kernel_stack) =
1040 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1041 EXPORT_PER_CPU_SYMBOL(kernel_stack);
1043 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1044 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1046 DEFINE_PER_CPU(unsigned int, irq_count) = -1;
1048 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1051 * Special IST stacks which the CPU switches to when it calls
1052 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1053 * limit), all of them are 4K, except the debug stack which
1056 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1057 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1058 [DEBUG_STACK - 1] = DEBUG_STKSZ
1061 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1062 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1064 /* May not be marked __init: used by software suspend */
1065 void syscall_init(void)
1068 * LSTAR and STAR live in a bit strange symbiosis.
1069 * They both write to the same internal register. STAR allows to
1070 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1072 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1073 wrmsrl(MSR_LSTAR, system_call);
1074 wrmsrl(MSR_CSTAR, ignore_sysret);
1076 #ifdef CONFIG_IA32_EMULATION
1077 syscall32_cpu_init();
1080 /* Flags to clear on syscall */
1081 wrmsrl(MSR_SYSCALL_MASK,
1082 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
1085 unsigned long kernel_eflags;
1088 * Copies of the original ist values from the tss are only accessed during
1089 * debugging, no special alignment required.
1091 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1093 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1094 DEFINE_PER_CPU(int, debug_stack_usage);
1096 int is_debug_stack(unsigned long addr)
1098 return __get_cpu_var(debug_stack_usage) ||
1099 (addr <= __get_cpu_var(debug_stack_addr) &&
1100 addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ));
1103 void debug_stack_set_zero(void)
1105 load_idt((const struct desc_ptr *)&nmi_idt_descr);
1108 void debug_stack_reset(void)
1110 load_idt((const struct desc_ptr *)&idt_descr);
1113 #else /* CONFIG_X86_64 */
1115 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1116 EXPORT_PER_CPU_SYMBOL(current_task);
1117 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1119 #ifdef CONFIG_CC_STACKPROTECTOR
1120 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1123 /* Make sure %fs and %gs are initialized properly in idle threads */
1124 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
1126 memset(regs, 0, sizeof(struct pt_regs));
1127 regs->fs = __KERNEL_PERCPU;
1128 regs->gs = __KERNEL_STACK_CANARY;
1132 #endif /* CONFIG_X86_64 */
1135 * Clear all 6 debug registers:
1137 static void clear_all_debug_regs(void)
1141 for (i = 0; i < 8; i++) {
1142 /* Ignore db4, db5 */
1143 if ((i == 4) || (i == 5))
1152 * Restore debug regs if using kgdbwait and you have a kernel debugger
1153 * connection established.
1155 static void dbg_restore_debug_regs(void)
1157 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1158 arch_kgdb_ops.correct_hw_break();
1160 #else /* ! CONFIG_KGDB */
1161 #define dbg_restore_debug_regs()
1162 #endif /* ! CONFIG_KGDB */
1165 * Prints an error where the NUMA and configured core-number mismatch and the
1166 * platform didn't override this to fix it up
1168 void __cpuinit x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node)
1170 pr_err("NUMA core number %d differs from configured core number %d\n", node, c->phys_proc_id);
1174 * cpu_init() initializes state that is per-CPU. Some data is already
1175 * initialized (naturally) in the bootstrap process, such as the GDT
1176 * and IDT. We reload them nevertheless, this function acts as a
1177 * 'CPU state barrier', nothing should get across.
1178 * A lot of state is already set up in PDA init for 64 bit
1180 #ifdef CONFIG_X86_64
1182 void __cpuinit cpu_init(void)
1184 struct orig_ist *oist;
1185 struct task_struct *me;
1186 struct tss_struct *t;
1191 cpu = stack_smp_processor_id();
1192 t = &per_cpu(init_tss, cpu);
1193 oist = &per_cpu(orig_ist, cpu);
1196 if (cpu != 0 && percpu_read(numa_node) == 0 &&
1197 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1198 set_numa_node(early_cpu_to_node(cpu));
1203 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1204 panic("CPU#%d already initialized!\n", cpu);
1206 pr_debug("Initializing CPU#%d\n", cpu);
1208 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1211 * Initialize the per-CPU GDT with the boot GDT,
1212 * and set up the GDT descriptor:
1215 switch_to_new_gdt(cpu);
1218 load_idt((const struct desc_ptr *)&idt_descr);
1220 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1223 wrmsrl(MSR_FS_BASE, 0);
1224 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1232 * set up and load the per-CPU TSS
1234 if (!oist->ist[0]) {
1235 char *estacks = per_cpu(exception_stacks, cpu);
1237 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1238 estacks += exception_stack_sizes[v];
1239 oist->ist[v] = t->x86_tss.ist[v] =
1240 (unsigned long)estacks;
1241 if (v == DEBUG_STACK-1)
1242 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1246 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1249 * <= is required because the CPU will access up to
1250 * 8 bits beyond the end of the IO permission bitmap.
1252 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1253 t->io_bitmap[i] = ~0UL;
1255 atomic_inc(&init_mm.mm_count);
1256 me->active_mm = &init_mm;
1258 enter_lazy_tlb(&init_mm, me);
1260 load_sp0(t, ¤t->thread);
1261 set_tss_desc(cpu, t);
1263 load_LDT(&init_mm.context);
1265 clear_all_debug_regs();
1266 dbg_restore_debug_regs();
1271 raw_local_save_flags(kernel_eflags);
1279 void __cpuinit cpu_init(void)
1281 int cpu = smp_processor_id();
1282 struct task_struct *curr = current;
1283 struct tss_struct *t = &per_cpu(init_tss, cpu);
1284 struct thread_struct *thread = &curr->thread;
1286 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1287 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1292 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1294 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1295 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1297 load_idt(&idt_descr);
1298 switch_to_new_gdt(cpu);
1301 * Set up and load the per-CPU TSS and LDT
1303 atomic_inc(&init_mm.mm_count);
1304 curr->active_mm = &init_mm;
1306 enter_lazy_tlb(&init_mm, curr);
1308 load_sp0(t, thread);
1309 set_tss_desc(cpu, t);
1311 load_LDT(&init_mm.context);
1313 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1315 #ifdef CONFIG_DOUBLEFAULT
1316 /* Set up doublefault TSS pointer in the GDT */
1317 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1320 clear_all_debug_regs();
1321 dbg_restore_debug_regs();