1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/export.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched/mm.h>
11 #include <linux/sched/clock.h>
12 #include <linux/sched/task.h>
13 #include <linux/init.h>
14 #include <linux/kprobes.h>
15 #include <linux/kgdb.h>
16 #include <linux/smp.h>
18 #include <linux/syscore_ops.h>
20 #include <asm/stackprotector.h>
21 #include <asm/perf_event.h>
22 #include <asm/mmu_context.h>
23 #include <asm/archrandom.h>
24 #include <asm/hypervisor.h>
25 #include <asm/processor.h>
26 #include <asm/tlbflush.h>
27 #include <asm/debugreg.h>
28 #include <asm/sections.h>
29 #include <asm/vsyscall.h>
30 #include <linux/topology.h>
31 #include <linux/cpumask.h>
32 #include <asm/pgtable.h>
33 #include <linux/atomic.h>
34 #include <asm/proto.h>
35 #include <asm/setup.h>
38 #include <asm/fpu/internal.h>
40 #include <asm/hwcap2.h>
41 #include <linux/numa.h>
48 #include <asm/microcode.h>
49 #include <asm/microcode_intel.h>
51 #ifdef CONFIG_X86_LOCAL_APIC
52 #include <asm/uv/uv.h>
57 u32 elf_hwcap2 __read_mostly;
59 /* all of these masks are initialized in setup_cpu_local_masks() */
60 cpumask_var_t cpu_initialized_mask;
61 cpumask_var_t cpu_callout_mask;
62 cpumask_var_t cpu_callin_mask;
64 /* representing cpus for which sibling maps can be computed */
65 cpumask_var_t cpu_sibling_setup_mask;
67 /* correctly size the local cpu masks */
68 void __init setup_cpu_local_masks(void)
70 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
71 alloc_bootmem_cpumask_var(&cpu_callin_mask);
72 alloc_bootmem_cpumask_var(&cpu_callout_mask);
73 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
76 static void default_init(struct cpuinfo_x86 *c)
79 cpu_detect_cache_sizes(c);
81 /* Not much we can do here... */
82 /* Check if at least it has cpuid */
83 if (c->cpuid_level == -1) {
84 /* No cpuid. It must be an ancient CPU */
86 strcpy(c->x86_model_id, "486");
88 strcpy(c->x86_model_id, "386");
93 static const struct cpu_dev default_cpu = {
94 .c_init = default_init,
95 .c_vendor = "Unknown",
96 .c_x86_vendor = X86_VENDOR_UNKNOWN,
99 static const struct cpu_dev *this_cpu = &default_cpu;
101 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
104 * We need valid kernel segments for data and code in long mode too
105 * IRET will check the segment types kkeil 2000/10/28
106 * Also sysret mandates a special GDT layout
108 * TLS descriptors are currently at a different place compared to i386.
109 * Hopefully nobody expects them at a fixed place (Wine?)
111 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
114 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
116 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
118 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
119 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
120 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
121 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
123 * Segments used for calling PnP BIOS have byte granularity.
124 * They code segments and data segments have fixed 64k limits,
125 * the transfer segment sizes are set at run time.
128 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
130 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
132 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
134 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
136 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
138 * The APM segments have byte granularity and their bases
139 * are set at run time. All have 64k limits.
142 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
144 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
146 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
148 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
149 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
150 GDT_STACK_CANARY_INIT
153 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
155 static int __init x86_mpx_setup(char *s)
157 /* require an exact match without trailing characters */
161 /* do not emit a message if the feature is not present */
162 if (!boot_cpu_has(X86_FEATURE_MPX))
165 setup_clear_cpu_cap(X86_FEATURE_MPX);
166 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
169 __setup("nompx", x86_mpx_setup);
172 static int __init x86_nopcid_setup(char *s)
174 /* nopcid doesn't accept parameters */
178 /* do not emit a message if the feature is not present */
179 if (!boot_cpu_has(X86_FEATURE_PCID))
182 setup_clear_cpu_cap(X86_FEATURE_PCID);
183 pr_info("nopcid: PCID feature disabled\n");
186 early_param("nopcid", x86_nopcid_setup);
189 static int __init x86_noinvpcid_setup(char *s)
191 /* noinvpcid doesn't accept parameters */
195 /* do not emit a message if the feature is not present */
196 if (!boot_cpu_has(X86_FEATURE_INVPCID))
199 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
200 pr_info("noinvpcid: INVPCID feature disabled\n");
203 early_param("noinvpcid", x86_noinvpcid_setup);
206 static int cachesize_override = -1;
207 static int disable_x86_serial_nr = 1;
209 static int __init cachesize_setup(char *str)
211 get_option(&str, &cachesize_override);
214 __setup("cachesize=", cachesize_setup);
216 static int __init x86_sep_setup(char *s)
218 setup_clear_cpu_cap(X86_FEATURE_SEP);
221 __setup("nosep", x86_sep_setup);
223 /* Standard macro to see if a specific flag is changeable */
224 static inline int flag_is_changeable_p(u32 flag)
229 * Cyrix and IDT cpus allow disabling of CPUID
230 * so the code below may return different results
231 * when it is executed before and after enabling
232 * the CPUID. Add "volatile" to not allow gcc to
233 * optimize the subsequent calls to this function.
235 asm volatile ("pushfl \n\t"
246 : "=&r" (f1), "=&r" (f2)
249 return ((f1^f2) & flag) != 0;
252 /* Probe for the CPUID instruction */
253 int have_cpuid_p(void)
255 return flag_is_changeable_p(X86_EFLAGS_ID);
258 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
260 unsigned long lo, hi;
262 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
265 /* Disable processor serial number: */
267 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
269 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
271 pr_notice("CPU serial number disabled.\n");
272 clear_cpu_cap(c, X86_FEATURE_PN);
274 /* Disabling the serial number may affect the cpuid level */
275 c->cpuid_level = cpuid_eax(0);
278 static int __init x86_serial_nr_setup(char *s)
280 disable_x86_serial_nr = 0;
283 __setup("serialnumber", x86_serial_nr_setup);
285 static inline int flag_is_changeable_p(u32 flag)
289 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
294 static __init int setup_disable_smep(char *arg)
296 setup_clear_cpu_cap(X86_FEATURE_SMEP);
297 /* Check for things that depend on SMEP being enabled: */
298 check_mpx_erratum(&boot_cpu_data);
301 __setup("nosmep", setup_disable_smep);
303 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
305 if (cpu_has(c, X86_FEATURE_SMEP))
306 cr4_set_bits(X86_CR4_SMEP);
309 static __init int setup_disable_smap(char *arg)
311 setup_clear_cpu_cap(X86_FEATURE_SMAP);
314 __setup("nosmap", setup_disable_smap);
316 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
318 unsigned long eflags = native_save_fl();
320 /* This should have been cleared long ago */
321 BUG_ON(eflags & X86_EFLAGS_AC);
323 if (cpu_has(c, X86_FEATURE_SMAP)) {
324 #ifdef CONFIG_X86_SMAP
325 cr4_set_bits(X86_CR4_SMAP);
327 cr4_clear_bits(X86_CR4_SMAP);
332 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
334 /* Check the boot processor, plus build option for UMIP. */
335 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
338 /* Check the current processor's cpuid bits. */
339 if (!cpu_has(c, X86_FEATURE_UMIP))
342 cr4_set_bits(X86_CR4_UMIP);
344 pr_info("x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature\n");
350 * Make sure UMIP is disabled in case it was enabled in a
351 * previous boot (e.g., via kexec).
353 cr4_clear_bits(X86_CR4_UMIP);
357 * Protection Keys are not available in 32-bit mode.
359 static bool pku_disabled;
361 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
363 /* check the boot processor, plus compile options for PKU: */
364 if (!cpu_feature_enabled(X86_FEATURE_PKU))
366 /* checks the actual processor's cpuid bits: */
367 if (!cpu_has(c, X86_FEATURE_PKU))
372 cr4_set_bits(X86_CR4_PKE);
374 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
375 * cpuid bit to be set. We need to ensure that we
376 * update that bit in this CPU's "cpu_info".
381 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
382 static __init int setup_disable_pku(char *arg)
385 * Do not clear the X86_FEATURE_PKU bit. All of the
386 * runtime checks are against OSPKE so clearing the
389 * This way, we will see "pku" in cpuinfo, but not
390 * "ospke", which is exactly what we want. It shows
391 * that the CPU has PKU, but the OS has not enabled it.
392 * This happens to be exactly how a system would look
393 * if we disabled the config option.
395 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
399 __setup("nopku", setup_disable_pku);
400 #endif /* CONFIG_X86_64 */
403 * Some CPU features depend on higher CPUID levels, which may not always
404 * be available due to CPUID level capping or broken virtualization
405 * software. Add those features to this table to auto-disable them.
407 struct cpuid_dependent_feature {
412 static const struct cpuid_dependent_feature
413 cpuid_dependent_features[] = {
414 { X86_FEATURE_MWAIT, 0x00000005 },
415 { X86_FEATURE_DCA, 0x00000009 },
416 { X86_FEATURE_XSAVE, 0x0000000d },
420 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
422 const struct cpuid_dependent_feature *df;
424 for (df = cpuid_dependent_features; df->feature; df++) {
426 if (!cpu_has(c, df->feature))
429 * Note: cpuid_level is set to -1 if unavailable, but
430 * extended_extended_level is set to 0 if unavailable
431 * and the legitimate extended levels are all negative
432 * when signed; hence the weird messing around with
435 if (!((s32)df->level < 0 ?
436 (u32)df->level > (u32)c->extended_cpuid_level :
437 (s32)df->level > (s32)c->cpuid_level))
440 clear_cpu_cap(c, df->feature);
444 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
445 x86_cap_flag(df->feature), df->level);
450 * Naming convention should be: <Name> [(<Codename>)]
451 * This table only is used unless init_<vendor>() below doesn't set it;
452 * in particular, if CPUID levels 0x80000002..4 are supported, this
456 /* Look up CPU names by table lookup. */
457 static const char *table_lookup_model(struct cpuinfo_x86 *c)
460 const struct legacy_cpu_model_info *info;
462 if (c->x86_model >= 16)
463 return NULL; /* Range check */
468 info = this_cpu->legacy_models;
470 while (info->family) {
471 if (info->family == c->x86)
472 return info->model_names[c->x86_model];
476 return NULL; /* Not found */
479 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
480 __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
482 void load_percpu_segment(int cpu)
485 loadsegment(fs, __KERNEL_PERCPU);
487 __loadsegment_simple(gs, 0);
488 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
490 load_stack_canary_segment();
494 /* The 32-bit entry code needs to find cpu_entry_area. */
495 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
500 * Special IST stacks which the CPU switches to when it calls
501 * an IST-marked descriptor entry. Up to 7 stacks (hardware
502 * limit), all of them are 4K, except the debug stack which
505 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
506 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
507 [DEBUG_STACK - 1] = DEBUG_STKSZ
510 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
511 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
514 static DEFINE_PER_CPU_PAGE_ALIGNED(struct SYSENTER_stack_page,
515 SYSENTER_stack_storage);
518 set_percpu_fixmap_pages(int idx, void *ptr, int pages, pgprot_t prot)
520 for ( ; pages; pages--, idx--, ptr += PAGE_SIZE)
521 __set_fixmap(idx, per_cpu_ptr_to_phys(ptr), prot);
524 /* Setup the fixmap mappings only once per-processor */
525 static void __init setup_cpu_entry_area(int cpu)
528 extern char _entry_trampoline[];
530 /* On 64-bit systems, we use a read-only fixmap GDT and TSS. */
531 pgprot_t gdt_prot = PAGE_KERNEL_RO;
532 pgprot_t tss_prot = PAGE_KERNEL_RO;
535 * On native 32-bit systems, the GDT cannot be read-only because
536 * our double fault handler uses a task gate, and entering through
537 * a task gate needs to change an available TSS to busy. If the
538 * GDT is read-only, that will triple fault. The TSS cannot be
539 * read-only because the CPU writes to it on task switches.
541 * On Xen PV, the GDT must be read-only because the hypervisor
544 pgprot_t gdt_prot = boot_cpu_has(X86_FEATURE_XENPV) ?
545 PAGE_KERNEL_RO : PAGE_KERNEL;
546 pgprot_t tss_prot = PAGE_KERNEL;
549 __set_fixmap(get_cpu_entry_area_index(cpu, gdt), get_cpu_gdt_paddr(cpu), gdt_prot);
550 set_percpu_fixmap_pages(get_cpu_entry_area_index(cpu, SYSENTER_stack_page),
551 per_cpu_ptr(&SYSENTER_stack_storage, cpu), 1,
555 * The Intel SDM says (Volume 3, 7.2.1):
557 * Avoid placing a page boundary in the part of the TSS that the
558 * processor reads during a task switch (the first 104 bytes). The
559 * processor may not correctly perform address translations if a
560 * boundary occurs in this area. During a task switch, the processor
561 * reads and writes into the first 104 bytes of each TSS (using
562 * contiguous physical addresses beginning with the physical address
563 * of the first byte of the TSS). So, after TSS access begins, if
564 * part of the 104 bytes is not physically contiguous, the processor
565 * will access incorrect information without generating a page-fault
568 * There are also a lot of errata involving the TSS spanning a page
569 * boundary. Assert that we're not doing that.
571 BUILD_BUG_ON((offsetof(struct tss_struct, x86_tss) ^
572 offsetofend(struct tss_struct, x86_tss)) & PAGE_MASK);
573 BUILD_BUG_ON(sizeof(struct tss_struct) % PAGE_SIZE != 0);
574 set_percpu_fixmap_pages(get_cpu_entry_area_index(cpu, tss),
575 &per_cpu(cpu_tss_rw, cpu),
576 sizeof(struct tss_struct) / PAGE_SIZE,
580 per_cpu(cpu_entry_area, cpu) = get_cpu_entry_area(cpu);
584 BUILD_BUG_ON(sizeof(exception_stacks) % PAGE_SIZE != 0);
585 BUILD_BUG_ON(sizeof(exception_stacks) !=
586 sizeof(((struct cpu_entry_area *)0)->exception_stacks));
587 set_percpu_fixmap_pages(get_cpu_entry_area_index(cpu, exception_stacks),
588 &per_cpu(exception_stacks, cpu),
589 sizeof(exception_stacks) / PAGE_SIZE,
592 __set_fixmap(get_cpu_entry_area_index(cpu, entry_trampoline),
593 __pa_symbol(_entry_trampoline), PAGE_KERNEL_RX);
597 void __init setup_cpu_entry_areas(void)
601 for_each_possible_cpu(cpu)
602 setup_cpu_entry_area(cpu);
605 /* Load the original GDT from the per-cpu structure */
606 void load_direct_gdt(int cpu)
608 struct desc_ptr gdt_descr;
610 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
611 gdt_descr.size = GDT_SIZE - 1;
612 load_gdt(&gdt_descr);
614 EXPORT_SYMBOL_GPL(load_direct_gdt);
616 /* Load a fixmap remapping of the per-cpu GDT */
617 void load_fixmap_gdt(int cpu)
619 struct desc_ptr gdt_descr;
621 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
622 gdt_descr.size = GDT_SIZE - 1;
623 load_gdt(&gdt_descr);
625 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
628 * Current gdt points %fs at the "master" per-cpu area: after this,
629 * it's on the real one.
631 void switch_to_new_gdt(int cpu)
633 /* Load the original GDT */
634 load_direct_gdt(cpu);
635 /* Reload the per-cpu base */
636 load_percpu_segment(cpu);
639 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
641 static void get_model_name(struct cpuinfo_x86 *c)
646 if (c->extended_cpuid_level < 0x80000004)
649 v = (unsigned int *)c->x86_model_id;
650 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
651 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
652 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
653 c->x86_model_id[48] = 0;
655 /* Trim whitespace */
656 p = q = s = &c->x86_model_id[0];
662 /* Note the last non-whitespace index */
672 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
674 unsigned int n, dummy, ebx, ecx, edx, l2size;
676 n = c->extended_cpuid_level;
678 if (n >= 0x80000005) {
679 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
680 c->x86_cache_size = (ecx>>24) + (edx>>24);
682 /* On K8 L1 TLB is inclusive, so don't count it */
687 if (n < 0x80000006) /* Some chips just has a large L1. */
690 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
694 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
696 /* do processor-specific cache resizing */
697 if (this_cpu->legacy_cache_size)
698 l2size = this_cpu->legacy_cache_size(c, l2size);
700 /* Allow user to override all this if necessary. */
701 if (cachesize_override != -1)
702 l2size = cachesize_override;
705 return; /* Again, no L2 cache is possible */
708 c->x86_cache_size = l2size;
711 u16 __read_mostly tlb_lli_4k[NR_INFO];
712 u16 __read_mostly tlb_lli_2m[NR_INFO];
713 u16 __read_mostly tlb_lli_4m[NR_INFO];
714 u16 __read_mostly tlb_lld_4k[NR_INFO];
715 u16 __read_mostly tlb_lld_2m[NR_INFO];
716 u16 __read_mostly tlb_lld_4m[NR_INFO];
717 u16 __read_mostly tlb_lld_1g[NR_INFO];
719 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
721 if (this_cpu->c_detect_tlb)
722 this_cpu->c_detect_tlb(c);
724 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
725 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
726 tlb_lli_4m[ENTRIES]);
728 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
729 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
730 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
733 void detect_ht(struct cpuinfo_x86 *c)
736 u32 eax, ebx, ecx, edx;
737 int index_msb, core_bits;
740 if (!cpu_has(c, X86_FEATURE_HT))
743 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
746 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
749 cpuid(1, &eax, &ebx, &ecx, &edx);
751 smp_num_siblings = (ebx & 0xff0000) >> 16;
753 if (smp_num_siblings == 1) {
754 pr_info_once("CPU0: Hyper-Threading is disabled\n");
758 if (smp_num_siblings <= 1)
761 index_msb = get_count_order(smp_num_siblings);
762 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
764 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
766 index_msb = get_count_order(smp_num_siblings);
768 core_bits = get_count_order(c->x86_max_cores);
770 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
771 ((1 << core_bits) - 1);
774 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
775 pr_info("CPU: Physical Processor ID: %d\n",
777 pr_info("CPU: Processor Core ID: %d\n",
784 static void get_cpu_vendor(struct cpuinfo_x86 *c)
786 char *v = c->x86_vendor_id;
789 for (i = 0; i < X86_VENDOR_NUM; i++) {
793 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
794 (cpu_devs[i]->c_ident[1] &&
795 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
797 this_cpu = cpu_devs[i];
798 c->x86_vendor = this_cpu->c_x86_vendor;
803 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
804 "CPU: Your system may be unstable.\n", v);
806 c->x86_vendor = X86_VENDOR_UNKNOWN;
807 this_cpu = &default_cpu;
810 void cpu_detect(struct cpuinfo_x86 *c)
812 /* Get vendor name */
813 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
814 (unsigned int *)&c->x86_vendor_id[0],
815 (unsigned int *)&c->x86_vendor_id[8],
816 (unsigned int *)&c->x86_vendor_id[4]);
819 /* Intel-defined flags: level 0x00000001 */
820 if (c->cpuid_level >= 0x00000001) {
821 u32 junk, tfms, cap0, misc;
823 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
824 c->x86 = x86_family(tfms);
825 c->x86_model = x86_model(tfms);
826 c->x86_mask = x86_stepping(tfms);
828 if (cap0 & (1<<19)) {
829 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
830 c->x86_cache_alignment = c->x86_clflush_size;
835 static void apply_forced_caps(struct cpuinfo_x86 *c)
839 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
840 c->x86_capability[i] &= ~cpu_caps_cleared[i];
841 c->x86_capability[i] |= cpu_caps_set[i];
845 void get_cpu_cap(struct cpuinfo_x86 *c)
847 u32 eax, ebx, ecx, edx;
849 /* Intel-defined flags: level 0x00000001 */
850 if (c->cpuid_level >= 0x00000001) {
851 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
853 c->x86_capability[CPUID_1_ECX] = ecx;
854 c->x86_capability[CPUID_1_EDX] = edx;
857 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
858 if (c->cpuid_level >= 0x00000006)
859 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
861 /* Additional Intel-defined flags: level 0x00000007 */
862 if (c->cpuid_level >= 0x00000007) {
863 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
864 c->x86_capability[CPUID_7_0_EBX] = ebx;
865 c->x86_capability[CPUID_7_ECX] = ecx;
868 /* Extended state features: level 0x0000000d */
869 if (c->cpuid_level >= 0x0000000d) {
870 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
872 c->x86_capability[CPUID_D_1_EAX] = eax;
875 /* Additional Intel-defined flags: level 0x0000000F */
876 if (c->cpuid_level >= 0x0000000F) {
878 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
879 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
880 c->x86_capability[CPUID_F_0_EDX] = edx;
882 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
883 /* will be overridden if occupancy monitoring exists */
884 c->x86_cache_max_rmid = ebx;
886 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
887 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
888 c->x86_capability[CPUID_F_1_EDX] = edx;
890 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
891 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
892 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
893 c->x86_cache_max_rmid = ecx;
894 c->x86_cache_occ_scale = ebx;
897 c->x86_cache_max_rmid = -1;
898 c->x86_cache_occ_scale = -1;
902 /* AMD-defined flags: level 0x80000001 */
903 eax = cpuid_eax(0x80000000);
904 c->extended_cpuid_level = eax;
906 if ((eax & 0xffff0000) == 0x80000000) {
907 if (eax >= 0x80000001) {
908 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
910 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
911 c->x86_capability[CPUID_8000_0001_EDX] = edx;
915 if (c->extended_cpuid_level >= 0x80000007) {
916 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
918 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
922 if (c->extended_cpuid_level >= 0x80000008) {
923 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
925 c->x86_virt_bits = (eax >> 8) & 0xff;
926 c->x86_phys_bits = eax & 0xff;
927 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
930 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
931 c->x86_phys_bits = 36;
934 if (c->extended_cpuid_level >= 0x8000000a)
935 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
937 init_scattered_cpuid_features(c);
940 * Clear/Set all flags overridden by options, after probe.
941 * This needs to happen each time we re-probe, which may happen
942 * several times during CPU initialization.
944 apply_forced_caps(c);
947 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
953 * First of all, decide if this is a 486 or higher
954 * It's a 486 if we can modify the AC flag
956 if (flag_is_changeable_p(X86_EFLAGS_AC))
961 for (i = 0; i < X86_VENDOR_NUM; i++)
962 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
963 c->x86_vendor_id[0] = 0;
964 cpu_devs[i]->c_identify(c);
965 if (c->x86_vendor_id[0]) {
974 * Do minimum CPU detection early.
975 * Fields really needed: vendor, cpuid_level, family, model, mask,
977 * The others are not touched to avoid unwanted side effects.
979 * WARNING: this function is only called on the boot CPU. Don't add code
980 * here that is supposed to run on all CPUs.
982 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
985 c->x86_clflush_size = 64;
986 c->x86_phys_bits = 36;
987 c->x86_virt_bits = 48;
989 c->x86_clflush_size = 32;
990 c->x86_phys_bits = 32;
991 c->x86_virt_bits = 32;
993 c->x86_cache_alignment = c->x86_clflush_size;
995 memset(&c->x86_capability, 0, sizeof c->x86_capability);
996 c->extended_cpuid_level = 0;
998 /* cyrix could have cpuid enabled via c_identify()*/
999 if (have_cpuid_p()) {
1003 setup_force_cpu_cap(X86_FEATURE_CPUID);
1005 if (this_cpu->c_early_init)
1006 this_cpu->c_early_init(c);
1009 filter_cpuid_features(c, false);
1011 if (this_cpu->c_bsp_init)
1012 this_cpu->c_bsp_init(c);
1014 identify_cpu_without_cpuid(c);
1015 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1018 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1019 fpu__init_system(c);
1021 #ifdef CONFIG_X86_32
1023 * Regardless of whether PCID is enumerated, the SDM says
1024 * that it can't be enabled in 32-bit mode.
1026 setup_clear_cpu_cap(X86_FEATURE_PCID);
1030 void __init early_cpu_init(void)
1032 const struct cpu_dev *const *cdev;
1035 #ifdef CONFIG_PROCESSOR_SELECT
1036 pr_info("KERNEL supported cpus:\n");
1039 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1040 const struct cpu_dev *cpudev = *cdev;
1042 if (count >= X86_VENDOR_NUM)
1044 cpu_devs[count] = cpudev;
1047 #ifdef CONFIG_PROCESSOR_SELECT
1051 for (j = 0; j < 2; j++) {
1052 if (!cpudev->c_ident[j])
1054 pr_info(" %s %s\n", cpudev->c_vendor,
1055 cpudev->c_ident[j]);
1060 early_identify_cpu(&boot_cpu_data);
1064 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1065 * unfortunately, that's not true in practice because of early VIA
1066 * chips and (more importantly) broken virtualizers that are not easy
1067 * to detect. In the latter case it doesn't even *fail* reliably, so
1068 * probing for it doesn't even work. Disable it completely on 32-bit
1069 * unless we can find a reliable way to detect all the broken cases.
1070 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1072 static void detect_nopl(struct cpuinfo_x86 *c)
1074 #ifdef CONFIG_X86_32
1075 clear_cpu_cap(c, X86_FEATURE_NOPL);
1077 set_cpu_cap(c, X86_FEATURE_NOPL);
1081 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
1083 #ifdef CONFIG_X86_64
1085 * Empirically, writing zero to a segment selector on AMD does
1086 * not clear the base, whereas writing zero to a segment
1087 * selector on Intel does clear the base. Intel's behavior
1088 * allows slightly faster context switches in the common case
1089 * where GS is unused by the prev and next threads.
1091 * Since neither vendor documents this anywhere that I can see,
1092 * detect it directly instead of hardcoding the choice by
1095 * I've designated AMD's behavior as the "bug" because it's
1096 * counterintuitive and less friendly.
1099 unsigned long old_base, tmp;
1100 rdmsrl(MSR_FS_BASE, old_base);
1101 wrmsrl(MSR_FS_BASE, 1);
1103 rdmsrl(MSR_FS_BASE, tmp);
1105 set_cpu_bug(c, X86_BUG_NULL_SEG);
1106 wrmsrl(MSR_FS_BASE, old_base);
1110 static void generic_identify(struct cpuinfo_x86 *c)
1112 c->extended_cpuid_level = 0;
1114 if (!have_cpuid_p())
1115 identify_cpu_without_cpuid(c);
1117 /* cyrix could have cpuid enabled via c_identify()*/
1118 if (!have_cpuid_p())
1127 if (c->cpuid_level >= 0x00000001) {
1128 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1129 #ifdef CONFIG_X86_32
1131 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1133 c->apicid = c->initial_apicid;
1136 c->phys_proc_id = c->initial_apicid;
1139 get_model_name(c); /* Default name */
1143 detect_null_seg_behavior(c);
1146 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1147 * systems that run Linux at CPL > 0 may or may not have the
1148 * issue, but, even if they have the issue, there's absolutely
1149 * nothing we can do about it because we can't use the real IRET
1152 * NB: For the time being, only 32-bit kernels support
1153 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1154 * whether to apply espfix using paravirt hooks. If any
1155 * non-paravirt system ever shows up that does *not* have the
1156 * ESPFIX issue, we can change this.
1158 #ifdef CONFIG_X86_32
1159 # ifdef CONFIG_PARAVIRT
1161 extern void native_iret(void);
1162 if (pv_cpu_ops.iret == native_iret)
1163 set_cpu_bug(c, X86_BUG_ESPFIX);
1166 set_cpu_bug(c, X86_BUG_ESPFIX);
1171 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
1174 * The heavy lifting of max_rmid and cache_occ_scale are handled
1175 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1176 * in case CQM bits really aren't there in this CPU.
1178 if (c != &boot_cpu_data) {
1179 boot_cpu_data.x86_cache_max_rmid =
1180 min(boot_cpu_data.x86_cache_max_rmid,
1181 c->x86_cache_max_rmid);
1186 * Validate that ACPI/mptables have the same information about the
1187 * effective APIC id and update the package map.
1189 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1192 unsigned int apicid, cpu = smp_processor_id();
1194 apicid = apic->cpu_present_to_apicid(cpu);
1196 if (apicid != c->apicid) {
1197 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1198 cpu, apicid, c->initial_apicid);
1200 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1202 c->logical_proc_id = 0;
1207 * This does the hard work of actually picking apart the CPU stuff...
1209 static void identify_cpu(struct cpuinfo_x86 *c)
1213 c->loops_per_jiffy = loops_per_jiffy;
1214 c->x86_cache_size = -1;
1215 c->x86_vendor = X86_VENDOR_UNKNOWN;
1216 c->x86_model = c->x86_mask = 0; /* So far unknown... */
1217 c->x86_vendor_id[0] = '\0'; /* Unset */
1218 c->x86_model_id[0] = '\0'; /* Unset */
1219 c->x86_max_cores = 1;
1220 c->x86_coreid_bits = 0;
1222 #ifdef CONFIG_X86_64
1223 c->x86_clflush_size = 64;
1224 c->x86_phys_bits = 36;
1225 c->x86_virt_bits = 48;
1227 c->cpuid_level = -1; /* CPUID not detected */
1228 c->x86_clflush_size = 32;
1229 c->x86_phys_bits = 32;
1230 c->x86_virt_bits = 32;
1232 c->x86_cache_alignment = c->x86_clflush_size;
1233 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1235 generic_identify(c);
1237 if (this_cpu->c_identify)
1238 this_cpu->c_identify(c);
1240 /* Clear/Set all flags overridden by options, after probe */
1241 apply_forced_caps(c);
1243 #ifdef CONFIG_X86_64
1244 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1248 * Vendor-specific initialization. In this section we
1249 * canonicalize the feature flags, meaning if there are
1250 * features a certain CPU supports which CPUID doesn't
1251 * tell us, CPUID claiming incorrect flags, or other bugs,
1252 * we handle them here.
1254 * At the end of this section, c->x86_capability better
1255 * indicate the features this CPU genuinely supports!
1257 if (this_cpu->c_init)
1258 this_cpu->c_init(c);
1260 /* Disable the PN if appropriate */
1261 squash_the_stupid_serial_number(c);
1263 /* Set up SMEP/SMAP/UMIP */
1269 * The vendor-specific functions might have changed features.
1270 * Now we do "generic changes."
1273 /* Filter out anything that depends on CPUID levels we don't have */
1274 filter_cpuid_features(c, true);
1276 /* If the model name is still unset, do table lookup. */
1277 if (!c->x86_model_id[0]) {
1279 p = table_lookup_model(c);
1281 strcpy(c->x86_model_id, p);
1283 /* Last resort... */
1284 sprintf(c->x86_model_id, "%02x/%02x",
1285 c->x86, c->x86_model);
1288 #ifdef CONFIG_X86_64
1293 x86_init_cache_qos(c);
1297 * Clear/Set all flags overridden by options, need do it
1298 * before following smp all cpus cap AND.
1300 apply_forced_caps(c);
1303 * On SMP, boot_cpu_data holds the common feature set between
1304 * all CPUs; so make sure that we indicate which features are
1305 * common between the CPUs. The first time this routine gets
1306 * executed, c == &boot_cpu_data.
1308 if (c != &boot_cpu_data) {
1309 /* AND the already accumulated flags with these */
1310 for (i = 0; i < NCAPINTS; i++)
1311 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1313 /* OR, i.e. replicate the bug flags */
1314 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1315 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1318 /* Init Machine Check Exception if available. */
1321 select_idle_routine(c);
1324 numa_add_cpu(smp_processor_id());
1329 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1330 * on 32-bit kernels:
1332 #ifdef CONFIG_X86_32
1333 void enable_sep_cpu(void)
1335 struct tss_struct *tss;
1338 if (!boot_cpu_has(X86_FEATURE_SEP))
1342 tss = &per_cpu(cpu_tss_rw, cpu);
1345 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1346 * see the big comment in struct x86_hw_tss's definition.
1349 tss->x86_tss.ss1 = __KERNEL_CS;
1350 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1351 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_SYSENTER_stack(cpu) + 1), 0);
1352 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1358 void __init identify_boot_cpu(void)
1360 identify_cpu(&boot_cpu_data);
1361 #ifdef CONFIG_X86_32
1365 cpu_detect_tlb(&boot_cpu_data);
1368 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1370 BUG_ON(c == &boot_cpu_data);
1372 #ifdef CONFIG_X86_32
1376 validate_apic_and_package_id(c);
1379 static __init int setup_noclflush(char *arg)
1381 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1382 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1385 __setup("noclflush", setup_noclflush);
1387 void print_cpu_info(struct cpuinfo_x86 *c)
1389 const char *vendor = NULL;
1391 if (c->x86_vendor < X86_VENDOR_NUM) {
1392 vendor = this_cpu->c_vendor;
1394 if (c->cpuid_level >= 0)
1395 vendor = c->x86_vendor_id;
1398 if (vendor && !strstr(c->x86_model_id, vendor))
1399 pr_cont("%s ", vendor);
1401 if (c->x86_model_id[0])
1402 pr_cont("%s", c->x86_model_id);
1404 pr_cont("%d86", c->x86);
1406 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1408 if (c->x86_mask || c->cpuid_level >= 0)
1409 pr_cont(", stepping: 0x%x)\n", c->x86_mask);
1415 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1416 * But we need to keep a dummy __setup around otherwise it would
1417 * show up as an environment variable for init.
1419 static __init int setup_clearcpuid(char *arg)
1423 __setup("clearcpuid=", setup_clearcpuid);
1425 #ifdef CONFIG_X86_64
1426 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1427 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1430 * The following percpu variables are hot. Align current_task to
1431 * cacheline size such that they fall in the same cacheline.
1433 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1435 EXPORT_PER_CPU_SYMBOL(current_task);
1437 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1438 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE;
1440 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1442 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1443 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1445 /* May not be marked __init: used by software suspend */
1446 void syscall_init(void)
1448 extern char _entry_trampoline[];
1449 extern char entry_SYSCALL_64_trampoline[];
1451 int cpu = smp_processor_id();
1452 unsigned long SYSCALL64_entry_trampoline =
1453 (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline +
1454 (entry_SYSCALL_64_trampoline - _entry_trampoline);
1456 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1457 wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline);
1459 #ifdef CONFIG_IA32_EMULATION
1460 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1462 * This only works on Intel CPUs.
1463 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1464 * This does not cause SYSENTER to jump to the wrong location, because
1465 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1467 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1468 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_SYSENTER_stack(cpu) + 1));
1469 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1471 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1472 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1473 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1474 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1477 /* Flags to clear on syscall */
1478 wrmsrl(MSR_SYSCALL_MASK,
1479 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1480 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1484 * Copies of the original ist values from the tss are only accessed during
1485 * debugging, no special alignment required.
1487 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1489 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1490 DEFINE_PER_CPU(int, debug_stack_usage);
1492 int is_debug_stack(unsigned long addr)
1494 return __this_cpu_read(debug_stack_usage) ||
1495 (addr <= __this_cpu_read(debug_stack_addr) &&
1496 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1498 NOKPROBE_SYMBOL(is_debug_stack);
1500 DEFINE_PER_CPU(u32, debug_idt_ctr);
1502 void debug_stack_set_zero(void)
1504 this_cpu_inc(debug_idt_ctr);
1507 NOKPROBE_SYMBOL(debug_stack_set_zero);
1509 void debug_stack_reset(void)
1511 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1513 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1516 NOKPROBE_SYMBOL(debug_stack_reset);
1518 #else /* CONFIG_X86_64 */
1520 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1521 EXPORT_PER_CPU_SYMBOL(current_task);
1522 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1523 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1526 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1527 * the top of the kernel stack. Use an extra percpu variable to track the
1528 * top of the kernel stack directly.
1530 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1531 (unsigned long)&init_thread_union + THREAD_SIZE;
1532 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1534 #ifdef CONFIG_CC_STACKPROTECTOR
1535 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1538 #endif /* CONFIG_X86_64 */
1541 * Clear all 6 debug registers:
1543 static void clear_all_debug_regs(void)
1547 for (i = 0; i < 8; i++) {
1548 /* Ignore db4, db5 */
1549 if ((i == 4) || (i == 5))
1558 * Restore debug regs if using kgdbwait and you have a kernel debugger
1559 * connection established.
1561 static void dbg_restore_debug_regs(void)
1563 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1564 arch_kgdb_ops.correct_hw_break();
1566 #else /* ! CONFIG_KGDB */
1567 #define dbg_restore_debug_regs()
1568 #endif /* ! CONFIG_KGDB */
1570 static void wait_for_master_cpu(int cpu)
1574 * wait for ACK from master CPU before continuing
1575 * with AP initialization
1577 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1578 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1584 * cpu_init() initializes state that is per-CPU. Some data is already
1585 * initialized (naturally) in the bootstrap process, such as the GDT
1586 * and IDT. We reload them nevertheless, this function acts as a
1587 * 'CPU state barrier', nothing should get across.
1588 * A lot of state is already set up in PDA init for 64 bit
1590 #ifdef CONFIG_X86_64
1594 struct orig_ist *oist;
1595 struct task_struct *me;
1596 struct tss_struct *t;
1598 int cpu = raw_smp_processor_id();
1601 wait_for_master_cpu(cpu);
1604 * Initialize the CR4 shadow before doing anything that could
1612 t = &per_cpu(cpu_tss_rw, cpu);
1613 oist = &per_cpu(orig_ist, cpu);
1616 if (this_cpu_read(numa_node) == 0 &&
1617 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1618 set_numa_node(early_cpu_to_node(cpu));
1623 pr_debug("Initializing CPU#%d\n", cpu);
1625 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1628 * Initialize the per-CPU GDT with the boot GDT,
1629 * and set up the GDT descriptor:
1632 switch_to_new_gdt(cpu);
1637 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1640 wrmsrl(MSR_FS_BASE, 0);
1641 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1648 * set up and load the per-CPU TSS
1650 if (!oist->ist[0]) {
1651 char *estacks = get_cpu_entry_area(cpu)->exception_stacks;
1653 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1654 estacks += exception_stack_sizes[v];
1655 oist->ist[v] = t->x86_tss.ist[v] =
1656 (unsigned long)estacks;
1657 if (v == DEBUG_STACK-1)
1658 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1662 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1665 * <= is required because the CPU will access up to
1666 * 8 bits beyond the end of the IO permission bitmap.
1668 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1669 t->io_bitmap[i] = ~0UL;
1672 me->active_mm = &init_mm;
1674 initialize_tlbstate_and_flush();
1675 enter_lazy_tlb(&init_mm, me);
1678 * Initialize the TSS. sp0 points to the entry trampoline stack
1679 * regardless of what task is running.
1681 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1683 load_sp0((unsigned long)(cpu_SYSENTER_stack(cpu) + 1));
1685 load_mm_ldt(&init_mm);
1687 clear_all_debug_regs();
1688 dbg_restore_debug_regs();
1695 load_fixmap_gdt(cpu);
1702 int cpu = smp_processor_id();
1703 struct task_struct *curr = current;
1704 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu);
1706 wait_for_master_cpu(cpu);
1709 * Initialize the CR4 shadow before doing anything that could
1714 show_ucode_info_early();
1716 pr_info("Initializing CPU#%d\n", cpu);
1718 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1719 boot_cpu_has(X86_FEATURE_TSC) ||
1720 boot_cpu_has(X86_FEATURE_DE))
1721 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1724 switch_to_new_gdt(cpu);
1727 * Set up and load the per-CPU TSS and LDT
1730 curr->active_mm = &init_mm;
1732 initialize_tlbstate_and_flush();
1733 enter_lazy_tlb(&init_mm, curr);
1736 * Initialize the TSS. Don't bother initializing sp0, as the initial
1737 * task never enters user mode.
1739 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1742 load_mm_ldt(&init_mm);
1744 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1746 #ifdef CONFIG_DOUBLEFAULT
1747 /* Set up doublefault TSS pointer in the GDT */
1748 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1751 clear_all_debug_regs();
1752 dbg_restore_debug_regs();
1756 load_fixmap_gdt(cpu);
1760 static void bsp_resume(void)
1762 if (this_cpu->c_bsp_resume)
1763 this_cpu->c_bsp_resume(&boot_cpu_data);
1766 static struct syscore_ops cpu_syscore_ops = {
1767 .resume = bsp_resume,
1770 static int __init init_cpu_syscore(void)
1772 register_syscore_ops(&cpu_syscore_ops);
1775 core_initcall(init_cpu_syscore);