1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched.h>
11 #include <linux/init.h>
12 #include <linux/kprobes.h>
13 #include <linux/kgdb.h>
14 #include <linux/smp.h>
16 #include <linux/syscore_ops.h>
18 #include <asm/stackprotector.h>
19 #include <asm/perf_event.h>
20 #include <asm/mmu_context.h>
21 #include <asm/archrandom.h>
22 #include <asm/hypervisor.h>
23 #include <asm/processor.h>
24 #include <asm/tlbflush.h>
25 #include <asm/debugreg.h>
26 #include <asm/sections.h>
27 #include <asm/vsyscall.h>
28 #include <linux/topology.h>
29 #include <linux/cpumask.h>
30 #include <asm/pgtable.h>
31 #include <linux/atomic.h>
32 #include <asm/proto.h>
33 #include <asm/setup.h>
36 #include <asm/fpu/internal.h>
38 #include <linux/numa.h>
44 #include <asm/microcode.h>
45 #include <asm/microcode_intel.h>
47 #ifdef CONFIG_X86_LOCAL_APIC
48 #include <asm/uv/uv.h>
53 /* all of these masks are initialized in setup_cpu_local_masks() */
54 cpumask_var_t cpu_initialized_mask;
55 cpumask_var_t cpu_callout_mask;
56 cpumask_var_t cpu_callin_mask;
58 /* representing cpus for which sibling maps can be computed */
59 cpumask_var_t cpu_sibling_setup_mask;
61 /* correctly size the local cpu masks */
62 void __init setup_cpu_local_masks(void)
64 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
65 alloc_bootmem_cpumask_var(&cpu_callin_mask);
66 alloc_bootmem_cpumask_var(&cpu_callout_mask);
67 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
70 static void default_init(struct cpuinfo_x86 *c)
73 cpu_detect_cache_sizes(c);
75 /* Not much we can do here... */
76 /* Check if at least it has cpuid */
77 if (c->cpuid_level == -1) {
78 /* No cpuid. It must be an ancient CPU */
80 strcpy(c->x86_model_id, "486");
82 strcpy(c->x86_model_id, "386");
87 static const struct cpu_dev default_cpu = {
88 .c_init = default_init,
89 .c_vendor = "Unknown",
90 .c_x86_vendor = X86_VENDOR_UNKNOWN,
93 static const struct cpu_dev *this_cpu = &default_cpu;
95 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
98 * We need valid kernel segments for data and code in long mode too
99 * IRET will check the segment types kkeil 2000/10/28
100 * Also sysret mandates a special GDT layout
102 * TLS descriptors are currently at a different place compared to i386.
103 * Hopefully nobody expects them at a fixed place (Wine?)
105 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
106 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
107 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
108 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
109 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
110 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
114 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
117 * Segments used for calling PnP BIOS have byte granularity.
118 * They code segments and data segments have fixed 64k limits,
119 * the transfer segment sizes are set at run time.
122 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
124 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
126 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
128 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
130 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
132 * The APM segments have byte granularity and their bases
133 * are set at run time. All have 64k limits.
136 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
138 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
140 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
142 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
143 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
144 GDT_STACK_CANARY_INIT
147 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
149 static int __init x86_mpx_setup(char *s)
151 /* require an exact match without trailing characters */
155 /* do not emit a message if the feature is not present */
156 if (!boot_cpu_has(X86_FEATURE_MPX))
159 setup_clear_cpu_cap(X86_FEATURE_MPX);
160 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
163 __setup("nompx", x86_mpx_setup);
165 static int __init x86_noinvpcid_setup(char *s)
167 /* noinvpcid doesn't accept parameters */
171 /* do not emit a message if the feature is not present */
172 if (!boot_cpu_has(X86_FEATURE_INVPCID))
175 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
176 pr_info("noinvpcid: INVPCID feature disabled\n");
179 early_param("noinvpcid", x86_noinvpcid_setup);
182 static int cachesize_override = -1;
183 static int disable_x86_serial_nr = 1;
185 static int __init cachesize_setup(char *str)
187 get_option(&str, &cachesize_override);
190 __setup("cachesize=", cachesize_setup);
192 static int __init x86_sep_setup(char *s)
194 setup_clear_cpu_cap(X86_FEATURE_SEP);
197 __setup("nosep", x86_sep_setup);
199 /* Standard macro to see if a specific flag is changeable */
200 static inline int flag_is_changeable_p(u32 flag)
205 * Cyrix and IDT cpus allow disabling of CPUID
206 * so the code below may return different results
207 * when it is executed before and after enabling
208 * the CPUID. Add "volatile" to not allow gcc to
209 * optimize the subsequent calls to this function.
211 asm volatile ("pushfl \n\t"
222 : "=&r" (f1), "=&r" (f2)
225 return ((f1^f2) & flag) != 0;
228 /* Probe for the CPUID instruction */
229 int have_cpuid_p(void)
231 return flag_is_changeable_p(X86_EFLAGS_ID);
234 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
236 unsigned long lo, hi;
238 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
241 /* Disable processor serial number: */
243 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
245 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
247 pr_notice("CPU serial number disabled.\n");
248 clear_cpu_cap(c, X86_FEATURE_PN);
250 /* Disabling the serial number may affect the cpuid level */
251 c->cpuid_level = cpuid_eax(0);
254 static int __init x86_serial_nr_setup(char *s)
256 disable_x86_serial_nr = 0;
259 __setup("serialnumber", x86_serial_nr_setup);
261 static inline int flag_is_changeable_p(u32 flag)
265 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
270 static __init int setup_disable_smep(char *arg)
272 setup_clear_cpu_cap(X86_FEATURE_SMEP);
275 __setup("nosmep", setup_disable_smep);
277 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
279 if (cpu_has(c, X86_FEATURE_SMEP))
280 cr4_set_bits(X86_CR4_SMEP);
283 static __init int setup_disable_smap(char *arg)
285 setup_clear_cpu_cap(X86_FEATURE_SMAP);
288 __setup("nosmap", setup_disable_smap);
290 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
292 unsigned long eflags = native_save_fl();
294 /* This should have been cleared long ago */
295 BUG_ON(eflags & X86_EFLAGS_AC);
297 if (cpu_has(c, X86_FEATURE_SMAP)) {
298 #ifdef CONFIG_X86_SMAP
299 cr4_set_bits(X86_CR4_SMAP);
301 cr4_clear_bits(X86_CR4_SMAP);
307 * Protection Keys are not available in 32-bit mode.
309 static bool pku_disabled;
311 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
313 if (!cpu_has(c, X86_FEATURE_PKU))
318 cr4_set_bits(X86_CR4_PKE);
320 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
321 * cpuid bit to be set. We need to ensure that we
322 * update that bit in this CPU's "cpu_info".
327 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
328 static __init int setup_disable_pku(char *arg)
331 * Do not clear the X86_FEATURE_PKU bit. All of the
332 * runtime checks are against OSPKE so clearing the
335 * This way, we will see "pku" in cpuinfo, but not
336 * "ospke", which is exactly what we want. It shows
337 * that the CPU has PKU, but the OS has not enabled it.
338 * This happens to be exactly how a system would look
339 * if we disabled the config option.
341 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
345 __setup("nopku", setup_disable_pku);
346 #endif /* CONFIG_X86_64 */
349 * Some CPU features depend on higher CPUID levels, which may not always
350 * be available due to CPUID level capping or broken virtualization
351 * software. Add those features to this table to auto-disable them.
353 struct cpuid_dependent_feature {
358 static const struct cpuid_dependent_feature
359 cpuid_dependent_features[] = {
360 { X86_FEATURE_MWAIT, 0x00000005 },
361 { X86_FEATURE_DCA, 0x00000009 },
362 { X86_FEATURE_XSAVE, 0x0000000d },
366 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
368 const struct cpuid_dependent_feature *df;
370 for (df = cpuid_dependent_features; df->feature; df++) {
372 if (!cpu_has(c, df->feature))
375 * Note: cpuid_level is set to -1 if unavailable, but
376 * extended_extended_level is set to 0 if unavailable
377 * and the legitimate extended levels are all negative
378 * when signed; hence the weird messing around with
381 if (!((s32)df->level < 0 ?
382 (u32)df->level > (u32)c->extended_cpuid_level :
383 (s32)df->level > (s32)c->cpuid_level))
386 clear_cpu_cap(c, df->feature);
390 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
391 x86_cap_flag(df->feature), df->level);
396 * Naming convention should be: <Name> [(<Codename>)]
397 * This table only is used unless init_<vendor>() below doesn't set it;
398 * in particular, if CPUID levels 0x80000002..4 are supported, this
402 /* Look up CPU names by table lookup. */
403 static const char *table_lookup_model(struct cpuinfo_x86 *c)
406 const struct legacy_cpu_model_info *info;
408 if (c->x86_model >= 16)
409 return NULL; /* Range check */
414 info = this_cpu->legacy_models;
416 while (info->family) {
417 if (info->family == c->x86)
418 return info->model_names[c->x86_model];
422 return NULL; /* Not found */
425 __u32 cpu_caps_cleared[NCAPINTS];
426 __u32 cpu_caps_set[NCAPINTS];
428 void load_percpu_segment(int cpu)
431 loadsegment(fs, __KERNEL_PERCPU);
433 __loadsegment_simple(gs, 0);
434 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
436 load_stack_canary_segment();
440 * Current gdt points %fs at the "master" per-cpu area: after this,
441 * it's on the real one.
443 void switch_to_new_gdt(int cpu)
445 struct desc_ptr gdt_descr;
447 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
448 gdt_descr.size = GDT_SIZE - 1;
449 load_gdt(&gdt_descr);
450 /* Reload the per-cpu base */
452 load_percpu_segment(cpu);
455 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
457 static void get_model_name(struct cpuinfo_x86 *c)
462 if (c->extended_cpuid_level < 0x80000004)
465 v = (unsigned int *)c->x86_model_id;
466 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
467 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
468 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
469 c->x86_model_id[48] = 0;
471 /* Trim whitespace */
472 p = q = s = &c->x86_model_id[0];
478 /* Note the last non-whitespace index */
488 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
490 unsigned int n, dummy, ebx, ecx, edx, l2size;
492 n = c->extended_cpuid_level;
494 if (n >= 0x80000005) {
495 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
496 c->x86_cache_size = (ecx>>24) + (edx>>24);
498 /* On K8 L1 TLB is inclusive, so don't count it */
503 if (n < 0x80000006) /* Some chips just has a large L1. */
506 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
510 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
512 /* do processor-specific cache resizing */
513 if (this_cpu->legacy_cache_size)
514 l2size = this_cpu->legacy_cache_size(c, l2size);
516 /* Allow user to override all this if necessary. */
517 if (cachesize_override != -1)
518 l2size = cachesize_override;
521 return; /* Again, no L2 cache is possible */
524 c->x86_cache_size = l2size;
527 u16 __read_mostly tlb_lli_4k[NR_INFO];
528 u16 __read_mostly tlb_lli_2m[NR_INFO];
529 u16 __read_mostly tlb_lli_4m[NR_INFO];
530 u16 __read_mostly tlb_lld_4k[NR_INFO];
531 u16 __read_mostly tlb_lld_2m[NR_INFO];
532 u16 __read_mostly tlb_lld_4m[NR_INFO];
533 u16 __read_mostly tlb_lld_1g[NR_INFO];
535 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
537 if (this_cpu->c_detect_tlb)
538 this_cpu->c_detect_tlb(c);
540 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
541 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
542 tlb_lli_4m[ENTRIES]);
544 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
545 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
546 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
549 void detect_ht(struct cpuinfo_x86 *c)
552 u32 eax, ebx, ecx, edx;
553 int index_msb, core_bits;
556 if (!cpu_has(c, X86_FEATURE_HT))
559 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
562 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
565 cpuid(1, &eax, &ebx, &ecx, &edx);
567 smp_num_siblings = (ebx & 0xff0000) >> 16;
569 if (smp_num_siblings == 1) {
570 pr_info_once("CPU0: Hyper-Threading is disabled\n");
574 if (smp_num_siblings <= 1)
577 index_msb = get_count_order(smp_num_siblings);
578 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
580 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
582 index_msb = get_count_order(smp_num_siblings);
584 core_bits = get_count_order(c->x86_max_cores);
586 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
587 ((1 << core_bits) - 1);
590 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
591 pr_info("CPU: Physical Processor ID: %d\n",
593 pr_info("CPU: Processor Core ID: %d\n",
600 static void get_cpu_vendor(struct cpuinfo_x86 *c)
602 char *v = c->x86_vendor_id;
605 for (i = 0; i < X86_VENDOR_NUM; i++) {
609 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
610 (cpu_devs[i]->c_ident[1] &&
611 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
613 this_cpu = cpu_devs[i];
614 c->x86_vendor = this_cpu->c_x86_vendor;
619 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
620 "CPU: Your system may be unstable.\n", v);
622 c->x86_vendor = X86_VENDOR_UNKNOWN;
623 this_cpu = &default_cpu;
626 void cpu_detect(struct cpuinfo_x86 *c)
628 /* Get vendor name */
629 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
630 (unsigned int *)&c->x86_vendor_id[0],
631 (unsigned int *)&c->x86_vendor_id[8],
632 (unsigned int *)&c->x86_vendor_id[4]);
635 /* Intel-defined flags: level 0x00000001 */
636 if (c->cpuid_level >= 0x00000001) {
637 u32 junk, tfms, cap0, misc;
639 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
640 c->x86 = x86_family(tfms);
641 c->x86_model = x86_model(tfms);
642 c->x86_mask = x86_stepping(tfms);
644 if (cap0 & (1<<19)) {
645 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
646 c->x86_cache_alignment = c->x86_clflush_size;
651 void get_cpu_cap(struct cpuinfo_x86 *c)
653 u32 eax, ebx, ecx, edx;
655 /* Intel-defined flags: level 0x00000001 */
656 if (c->cpuid_level >= 0x00000001) {
657 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
659 c->x86_capability[CPUID_1_ECX] = ecx;
660 c->x86_capability[CPUID_1_EDX] = edx;
663 /* Additional Intel-defined flags: level 0x00000007 */
664 if (c->cpuid_level >= 0x00000007) {
665 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
667 c->x86_capability[CPUID_7_0_EBX] = ebx;
669 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
670 c->x86_capability[CPUID_7_ECX] = ecx;
673 /* Extended state features: level 0x0000000d */
674 if (c->cpuid_level >= 0x0000000d) {
675 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
677 c->x86_capability[CPUID_D_1_EAX] = eax;
680 /* Additional Intel-defined flags: level 0x0000000F */
681 if (c->cpuid_level >= 0x0000000F) {
683 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
684 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
685 c->x86_capability[CPUID_F_0_EDX] = edx;
687 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
688 /* will be overridden if occupancy monitoring exists */
689 c->x86_cache_max_rmid = ebx;
691 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
692 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
693 c->x86_capability[CPUID_F_1_EDX] = edx;
695 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
696 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
697 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
698 c->x86_cache_max_rmid = ecx;
699 c->x86_cache_occ_scale = ebx;
702 c->x86_cache_max_rmid = -1;
703 c->x86_cache_occ_scale = -1;
707 /* AMD-defined flags: level 0x80000001 */
708 eax = cpuid_eax(0x80000000);
709 c->extended_cpuid_level = eax;
711 if ((eax & 0xffff0000) == 0x80000000) {
712 if (eax >= 0x80000001) {
713 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
715 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
716 c->x86_capability[CPUID_8000_0001_EDX] = edx;
720 if (c->extended_cpuid_level >= 0x80000007) {
721 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
723 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
727 if (c->extended_cpuid_level >= 0x80000008) {
728 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
730 c->x86_virt_bits = (eax >> 8) & 0xff;
731 c->x86_phys_bits = eax & 0xff;
732 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
735 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
736 c->x86_phys_bits = 36;
739 if (c->extended_cpuid_level >= 0x8000000a)
740 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
742 init_scattered_cpuid_features(c);
745 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
751 * First of all, decide if this is a 486 or higher
752 * It's a 486 if we can modify the AC flag
754 if (flag_is_changeable_p(X86_EFLAGS_AC))
759 for (i = 0; i < X86_VENDOR_NUM; i++)
760 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
761 c->x86_vendor_id[0] = 0;
762 cpu_devs[i]->c_identify(c);
763 if (c->x86_vendor_id[0]) {
772 * Do minimum CPU detection early.
773 * Fields really needed: vendor, cpuid_level, family, model, mask,
775 * The others are not touched to avoid unwanted side effects.
777 * WARNING: this function is only called on the BP. Don't add code here
778 * that is supposed to run on all CPUs.
780 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
783 c->x86_clflush_size = 64;
784 c->x86_phys_bits = 36;
785 c->x86_virt_bits = 48;
787 c->x86_clflush_size = 32;
788 c->x86_phys_bits = 32;
789 c->x86_virt_bits = 32;
791 c->x86_cache_alignment = c->x86_clflush_size;
793 memset(&c->x86_capability, 0, sizeof c->x86_capability);
794 c->extended_cpuid_level = 0;
797 identify_cpu_without_cpuid(c);
799 /* cyrix could have cpuid enabled via c_identify()*/
807 if (this_cpu->c_early_init)
808 this_cpu->c_early_init(c);
811 filter_cpuid_features(c, false);
813 if (this_cpu->c_bsp_init)
814 this_cpu->c_bsp_init(c);
816 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
820 void __init early_cpu_init(void)
822 const struct cpu_dev *const *cdev;
825 #ifdef CONFIG_PROCESSOR_SELECT
826 pr_info("KERNEL supported cpus:\n");
829 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
830 const struct cpu_dev *cpudev = *cdev;
832 if (count >= X86_VENDOR_NUM)
834 cpu_devs[count] = cpudev;
837 #ifdef CONFIG_PROCESSOR_SELECT
841 for (j = 0; j < 2; j++) {
842 if (!cpudev->c_ident[j])
844 pr_info(" %s %s\n", cpudev->c_vendor,
850 early_identify_cpu(&boot_cpu_data);
854 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
855 * unfortunately, that's not true in practice because of early VIA
856 * chips and (more importantly) broken virtualizers that are not easy
857 * to detect. In the latter case it doesn't even *fail* reliably, so
858 * probing for it doesn't even work. Disable it completely on 32-bit
859 * unless we can find a reliable way to detect all the broken cases.
860 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
862 static void detect_nopl(struct cpuinfo_x86 *c)
865 clear_cpu_cap(c, X86_FEATURE_NOPL);
867 set_cpu_cap(c, X86_FEATURE_NOPL);
871 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
875 * Empirically, writing zero to a segment selector on AMD does
876 * not clear the base, whereas writing zero to a segment
877 * selector on Intel does clear the base. Intel's behavior
878 * allows slightly faster context switches in the common case
879 * where GS is unused by the prev and next threads.
881 * Since neither vendor documents this anywhere that I can see,
882 * detect it directly instead of hardcoding the choice by
885 * I've designated AMD's behavior as the "bug" because it's
886 * counterintuitive and less friendly.
889 unsigned long old_base, tmp;
890 rdmsrl(MSR_FS_BASE, old_base);
891 wrmsrl(MSR_FS_BASE, 1);
893 rdmsrl(MSR_FS_BASE, tmp);
895 set_cpu_bug(c, X86_BUG_NULL_SEG);
896 wrmsrl(MSR_FS_BASE, old_base);
900 static void generic_identify(struct cpuinfo_x86 *c)
902 c->extended_cpuid_level = 0;
905 identify_cpu_without_cpuid(c);
907 /* cyrix could have cpuid enabled via c_identify()*/
917 if (c->cpuid_level >= 0x00000001) {
918 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
921 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
923 c->apicid = c->initial_apicid;
926 c->phys_proc_id = c->initial_apicid;
929 get_model_name(c); /* Default name */
933 detect_null_seg_behavior(c);
936 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
937 * systems that run Linux at CPL > 0 may or may not have the
938 * issue, but, even if they have the issue, there's absolutely
939 * nothing we can do about it because we can't use the real IRET
942 * NB: For the time being, only 32-bit kernels support
943 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
944 * whether to apply espfix using paravirt hooks. If any
945 * non-paravirt system ever shows up that does *not* have the
946 * ESPFIX issue, we can change this.
949 # ifdef CONFIG_PARAVIRT
951 extern void native_iret(void);
952 if (pv_cpu_ops.iret == native_iret)
953 set_cpu_bug(c, X86_BUG_ESPFIX);
956 set_cpu_bug(c, X86_BUG_ESPFIX);
961 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
964 * The heavy lifting of max_rmid and cache_occ_scale are handled
965 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
966 * in case CQM bits really aren't there in this CPU.
968 if (c != &boot_cpu_data) {
969 boot_cpu_data.x86_cache_max_rmid =
970 min(boot_cpu_data.x86_cache_max_rmid,
971 c->x86_cache_max_rmid);
976 * This does the hard work of actually picking apart the CPU stuff...
978 static void identify_cpu(struct cpuinfo_x86 *c)
982 c->loops_per_jiffy = loops_per_jiffy;
983 c->x86_cache_size = -1;
984 c->x86_vendor = X86_VENDOR_UNKNOWN;
985 c->x86_model = c->x86_mask = 0; /* So far unknown... */
986 c->x86_vendor_id[0] = '\0'; /* Unset */
987 c->x86_model_id[0] = '\0'; /* Unset */
988 c->x86_max_cores = 1;
989 c->x86_coreid_bits = 0;
991 c->x86_clflush_size = 64;
992 c->x86_phys_bits = 36;
993 c->x86_virt_bits = 48;
995 c->cpuid_level = -1; /* CPUID not detected */
996 c->x86_clflush_size = 32;
997 c->x86_phys_bits = 32;
998 c->x86_virt_bits = 32;
1000 c->x86_cache_alignment = c->x86_clflush_size;
1001 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1003 generic_identify(c);
1005 if (this_cpu->c_identify)
1006 this_cpu->c_identify(c);
1008 /* Clear/Set all flags overridden by options, after probe */
1009 for (i = 0; i < NCAPINTS; i++) {
1010 c->x86_capability[i] &= ~cpu_caps_cleared[i];
1011 c->x86_capability[i] |= cpu_caps_set[i];
1014 #ifdef CONFIG_X86_64
1015 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1019 * Vendor-specific initialization. In this section we
1020 * canonicalize the feature flags, meaning if there are
1021 * features a certain CPU supports which CPUID doesn't
1022 * tell us, CPUID claiming incorrect flags, or other bugs,
1023 * we handle them here.
1025 * At the end of this section, c->x86_capability better
1026 * indicate the features this CPU genuinely supports!
1028 if (this_cpu->c_init)
1029 this_cpu->c_init(c);
1031 /* Disable the PN if appropriate */
1032 squash_the_stupid_serial_number(c);
1034 /* Set up SMEP/SMAP */
1039 * The vendor-specific functions might have changed features.
1040 * Now we do "generic changes."
1043 /* Filter out anything that depends on CPUID levels we don't have */
1044 filter_cpuid_features(c, true);
1046 /* If the model name is still unset, do table lookup. */
1047 if (!c->x86_model_id[0]) {
1049 p = table_lookup_model(c);
1051 strcpy(c->x86_model_id, p);
1053 /* Last resort... */
1054 sprintf(c->x86_model_id, "%02x/%02x",
1055 c->x86, c->x86_model);
1058 #ifdef CONFIG_X86_64
1064 x86_init_cache_qos(c);
1068 * Clear/Set all flags overridden by options, need do it
1069 * before following smp all cpus cap AND.
1071 for (i = 0; i < NCAPINTS; i++) {
1072 c->x86_capability[i] &= ~cpu_caps_cleared[i];
1073 c->x86_capability[i] |= cpu_caps_set[i];
1077 * On SMP, boot_cpu_data holds the common feature set between
1078 * all CPUs; so make sure that we indicate which features are
1079 * common between the CPUs. The first time this routine gets
1080 * executed, c == &boot_cpu_data.
1082 if (c != &boot_cpu_data) {
1083 /* AND the already accumulated flags with these */
1084 for (i = 0; i < NCAPINTS; i++)
1085 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1087 /* OR, i.e. replicate the bug flags */
1088 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1089 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1092 /* Init Machine Check Exception if available. */
1095 select_idle_routine(c);
1098 numa_add_cpu(smp_processor_id());
1100 /* The boot/hotplug time assigment got cleared, restore it */
1101 c->logical_proc_id = topology_phys_to_logical_pkg(c->phys_proc_id);
1105 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1106 * on 32-bit kernels:
1108 #ifdef CONFIG_X86_32
1109 void enable_sep_cpu(void)
1111 struct tss_struct *tss;
1114 if (!boot_cpu_has(X86_FEATURE_SEP))
1118 tss = &per_cpu(cpu_tss, cpu);
1121 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1122 * see the big comment in struct x86_hw_tss's definition.
1125 tss->x86_tss.ss1 = __KERNEL_CS;
1126 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1128 wrmsr(MSR_IA32_SYSENTER_ESP,
1129 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
1132 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1138 void __init identify_boot_cpu(void)
1140 identify_cpu(&boot_cpu_data);
1141 init_amd_e400_c1e_mask();
1142 #ifdef CONFIG_X86_32
1146 cpu_detect_tlb(&boot_cpu_data);
1149 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1151 BUG_ON(c == &boot_cpu_data);
1153 #ifdef CONFIG_X86_32
1164 static const struct msr_range msr_range_array[] = {
1165 { 0x00000000, 0x00000418},
1166 { 0xc0000000, 0xc000040b},
1167 { 0xc0010000, 0xc0010142},
1168 { 0xc0011000, 0xc001103b},
1171 static void __print_cpu_msr(void)
1173 unsigned index_min, index_max;
1178 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1179 index_min = msr_range_array[i].min;
1180 index_max = msr_range_array[i].max;
1182 for (index = index_min; index < index_max; index++) {
1183 if (rdmsrl_safe(index, &val))
1185 pr_info(" MSR%08x: %016llx\n", index, val);
1190 static int show_msr;
1192 static __init int setup_show_msr(char *arg)
1196 get_option(&arg, &num);
1202 __setup("show_msr=", setup_show_msr);
1204 static __init int setup_noclflush(char *arg)
1206 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1207 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1210 __setup("noclflush", setup_noclflush);
1212 void print_cpu_info(struct cpuinfo_x86 *c)
1214 const char *vendor = NULL;
1216 if (c->x86_vendor < X86_VENDOR_NUM) {
1217 vendor = this_cpu->c_vendor;
1219 if (c->cpuid_level >= 0)
1220 vendor = c->x86_vendor_id;
1223 if (vendor && !strstr(c->x86_model_id, vendor))
1224 pr_cont("%s ", vendor);
1226 if (c->x86_model_id[0])
1227 pr_cont("%s", c->x86_model_id);
1229 pr_cont("%d86", c->x86);
1231 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1233 if (c->x86_mask || c->cpuid_level >= 0)
1234 pr_cont(", stepping: 0x%x)\n", c->x86_mask);
1241 void print_cpu_msr(struct cpuinfo_x86 *c)
1243 if (c->cpu_index < show_msr)
1247 static __init int setup_disablecpuid(char *arg)
1251 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1252 setup_clear_cpu_cap(bit);
1258 __setup("clearcpuid=", setup_disablecpuid);
1260 #ifdef CONFIG_X86_64
1261 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1262 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
1263 (unsigned long) debug_idt_table };
1265 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1266 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1269 * The following percpu variables are hot. Align current_task to
1270 * cacheline size such that they fall in the same cacheline.
1272 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1274 EXPORT_PER_CPU_SYMBOL(current_task);
1276 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1277 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1279 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1281 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1282 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1285 * Special IST stacks which the CPU switches to when it calls
1286 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1287 * limit), all of them are 4K, except the debug stack which
1290 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1291 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1292 [DEBUG_STACK - 1] = DEBUG_STKSZ
1295 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1296 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1298 /* May not be marked __init: used by software suspend */
1299 void syscall_init(void)
1302 * LSTAR and STAR live in a bit strange symbiosis.
1303 * They both write to the same internal register. STAR allows to
1304 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1306 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1307 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1309 #ifdef CONFIG_IA32_EMULATION
1310 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1312 * This only works on Intel CPUs.
1313 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1314 * This does not cause SYSENTER to jump to the wrong location, because
1315 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1317 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1318 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1319 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1321 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1322 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1323 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1324 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1327 /* Flags to clear on syscall */
1328 wrmsrl(MSR_SYSCALL_MASK,
1329 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1330 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1334 * Copies of the original ist values from the tss are only accessed during
1335 * debugging, no special alignment required.
1337 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1339 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1340 DEFINE_PER_CPU(int, debug_stack_usage);
1342 int is_debug_stack(unsigned long addr)
1344 return __this_cpu_read(debug_stack_usage) ||
1345 (addr <= __this_cpu_read(debug_stack_addr) &&
1346 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1348 NOKPROBE_SYMBOL(is_debug_stack);
1350 DEFINE_PER_CPU(u32, debug_idt_ctr);
1352 void debug_stack_set_zero(void)
1354 this_cpu_inc(debug_idt_ctr);
1357 NOKPROBE_SYMBOL(debug_stack_set_zero);
1359 void debug_stack_reset(void)
1361 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1363 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1366 NOKPROBE_SYMBOL(debug_stack_reset);
1368 #else /* CONFIG_X86_64 */
1370 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1371 EXPORT_PER_CPU_SYMBOL(current_task);
1372 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1373 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1376 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1377 * the top of the kernel stack. Use an extra percpu variable to track the
1378 * top of the kernel stack directly.
1380 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1381 (unsigned long)&init_thread_union + THREAD_SIZE;
1382 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1384 #ifdef CONFIG_CC_STACKPROTECTOR
1385 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1388 #endif /* CONFIG_X86_64 */
1391 * Clear all 6 debug registers:
1393 static void clear_all_debug_regs(void)
1397 for (i = 0; i < 8; i++) {
1398 /* Ignore db4, db5 */
1399 if ((i == 4) || (i == 5))
1408 * Restore debug regs if using kgdbwait and you have a kernel debugger
1409 * connection established.
1411 static void dbg_restore_debug_regs(void)
1413 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1414 arch_kgdb_ops.correct_hw_break();
1416 #else /* ! CONFIG_KGDB */
1417 #define dbg_restore_debug_regs()
1418 #endif /* ! CONFIG_KGDB */
1420 static void wait_for_master_cpu(int cpu)
1424 * wait for ACK from master CPU before continuing
1425 * with AP initialization
1427 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1428 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1434 * cpu_init() initializes state that is per-CPU. Some data is already
1435 * initialized (naturally) in the bootstrap process, such as the GDT
1436 * and IDT. We reload them nevertheless, this function acts as a
1437 * 'CPU state barrier', nothing should get across.
1438 * A lot of state is already set up in PDA init for 64 bit
1440 #ifdef CONFIG_X86_64
1444 struct orig_ist *oist;
1445 struct task_struct *me;
1446 struct tss_struct *t;
1448 int cpu = stack_smp_processor_id();
1451 wait_for_master_cpu(cpu);
1454 * Initialize the CR4 shadow before doing anything that could
1460 * Load microcode on this cpu if a valid microcode is available.
1461 * This is early microcode loading procedure.
1465 t = &per_cpu(cpu_tss, cpu);
1466 oist = &per_cpu(orig_ist, cpu);
1469 if (this_cpu_read(numa_node) == 0 &&
1470 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1471 set_numa_node(early_cpu_to_node(cpu));
1476 pr_debug("Initializing CPU#%d\n", cpu);
1478 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1481 * Initialize the per-CPU GDT with the boot GDT,
1482 * and set up the GDT descriptor:
1485 switch_to_new_gdt(cpu);
1490 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1493 wrmsrl(MSR_FS_BASE, 0);
1494 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1501 * set up and load the per-CPU TSS
1503 if (!oist->ist[0]) {
1504 char *estacks = per_cpu(exception_stacks, cpu);
1506 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1507 estacks += exception_stack_sizes[v];
1508 oist->ist[v] = t->x86_tss.ist[v] =
1509 (unsigned long)estacks;
1510 if (v == DEBUG_STACK-1)
1511 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1515 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1518 * <= is required because the CPU will access up to
1519 * 8 bits beyond the end of the IO permission bitmap.
1521 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1522 t->io_bitmap[i] = ~0UL;
1524 atomic_inc(&init_mm.mm_count);
1525 me->active_mm = &init_mm;
1527 enter_lazy_tlb(&init_mm, me);
1529 load_sp0(t, ¤t->thread);
1530 set_tss_desc(cpu, t);
1532 load_mm_ldt(&init_mm);
1534 clear_all_debug_regs();
1535 dbg_restore_debug_regs();
1547 int cpu = smp_processor_id();
1548 struct task_struct *curr = current;
1549 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
1550 struct thread_struct *thread = &curr->thread;
1552 wait_for_master_cpu(cpu);
1555 * Initialize the CR4 shadow before doing anything that could
1560 show_ucode_info_early();
1562 pr_info("Initializing CPU#%d\n", cpu);
1564 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1565 boot_cpu_has(X86_FEATURE_TSC) ||
1566 boot_cpu_has(X86_FEATURE_DE))
1567 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1570 switch_to_new_gdt(cpu);
1573 * Set up and load the per-CPU TSS and LDT
1575 atomic_inc(&init_mm.mm_count);
1576 curr->active_mm = &init_mm;
1578 enter_lazy_tlb(&init_mm, curr);
1580 load_sp0(t, thread);
1581 set_tss_desc(cpu, t);
1583 load_mm_ldt(&init_mm);
1585 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1587 #ifdef CONFIG_DOUBLEFAULT
1588 /* Set up doublefault TSS pointer in the GDT */
1589 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1592 clear_all_debug_regs();
1593 dbg_restore_debug_regs();
1599 static void bsp_resume(void)
1601 if (this_cpu->c_bsp_resume)
1602 this_cpu->c_bsp_resume(&boot_cpu_data);
1605 static struct syscore_ops cpu_syscore_ops = {
1606 .resume = bsp_resume,
1609 static int __init init_cpu_syscore(void)
1611 register_syscore_ops(&cpu_syscore_ops);
1614 core_initcall(init_cpu_syscore);