1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
25 #ifdef CONFIG_X86_LOCAL_APIC
26 #include <asm/mpspec.h>
28 #include <mach_apic.h>
29 #include <asm/genapic.h>
33 #include <asm/pgtable.h>
34 #include <asm/processor.h>
36 #include <asm/atomic.h>
37 #include <asm/proto.h>
38 #include <asm/sections.h>
39 #include <asm/setup.h>
40 #include <asm/hypervisor.h>
46 /* all of these masks are initialized in setup_cpu_local_masks() */
47 cpumask_var_t cpu_callin_mask;
48 cpumask_var_t cpu_callout_mask;
49 cpumask_var_t cpu_initialized_mask;
51 /* representing cpus for which sibling maps can be computed */
52 cpumask_var_t cpu_sibling_setup_mask;
54 #else /* CONFIG_X86_32 */
56 cpumask_t cpu_callin_map;
57 cpumask_t cpu_callout_map;
58 cpumask_t cpu_initialized;
59 cpumask_t cpu_sibling_setup_map;
61 #endif /* CONFIG_X86_32 */
64 static struct cpu_dev *this_cpu __cpuinitdata;
67 /* We need valid kernel segments for data and code in long mode too
68 * IRET will check the segment types kkeil 2000/10/28
69 * Also sysret mandates a special GDT layout
71 /* The TLS descriptors are currently at a different place compared to i386.
72 Hopefully nobody expects them at a fixed place (Wine?) */
73 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
74 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
75 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
76 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
77 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
78 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
79 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
82 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
83 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
84 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
85 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
86 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
88 * Segments used for calling PnP BIOS have byte granularity.
89 * They code segments and data segments have fixed 64k limits,
90 * the transfer segment sizes are set at run time.
93 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
95 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
97 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
99 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
101 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
103 * The APM segments have byte granularity and their bases
104 * are set at run time. All have 64k limits.
107 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
109 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
111 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
113 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
114 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
117 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
120 static int cachesize_override __cpuinitdata = -1;
121 static int disable_x86_serial_nr __cpuinitdata = 1;
123 static int __init cachesize_setup(char *str)
125 get_option(&str, &cachesize_override);
128 __setup("cachesize=", cachesize_setup);
130 static int __init x86_fxsr_setup(char *s)
132 setup_clear_cpu_cap(X86_FEATURE_FXSR);
133 setup_clear_cpu_cap(X86_FEATURE_XMM);
136 __setup("nofxsr", x86_fxsr_setup);
138 static int __init x86_sep_setup(char *s)
140 setup_clear_cpu_cap(X86_FEATURE_SEP);
143 __setup("nosep", x86_sep_setup);
145 /* Standard macro to see if a specific flag is changeable */
146 static inline int flag_is_changeable_p(u32 flag)
151 * Cyrix and IDT cpus allow disabling of CPUID
152 * so the code below may return different results
153 * when it is executed before and after enabling
154 * the CPUID. Add "volatile" to not allow gcc to
155 * optimize the subsequent calls to this function.
157 asm volatile ("pushfl\n\t"
167 : "=&r" (f1), "=&r" (f2)
170 return ((f1^f2) & flag) != 0;
173 /* Probe for the CPUID instruction */
174 static int __cpuinit have_cpuid_p(void)
176 return flag_is_changeable_p(X86_EFLAGS_ID);
179 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
181 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
182 /* Disable processor serial number */
183 unsigned long lo, hi;
184 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
186 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
187 printk(KERN_NOTICE "CPU serial number disabled.\n");
188 clear_cpu_cap(c, X86_FEATURE_PN);
190 /* Disabling the serial number may affect the cpuid level */
191 c->cpuid_level = cpuid_eax(0);
195 static int __init x86_serial_nr_setup(char *s)
197 disable_x86_serial_nr = 0;
200 __setup("serialnumber", x86_serial_nr_setup);
202 static inline int flag_is_changeable_p(u32 flag)
206 /* Probe for the CPUID instruction */
207 static inline int have_cpuid_p(void)
211 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
217 * Naming convention should be: <Name> [(<Codename>)]
218 * This table only is used unless init_<vendor>() below doesn't set it;
219 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
223 /* Look up CPU names by table lookup. */
224 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
226 struct cpu_model_info *info;
228 if (c->x86_model >= 16)
229 return NULL; /* Range check */
234 info = this_cpu->c_models;
236 while (info && info->family) {
237 if (info->family == c->x86)
238 return info->model_names[c->x86_model];
241 return NULL; /* Not found */
244 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
246 /* Current gdt points %fs at the "master" per-cpu area: after this,
247 * it's on the real one. */
248 void switch_to_new_gdt(void)
250 struct desc_ptr gdt_descr;
252 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
253 gdt_descr.size = GDT_SIZE - 1;
254 load_gdt(&gdt_descr);
256 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
260 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
262 static void __cpuinit default_init(struct cpuinfo_x86 *c)
265 display_cacheinfo(c);
267 /* Not much we can do here... */
268 /* Check if at least it has cpuid */
269 if (c->cpuid_level == -1) {
270 /* No cpuid. It must be an ancient CPU */
272 strcpy(c->x86_model_id, "486");
273 else if (c->x86 == 3)
274 strcpy(c->x86_model_id, "386");
279 static struct cpu_dev __cpuinitdata default_cpu = {
280 .c_init = default_init,
281 .c_vendor = "Unknown",
282 .c_x86_vendor = X86_VENDOR_UNKNOWN,
285 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
290 if (c->extended_cpuid_level < 0x80000004)
293 v = (unsigned int *) c->x86_model_id;
294 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
295 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
296 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
297 c->x86_model_id[48] = 0;
299 /* Intel chips right-justify this string for some dumb reason;
300 undo that brain damage */
301 p = q = &c->x86_model_id[0];
307 while (q <= &c->x86_model_id[48])
308 *q++ = '\0'; /* Zero-pad the rest */
312 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
314 unsigned int n, dummy, ebx, ecx, edx, l2size;
316 n = c->extended_cpuid_level;
318 if (n >= 0x80000005) {
319 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
320 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
321 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
322 c->x86_cache_size = (ecx>>24) + (edx>>24);
324 /* On K8 L1 TLB is inclusive, so don't count it */
329 if (n < 0x80000006) /* Some chips just has a large L1. */
332 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
336 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
338 /* do processor-specific cache resizing */
339 if (this_cpu->c_size_cache)
340 l2size = this_cpu->c_size_cache(c, l2size);
342 /* Allow user to override all this if necessary. */
343 if (cachesize_override != -1)
344 l2size = cachesize_override;
347 return; /* Again, no L2 cache is possible */
350 c->x86_cache_size = l2size;
352 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
356 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
359 u32 eax, ebx, ecx, edx;
360 int index_msb, core_bits;
362 if (!cpu_has(c, X86_FEATURE_HT))
365 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
368 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
371 cpuid(1, &eax, &ebx, &ecx, &edx);
373 smp_num_siblings = (ebx & 0xff0000) >> 16;
375 if (smp_num_siblings == 1) {
376 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
377 } else if (smp_num_siblings > 1) {
379 if (smp_num_siblings > nr_cpu_ids) {
380 printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
382 smp_num_siblings = 1;
386 index_msb = get_count_order(smp_num_siblings);
388 c->phys_proc_id = phys_pkg_id(index_msb);
390 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
393 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
395 index_msb = get_count_order(smp_num_siblings);
397 core_bits = get_count_order(c->x86_max_cores);
400 c->cpu_core_id = phys_pkg_id(index_msb) &
401 ((1 << core_bits) - 1);
403 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
404 ((1 << core_bits) - 1);
409 if ((c->x86_max_cores * smp_num_siblings) > 1) {
410 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
412 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
418 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
420 char *v = c->x86_vendor_id;
424 for (i = 0; i < X86_VENDOR_NUM; i++) {
428 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
429 (cpu_devs[i]->c_ident[1] &&
430 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
431 this_cpu = cpu_devs[i];
432 c->x86_vendor = this_cpu->c_x86_vendor;
439 printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v);
440 printk(KERN_ERR "CPU: Your system may be unstable.\n");
443 c->x86_vendor = X86_VENDOR_UNKNOWN;
444 this_cpu = &default_cpu;
447 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
449 /* Get vendor name */
450 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
451 (unsigned int *)&c->x86_vendor_id[0],
452 (unsigned int *)&c->x86_vendor_id[8],
453 (unsigned int *)&c->x86_vendor_id[4]);
456 /* Intel-defined flags: level 0x00000001 */
457 if (c->cpuid_level >= 0x00000001) {
458 u32 junk, tfms, cap0, misc;
459 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
460 c->x86 = (tfms >> 8) & 0xf;
461 c->x86_model = (tfms >> 4) & 0xf;
462 c->x86_mask = tfms & 0xf;
464 c->x86 += (tfms >> 20) & 0xff;
466 c->x86_model += ((tfms >> 16) & 0xf) << 4;
467 if (cap0 & (1<<19)) {
468 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
469 c->x86_cache_alignment = c->x86_clflush_size;
474 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
479 /* Intel-defined flags: level 0x00000001 */
480 if (c->cpuid_level >= 0x00000001) {
481 u32 capability, excap;
482 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
483 c->x86_capability[0] = capability;
484 c->x86_capability[4] = excap;
487 /* AMD-defined flags: level 0x80000001 */
488 xlvl = cpuid_eax(0x80000000);
489 c->extended_cpuid_level = xlvl;
490 if ((xlvl & 0xffff0000) == 0x80000000) {
491 if (xlvl >= 0x80000001) {
492 c->x86_capability[1] = cpuid_edx(0x80000001);
493 c->x86_capability[6] = cpuid_ecx(0x80000001);
498 if (c->extended_cpuid_level >= 0x80000008) {
499 u32 eax = cpuid_eax(0x80000008);
501 c->x86_virt_bits = (eax >> 8) & 0xff;
502 c->x86_phys_bits = eax & 0xff;
506 if (c->extended_cpuid_level >= 0x80000007)
507 c->x86_power = cpuid_edx(0x80000007);
511 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
517 * First of all, decide if this is a 486 or higher
518 * It's a 486 if we can modify the AC flag
520 if (flag_is_changeable_p(X86_EFLAGS_AC))
525 for (i = 0; i < X86_VENDOR_NUM; i++)
526 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
527 c->x86_vendor_id[0] = 0;
528 cpu_devs[i]->c_identify(c);
529 if (c->x86_vendor_id[0]) {
538 * Do minimum CPU detection early.
539 * Fields really needed: vendor, cpuid_level, family, model, mask,
541 * The others are not touched to avoid unwanted side effects.
543 * WARNING: this function is only called on the BP. Don't add code here
544 * that is supposed to run on all CPUs.
546 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
549 c->x86_clflush_size = 64;
551 c->x86_clflush_size = 32;
553 c->x86_cache_alignment = c->x86_clflush_size;
555 memset(&c->x86_capability, 0, sizeof c->x86_capability);
556 c->extended_cpuid_level = 0;
559 identify_cpu_without_cpuid(c);
561 /* cyrix could have cpuid enabled via c_identify()*/
571 if (this_cpu->c_early_init)
572 this_cpu->c_early_init(c);
574 validate_pat_support(c);
577 c->cpu_index = boot_cpu_id;
581 void __init early_cpu_init(void)
583 struct cpu_dev **cdev;
586 printk("KERNEL supported cpus:\n");
587 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
588 struct cpu_dev *cpudev = *cdev;
591 if (count >= X86_VENDOR_NUM)
593 cpu_devs[count] = cpudev;
596 for (j = 0; j < 2; j++) {
597 if (!cpudev->c_ident[j])
599 printk(" %s %s\n", cpudev->c_vendor,
604 early_identify_cpu(&boot_cpu_data);
608 * The NOPL instruction is supposed to exist on all CPUs with
609 * family >= 6; unfortunately, that's not true in practice because
610 * of early VIA chips and (more importantly) broken virtualizers that
611 * are not easy to detect. In the latter case it doesn't even *fail*
612 * reliably, so probing for it doesn't even work. Disable it completely
613 * unless we can find a reliable way to detect all the broken cases.
615 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
617 clear_cpu_cap(c, X86_FEATURE_NOPL);
620 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
622 c->extended_cpuid_level = 0;
625 identify_cpu_without_cpuid(c);
627 /* cyrix could have cpuid enabled via c_identify()*/
637 if (c->cpuid_level >= 0x00000001) {
638 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
640 # ifdef CONFIG_X86_HT
641 c->apicid = phys_pkg_id(c->initial_apicid, 0);
643 c->apicid = c->initial_apicid;
648 c->phys_proc_id = c->initial_apicid;
652 get_model_name(c); /* Default name */
654 init_scattered_cpuid_features(c);
659 * This does the hard work of actually picking apart the CPU stuff...
661 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
665 c->loops_per_jiffy = loops_per_jiffy;
666 c->x86_cache_size = -1;
667 c->x86_vendor = X86_VENDOR_UNKNOWN;
668 c->x86_model = c->x86_mask = 0; /* So far unknown... */
669 c->x86_vendor_id[0] = '\0'; /* Unset */
670 c->x86_model_id[0] = '\0'; /* Unset */
671 c->x86_max_cores = 1;
672 c->x86_coreid_bits = 0;
674 c->x86_clflush_size = 64;
676 c->cpuid_level = -1; /* CPUID not detected */
677 c->x86_clflush_size = 32;
679 c->x86_cache_alignment = c->x86_clflush_size;
680 memset(&c->x86_capability, 0, sizeof c->x86_capability);
684 if (this_cpu->c_identify)
685 this_cpu->c_identify(c);
688 c->apicid = phys_pkg_id(0);
692 * Vendor-specific initialization. In this section we
693 * canonicalize the feature flags, meaning if there are
694 * features a certain CPU supports which CPUID doesn't
695 * tell us, CPUID claiming incorrect flags, or other bugs,
696 * we handle them here.
698 * At the end of this section, c->x86_capability better
699 * indicate the features this CPU genuinely supports!
701 if (this_cpu->c_init)
704 /* Disable the PN if appropriate */
705 squash_the_stupid_serial_number(c);
708 * The vendor-specific functions might have changed features. Now
709 * we do "generic changes."
712 /* If the model name is still unset, do table lookup. */
713 if (!c->x86_model_id[0]) {
715 p = table_lookup_model(c);
717 strcpy(c->x86_model_id, p);
720 sprintf(c->x86_model_id, "%02x/%02x",
721 c->x86, c->x86_model);
730 * On SMP, boot_cpu_data holds the common feature set between
731 * all CPUs; so make sure that we indicate which features are
732 * common between the CPUs. The first time this routine gets
733 * executed, c == &boot_cpu_data.
735 if (c != &boot_cpu_data) {
736 /* AND the already accumulated flags with these */
737 for (i = 0; i < NCAPINTS; i++)
738 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
741 /* Clear all flags overriden by options */
742 for (i = 0; i < NCAPINTS; i++)
743 c->x86_capability[i] &= ~cleared_cpu_caps[i];
745 #ifdef CONFIG_X86_MCE
746 /* Init Machine Check Exception if available. */
750 select_idle_routine(c);
752 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
753 numa_add_cpu(smp_processor_id());
758 static void vgetcpu_set_mode(void)
760 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
761 vgetcpu_mode = VGETCPU_RDTSCP;
763 vgetcpu_mode = VGETCPU_LSL;
767 void __init identify_boot_cpu(void)
769 identify_cpu(&boot_cpu_data);
778 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
780 BUG_ON(c == &boot_cpu_data);
793 static struct msr_range msr_range_array[] __cpuinitdata = {
794 { 0x00000000, 0x00000418},
795 { 0xc0000000, 0xc000040b},
796 { 0xc0010000, 0xc0010142},
797 { 0xc0011000, 0xc001103b},
800 static void __cpuinit print_cpu_msr(void)
805 unsigned index_min, index_max;
807 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
808 index_min = msr_range_array[i].min;
809 index_max = msr_range_array[i].max;
810 for (index = index_min; index < index_max; index++) {
811 if (rdmsrl_amd_safe(index, &val))
813 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
818 static int show_msr __cpuinitdata;
819 static __init int setup_show_msr(char *arg)
823 get_option(&arg, &num);
829 __setup("show_msr=", setup_show_msr);
831 static __init int setup_noclflush(char *arg)
833 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
836 __setup("noclflush", setup_noclflush);
838 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
842 if (c->x86_vendor < X86_VENDOR_NUM)
843 vendor = this_cpu->c_vendor;
844 else if (c->cpuid_level >= 0)
845 vendor = c->x86_vendor_id;
847 if (vendor && !strstr(c->x86_model_id, vendor))
848 printk(KERN_CONT "%s ", vendor);
850 if (c->x86_model_id[0])
851 printk(KERN_CONT "%s", c->x86_model_id);
853 printk(KERN_CONT "%d86", c->x86);
855 if (c->x86_mask || c->cpuid_level >= 0)
856 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
858 printk(KERN_CONT "\n");
861 if (c->cpu_index < show_msr)
869 static __init int setup_disablecpuid(char *arg)
872 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
873 setup_clear_cpu_cap(bit);
878 __setup("clearcpuid=", setup_disablecpuid);
881 struct x8664_pda **_cpu_pda __read_mostly;
882 EXPORT_SYMBOL(_cpu_pda);
884 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
886 static char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
888 void __cpuinit pda_init(int cpu)
890 struct x8664_pda *pda = cpu_pda(cpu);
892 /* Setup up data that may be needed in __get_free_pages early */
895 /* Memory clobbers used to order PDA accessed */
897 wrmsrl(MSR_GS_BASE, pda);
900 pda->cpunumber = cpu;
902 pda->kernelstack = (unsigned long)stack_thread_info() -
903 PDA_STACKOFFSET + THREAD_SIZE;
904 pda->active_mm = &init_mm;
908 /* others are initialized in smpboot.c */
909 pda->pcurrent = &init_task;
910 pda->irqstackptr = boot_cpu_stack;
911 pda->irqstackptr += IRQSTACKSIZE - 64;
913 if (!pda->irqstackptr) {
914 pda->irqstackptr = (char *)
915 __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
916 if (!pda->irqstackptr)
917 panic("cannot allocate irqstack for cpu %d",
919 pda->irqstackptr += IRQSTACKSIZE - 64;
922 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
923 pda->nodenumber = cpu_to_node(cpu);
927 static char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
928 DEBUG_STKSZ] __page_aligned_bss;
930 extern asmlinkage void ignore_sysret(void);
932 /* May not be marked __init: used by software suspend */
933 void syscall_init(void)
936 * LSTAR and STAR live in a bit strange symbiosis.
937 * They both write to the same internal register. STAR allows to
938 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
940 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
941 wrmsrl(MSR_LSTAR, system_call);
942 wrmsrl(MSR_CSTAR, ignore_sysret);
944 #ifdef CONFIG_IA32_EMULATION
945 syscall32_cpu_init();
948 /* Flags to clear on syscall */
949 wrmsrl(MSR_SYSCALL_MASK,
950 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
953 unsigned long kernel_eflags;
956 * Copies of the original ist values from the tss are only accessed during
957 * debugging, no special alignment required.
959 DEFINE_PER_CPU(struct orig_ist, orig_ist);
963 /* Make sure %fs is initialized properly in idle threads */
964 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
966 memset(regs, 0, sizeof(struct pt_regs));
967 regs->fs = __KERNEL_PERCPU;
973 * cpu_init() initializes state that is per-CPU. Some data is already
974 * initialized (naturally) in the bootstrap process, such as the GDT
975 * and IDT. We reload them nevertheless, this function acts as a
976 * 'CPU state barrier', nothing should get across.
977 * A lot of state is already set up in PDA init for 64 bit
980 void __cpuinit cpu_init(void)
982 int cpu = stack_smp_processor_id();
983 struct tss_struct *t = &per_cpu(init_tss, cpu);
984 struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
986 char *estacks = NULL;
987 struct task_struct *me;
990 /* CPU 0 is initialised in head64.c */
994 estacks = boot_exception_stacks;
998 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
999 panic("CPU#%d already initialized!\n", cpu);
1001 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1003 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1006 * Initialize the per-CPU GDT with the boot GDT,
1007 * and set up the GDT descriptor:
1010 switch_to_new_gdt();
1011 load_idt((const struct desc_ptr *)&idt_descr);
1013 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1016 wrmsrl(MSR_FS_BASE, 0);
1017 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1021 if (cpu != 0 && x2apic)
1025 * set up and load the per-CPU TSS
1027 if (!orig_ist->ist[0]) {
1028 static const unsigned int order[N_EXCEPTION_STACKS] = {
1029 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
1030 [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
1032 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1034 estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
1036 panic("Cannot allocate exception "
1037 "stack %ld %d\n", v, cpu);
1039 estacks += PAGE_SIZE << order[v];
1040 orig_ist->ist[v] = t->x86_tss.ist[v] =
1041 (unsigned long)estacks;
1045 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1047 * <= is required because the CPU will access up to
1048 * 8 bits beyond the end of the IO permission bitmap.
1050 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1051 t->io_bitmap[i] = ~0UL;
1053 atomic_inc(&init_mm.mm_count);
1054 me->active_mm = &init_mm;
1057 enter_lazy_tlb(&init_mm, me);
1059 load_sp0(t, ¤t->thread);
1060 set_tss_desc(cpu, t);
1062 load_LDT(&init_mm.context);
1066 * If the kgdb is connected no debug regs should be altered. This
1067 * is only applicable when KGDB and a KGDB I/O module are built
1068 * into the kernel and you are using early debugging with
1069 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1071 if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
1072 arch_kgdb_ops.correct_hw_break();
1076 * Clear all 6 debug registers:
1079 set_debugreg(0UL, 0);
1080 set_debugreg(0UL, 1);
1081 set_debugreg(0UL, 2);
1082 set_debugreg(0UL, 3);
1083 set_debugreg(0UL, 6);
1084 set_debugreg(0UL, 7);
1086 /* If the kgdb is connected no debug regs should be altered. */
1092 raw_local_save_flags(kernel_eflags);
1100 void __cpuinit cpu_init(void)
1102 int cpu = smp_processor_id();
1103 struct task_struct *curr = current;
1104 struct tss_struct *t = &per_cpu(init_tss, cpu);
1105 struct thread_struct *thread = &curr->thread;
1107 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1108 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1109 for (;;) local_irq_enable();
1112 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1114 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1115 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1117 load_idt(&idt_descr);
1118 switch_to_new_gdt();
1121 * Set up and load the per-CPU TSS and LDT
1123 atomic_inc(&init_mm.mm_count);
1124 curr->active_mm = &init_mm;
1127 enter_lazy_tlb(&init_mm, curr);
1129 load_sp0(t, thread);
1130 set_tss_desc(cpu, t);
1132 load_LDT(&init_mm.context);
1134 #ifdef CONFIG_DOUBLEFAULT
1135 /* Set up doublefault TSS pointer in the GDT */
1136 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1140 asm volatile ("mov %0, %%gs" : : "r" (0));
1142 /* Clear all 6 debug registers: */
1151 * Force FPU initialization:
1154 current_thread_info()->status = TS_XSAVE;
1156 current_thread_info()->status = 0;
1158 mxcsr_feature_mask_init();
1161 * Boot processor to setup the FP and extended state context info.
1163 if (smp_processor_id() == boot_cpu_id)
1164 init_thread_xstate();