1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/cpu.h>
13 #include <linux/module.h>
14 #include <linux/nospec.h>
15 #include <linux/prctl.h>
16 #include <linux/sched/smt.h>
17 #include <linux/pgtable.h>
18 #include <linux/bpf.h>
20 #include <asm/spec-ctrl.h>
21 #include <asm/cmdline.h>
23 #include <asm/processor.h>
24 #include <asm/processor-flags.h>
25 #include <asm/fpu/api.h>
28 #include <asm/paravirt.h>
29 #include <asm/intel-family.h>
30 #include <asm/e820/api.h>
31 #include <asm/hypervisor.h>
32 #include <asm/tlbflush.h>
37 static void __init spectre_v1_select_mitigation(void);
38 static void __init spectre_v2_select_mitigation(void);
39 static void __init retbleed_select_mitigation(void);
40 static void __init spectre_v2_user_select_mitigation(void);
41 static void __init ssb_select_mitigation(void);
42 static void __init l1tf_select_mitigation(void);
43 static void __init mds_select_mitigation(void);
44 static void __init md_clear_update_mitigation(void);
45 static void __init md_clear_select_mitigation(void);
46 static void __init taa_select_mitigation(void);
47 static void __init mmio_select_mitigation(void);
48 static void __init srbds_select_mitigation(void);
49 static void __init l1d_flush_select_mitigation(void);
51 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
52 u64 x86_spec_ctrl_base;
53 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
55 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
56 DEFINE_PER_CPU(u64, x86_spec_ctrl_current);
57 EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);
59 static DEFINE_MUTEX(spec_ctrl_mutex);
61 /* Update SPEC_CTRL MSR and its cached copy unconditionally */
62 static void update_spec_ctrl(u64 val)
64 this_cpu_write(x86_spec_ctrl_current, val);
65 wrmsrl(MSR_IA32_SPEC_CTRL, val);
69 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ
70 * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
72 void update_spec_ctrl_cond(u64 val)
74 if (this_cpu_read(x86_spec_ctrl_current) == val)
77 this_cpu_write(x86_spec_ctrl_current, val);
80 * When KERNEL_IBRS this MSR is written on return-to-user, unless
81 * forced the update can be delayed until that time.
83 if (!cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
84 wrmsrl(MSR_IA32_SPEC_CTRL, val);
87 noinstr u64 spec_ctrl_current(void)
89 return this_cpu_read(x86_spec_ctrl_current);
91 EXPORT_SYMBOL_GPL(spec_ctrl_current);
94 * AMD specific MSR info for Speculative Store Bypass control.
95 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
97 u64 __ro_after_init x86_amd_ls_cfg_base;
98 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
100 /* Control conditional STIBP in switch_to() */
101 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
102 /* Control conditional IBPB in switch_mm() */
103 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
104 /* Control unconditional IBPB in switch_mm() */
105 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
107 /* Control MDS CPU buffer clear before returning to user space */
108 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
109 EXPORT_SYMBOL_GPL(mds_user_clear);
110 /* Control MDS CPU buffer clear before idling (halt, mwait) */
111 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
112 EXPORT_SYMBOL_GPL(mds_idle_clear);
115 * Controls whether l1d flush based mitigations are enabled,
116 * based on hw features and admin setting via boot parameter
119 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
121 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
122 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear);
123 EXPORT_SYMBOL_GPL(mmio_stale_data_clear);
125 void __init cpu_select_mitigations(void)
128 * Read the SPEC_CTRL MSR to account for reserved bits which may
129 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
130 * init code as it is not enumerated and depends on the family.
132 if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) {
133 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
136 * Previously running kernel (kexec), may have some controls
137 * turned ON. Clear them and let the mitigations setup below
138 * rediscover them based on configuration.
140 x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;
143 /* Select the proper CPU mitigations before patching alternatives: */
144 spectre_v1_select_mitigation();
145 spectre_v2_select_mitigation();
147 * retbleed_select_mitigation() relies on the state set by
148 * spectre_v2_select_mitigation(); specifically it wants to know about
151 retbleed_select_mitigation();
153 * spectre_v2_user_select_mitigation() relies on the state set by
154 * retbleed_select_mitigation(); specifically the STIBP selection is
155 * forced for UNRET or IBPB.
157 spectre_v2_user_select_mitigation();
158 ssb_select_mitigation();
159 l1tf_select_mitigation();
160 md_clear_select_mitigation();
161 srbds_select_mitigation();
162 l1d_flush_select_mitigation();
166 * NOTE: This function is *only* called for SVM, since Intel uses
167 * MSR_IA32_SPEC_CTRL for SSBD.
170 x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl, bool setguest)
172 u64 guestval, hostval;
173 struct thread_info *ti = current_thread_info();
176 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
177 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
179 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
180 !static_cpu_has(X86_FEATURE_VIRT_SSBD))
184 * If the host has SSBD mitigation enabled, force it in the host's
185 * virtual MSR value. If its not permanently enabled, evaluate
186 * current's TIF_SSBD thread flag.
188 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
189 hostval = SPEC_CTRL_SSBD;
191 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
193 /* Sanitize the guest value */
194 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
196 if (hostval != guestval) {
199 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
200 ssbd_spec_ctrl_to_tif(hostval);
202 speculation_ctrl_update(tif);
205 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
207 static void x86_amd_ssb_disable(void)
209 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
211 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
212 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
213 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
214 wrmsrl(MSR_AMD64_LS_CFG, msrval);
218 #define pr_fmt(fmt) "MDS: " fmt
220 /* Default mitigation for MDS-affected CPUs */
221 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
222 static bool mds_nosmt __ro_after_init = false;
224 static const char * const mds_strings[] = {
225 [MDS_MITIGATION_OFF] = "Vulnerable",
226 [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers",
227 [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
230 static void __init mds_select_mitigation(void)
232 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
233 mds_mitigation = MDS_MITIGATION_OFF;
237 if (mds_mitigation == MDS_MITIGATION_FULL) {
238 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
239 mds_mitigation = MDS_MITIGATION_VMWERV;
241 static_branch_enable(&mds_user_clear);
243 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
244 (mds_nosmt || cpu_mitigations_auto_nosmt()))
245 cpu_smt_disable(false);
249 static int __init mds_cmdline(char *str)
251 if (!boot_cpu_has_bug(X86_BUG_MDS))
257 if (!strcmp(str, "off"))
258 mds_mitigation = MDS_MITIGATION_OFF;
259 else if (!strcmp(str, "full"))
260 mds_mitigation = MDS_MITIGATION_FULL;
261 else if (!strcmp(str, "full,nosmt")) {
262 mds_mitigation = MDS_MITIGATION_FULL;
268 early_param("mds", mds_cmdline);
271 #define pr_fmt(fmt) "TAA: " fmt
273 enum taa_mitigations {
275 TAA_MITIGATION_UCODE_NEEDED,
277 TAA_MITIGATION_TSX_DISABLED,
280 /* Default mitigation for TAA-affected CPUs */
281 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
282 static bool taa_nosmt __ro_after_init;
284 static const char * const taa_strings[] = {
285 [TAA_MITIGATION_OFF] = "Vulnerable",
286 [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
287 [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
288 [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled",
291 static void __init taa_select_mitigation(void)
295 if (!boot_cpu_has_bug(X86_BUG_TAA)) {
296 taa_mitigation = TAA_MITIGATION_OFF;
300 /* TSX previously disabled by tsx=off */
301 if (!boot_cpu_has(X86_FEATURE_RTM)) {
302 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
306 if (cpu_mitigations_off()) {
307 taa_mitigation = TAA_MITIGATION_OFF;
312 * TAA mitigation via VERW is turned off if both
313 * tsx_async_abort=off and mds=off are specified.
315 if (taa_mitigation == TAA_MITIGATION_OFF &&
316 mds_mitigation == MDS_MITIGATION_OFF)
319 if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
320 taa_mitigation = TAA_MITIGATION_VERW;
322 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
325 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
326 * A microcode update fixes this behavior to clear CPU buffers. It also
327 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
328 * ARCH_CAP_TSX_CTRL_MSR bit.
330 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
331 * update is required.
333 ia32_cap = x86_read_arch_cap_msr();
334 if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
335 !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
336 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
339 * TSX is enabled, select alternate mitigation for TAA which is
340 * the same as MDS. Enable MDS static branch to clear CPU buffers.
342 * For guests that can't determine whether the correct microcode is
343 * present on host, enable the mitigation for UCODE_NEEDED as well.
345 static_branch_enable(&mds_user_clear);
347 if (taa_nosmt || cpu_mitigations_auto_nosmt())
348 cpu_smt_disable(false);
351 static int __init tsx_async_abort_parse_cmdline(char *str)
353 if (!boot_cpu_has_bug(X86_BUG_TAA))
359 if (!strcmp(str, "off")) {
360 taa_mitigation = TAA_MITIGATION_OFF;
361 } else if (!strcmp(str, "full")) {
362 taa_mitigation = TAA_MITIGATION_VERW;
363 } else if (!strcmp(str, "full,nosmt")) {
364 taa_mitigation = TAA_MITIGATION_VERW;
370 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
373 #define pr_fmt(fmt) "MMIO Stale Data: " fmt
375 enum mmio_mitigations {
377 MMIO_MITIGATION_UCODE_NEEDED,
378 MMIO_MITIGATION_VERW,
381 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */
382 static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW;
383 static bool mmio_nosmt __ro_after_init = false;
385 static const char * const mmio_strings[] = {
386 [MMIO_MITIGATION_OFF] = "Vulnerable",
387 [MMIO_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
388 [MMIO_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
391 static void __init mmio_select_mitigation(void)
395 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
396 boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) ||
397 cpu_mitigations_off()) {
398 mmio_mitigation = MMIO_MITIGATION_OFF;
402 if (mmio_mitigation == MMIO_MITIGATION_OFF)
405 ia32_cap = x86_read_arch_cap_msr();
408 * Enable CPU buffer clear mitigation for host and VMM, if also affected
409 * by MDS or TAA. Otherwise, enable mitigation for VMM only.
411 if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) &&
412 boot_cpu_has(X86_FEATURE_RTM)))
413 static_branch_enable(&mds_user_clear);
415 static_branch_enable(&mmio_stale_data_clear);
418 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can
419 * be propagated to uncore buffers, clearing the Fill buffers on idle
420 * is required irrespective of SMT state.
422 if (!(ia32_cap & ARCH_CAP_FBSDP_NO))
423 static_branch_enable(&mds_idle_clear);
426 * Check if the system has the right microcode.
428 * CPU Fill buffer clear mitigation is enumerated by either an explicit
429 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
432 if ((ia32_cap & ARCH_CAP_FB_CLEAR) ||
433 (boot_cpu_has(X86_FEATURE_MD_CLEAR) &&
434 boot_cpu_has(X86_FEATURE_FLUSH_L1D) &&
435 !(ia32_cap & ARCH_CAP_MDS_NO)))
436 mmio_mitigation = MMIO_MITIGATION_VERW;
438 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED;
440 if (mmio_nosmt || cpu_mitigations_auto_nosmt())
441 cpu_smt_disable(false);
444 static int __init mmio_stale_data_parse_cmdline(char *str)
446 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
452 if (!strcmp(str, "off")) {
453 mmio_mitigation = MMIO_MITIGATION_OFF;
454 } else if (!strcmp(str, "full")) {
455 mmio_mitigation = MMIO_MITIGATION_VERW;
456 } else if (!strcmp(str, "full,nosmt")) {
457 mmio_mitigation = MMIO_MITIGATION_VERW;
463 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline);
466 #define pr_fmt(fmt) "" fmt
468 static void __init md_clear_update_mitigation(void)
470 if (cpu_mitigations_off())
473 if (!static_key_enabled(&mds_user_clear))
477 * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data
478 * mitigation, if necessary.
480 if (mds_mitigation == MDS_MITIGATION_OFF &&
481 boot_cpu_has_bug(X86_BUG_MDS)) {
482 mds_mitigation = MDS_MITIGATION_FULL;
483 mds_select_mitigation();
485 if (taa_mitigation == TAA_MITIGATION_OFF &&
486 boot_cpu_has_bug(X86_BUG_TAA)) {
487 taa_mitigation = TAA_MITIGATION_VERW;
488 taa_select_mitigation();
490 if (mmio_mitigation == MMIO_MITIGATION_OFF &&
491 boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) {
492 mmio_mitigation = MMIO_MITIGATION_VERW;
493 mmio_select_mitigation();
496 if (boot_cpu_has_bug(X86_BUG_MDS))
497 pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
498 if (boot_cpu_has_bug(X86_BUG_TAA))
499 pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
500 if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
501 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
502 else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
503 pr_info("MMIO Stale Data: Unknown: No mitigations\n");
506 static void __init md_clear_select_mitigation(void)
508 mds_select_mitigation();
509 taa_select_mitigation();
510 mmio_select_mitigation();
513 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
514 * and print their mitigation after MDS, TAA and MMIO Stale Data
515 * mitigation selection is done.
517 md_clear_update_mitigation();
521 #define pr_fmt(fmt) "SRBDS: " fmt
523 enum srbds_mitigations {
524 SRBDS_MITIGATION_OFF,
525 SRBDS_MITIGATION_UCODE_NEEDED,
526 SRBDS_MITIGATION_FULL,
527 SRBDS_MITIGATION_TSX_OFF,
528 SRBDS_MITIGATION_HYPERVISOR,
531 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
533 static const char * const srbds_strings[] = {
534 [SRBDS_MITIGATION_OFF] = "Vulnerable",
535 [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
536 [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode",
537 [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled",
538 [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status",
541 static bool srbds_off;
543 void update_srbds_msr(void)
547 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
550 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
553 if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
557 * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX
558 * being disabled and it hasn't received the SRBDS MSR microcode.
560 if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
563 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
565 switch (srbds_mitigation) {
566 case SRBDS_MITIGATION_OFF:
567 case SRBDS_MITIGATION_TSX_OFF:
568 mcu_ctrl |= RNGDS_MITG_DIS;
570 case SRBDS_MITIGATION_FULL:
571 mcu_ctrl &= ~RNGDS_MITG_DIS;
577 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
580 static void __init srbds_select_mitigation(void)
584 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
588 * Check to see if this is one of the MDS_NO systems supporting TSX that
589 * are only exposed to SRBDS when TSX is enabled or when CPU is affected
590 * by Processor MMIO Stale Data vulnerability.
592 ia32_cap = x86_read_arch_cap_msr();
593 if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
594 !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
595 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
596 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
597 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
598 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
599 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
600 else if (cpu_mitigations_off() || srbds_off)
601 srbds_mitigation = SRBDS_MITIGATION_OFF;
604 pr_info("%s\n", srbds_strings[srbds_mitigation]);
607 static int __init srbds_parse_cmdline(char *str)
612 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
615 srbds_off = !strcmp(str, "off");
618 early_param("srbds", srbds_parse_cmdline);
621 #define pr_fmt(fmt) "L1D Flush : " fmt
623 enum l1d_flush_mitigations {
628 static enum l1d_flush_mitigations l1d_flush_mitigation __initdata = L1D_FLUSH_OFF;
630 static void __init l1d_flush_select_mitigation(void)
632 if (!l1d_flush_mitigation || !boot_cpu_has(X86_FEATURE_FLUSH_L1D))
635 static_branch_enable(&switch_mm_cond_l1d_flush);
636 pr_info("Conditional flush on switch_mm() enabled\n");
639 static int __init l1d_flush_parse_cmdline(char *str)
641 if (!strcmp(str, "on"))
642 l1d_flush_mitigation = L1D_FLUSH_ON;
646 early_param("l1d_flush", l1d_flush_parse_cmdline);
649 #define pr_fmt(fmt) "Spectre V1 : " fmt
651 enum spectre_v1_mitigation {
652 SPECTRE_V1_MITIGATION_NONE,
653 SPECTRE_V1_MITIGATION_AUTO,
656 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
657 SPECTRE_V1_MITIGATION_AUTO;
659 static const char * const spectre_v1_strings[] = {
660 [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
661 [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
665 * Does SMAP provide full mitigation against speculative kernel access to
668 static bool smap_works_speculatively(void)
670 if (!boot_cpu_has(X86_FEATURE_SMAP))
674 * On CPUs which are vulnerable to Meltdown, SMAP does not
675 * prevent speculative access to user data in the L1 cache.
676 * Consider SMAP to be non-functional as a mitigation on these
679 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
685 static void __init spectre_v1_select_mitigation(void)
687 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
688 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
692 if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
694 * With Spectre v1, a user can speculatively control either
695 * path of a conditional swapgs with a user-controlled GS
696 * value. The mitigation is to add lfences to both code paths.
698 * If FSGSBASE is enabled, the user can put a kernel address in
699 * GS, in which case SMAP provides no protection.
701 * If FSGSBASE is disabled, the user can only put a user space
702 * address in GS. That makes an attack harder, but still
703 * possible if there's no SMAP protection.
705 if (boot_cpu_has(X86_FEATURE_FSGSBASE) ||
706 !smap_works_speculatively()) {
708 * Mitigation can be provided from SWAPGS itself or
709 * PTI as the CR3 write in the Meltdown mitigation
712 * If neither is there, mitigate with an LFENCE to
713 * stop speculation through swapgs.
715 if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
716 !boot_cpu_has(X86_FEATURE_PTI))
717 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
720 * Enable lfences in the kernel entry (non-swapgs)
721 * paths, to prevent user entry from speculatively
724 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
728 pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
731 static int __init nospectre_v1_cmdline(char *str)
733 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
736 early_param("nospectre_v1", nospectre_v1_cmdline);
738 enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = SPECTRE_V2_NONE;
741 #define pr_fmt(fmt) "RETBleed: " fmt
743 enum retbleed_mitigation {
744 RETBLEED_MITIGATION_NONE,
745 RETBLEED_MITIGATION_UNRET,
746 RETBLEED_MITIGATION_IBPB,
747 RETBLEED_MITIGATION_IBRS,
748 RETBLEED_MITIGATION_EIBRS,
749 RETBLEED_MITIGATION_STUFF,
752 enum retbleed_mitigation_cmd {
760 static const char * const retbleed_strings[] = {
761 [RETBLEED_MITIGATION_NONE] = "Vulnerable",
762 [RETBLEED_MITIGATION_UNRET] = "Mitigation: untrained return thunk",
763 [RETBLEED_MITIGATION_IBPB] = "Mitigation: IBPB",
764 [RETBLEED_MITIGATION_IBRS] = "Mitigation: IBRS",
765 [RETBLEED_MITIGATION_EIBRS] = "Mitigation: Enhanced IBRS",
766 [RETBLEED_MITIGATION_STUFF] = "Mitigation: Stuffing",
769 static enum retbleed_mitigation retbleed_mitigation __ro_after_init =
770 RETBLEED_MITIGATION_NONE;
771 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =
774 static int __ro_after_init retbleed_nosmt = false;
776 static int __init retbleed_parse_cmdline(char *str)
782 char *next = strchr(str, ',');
788 if (!strcmp(str, "off")) {
789 retbleed_cmd = RETBLEED_CMD_OFF;
790 } else if (!strcmp(str, "auto")) {
791 retbleed_cmd = RETBLEED_CMD_AUTO;
792 } else if (!strcmp(str, "unret")) {
793 retbleed_cmd = RETBLEED_CMD_UNRET;
794 } else if (!strcmp(str, "ibpb")) {
795 retbleed_cmd = RETBLEED_CMD_IBPB;
796 } else if (!strcmp(str, "stuff")) {
797 retbleed_cmd = RETBLEED_CMD_STUFF;
798 } else if (!strcmp(str, "nosmt")) {
799 retbleed_nosmt = true;
800 } else if (!strcmp(str, "force")) {
801 setup_force_cpu_bug(X86_BUG_RETBLEED);
803 pr_err("Ignoring unknown retbleed option (%s).", str);
811 early_param("retbleed", retbleed_parse_cmdline);
813 #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n"
814 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n"
816 static void __init retbleed_select_mitigation(void)
818 bool mitigate_smt = false;
820 if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off())
823 switch (retbleed_cmd) {
824 case RETBLEED_CMD_OFF:
827 case RETBLEED_CMD_UNRET:
828 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY)) {
829 retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
831 pr_err("WARNING: kernel not compiled with CPU_UNRET_ENTRY.\n");
836 case RETBLEED_CMD_IBPB:
837 if (!boot_cpu_has(X86_FEATURE_IBPB)) {
838 pr_err("WARNING: CPU does not support IBPB.\n");
840 } else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY)) {
841 retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
843 pr_err("WARNING: kernel not compiled with CPU_IBPB_ENTRY.\n");
848 case RETBLEED_CMD_STUFF:
849 if (IS_ENABLED(CONFIG_CALL_DEPTH_TRACKING) &&
850 spectre_v2_enabled == SPECTRE_V2_RETPOLINE) {
851 retbleed_mitigation = RETBLEED_MITIGATION_STUFF;
854 if (IS_ENABLED(CONFIG_CALL_DEPTH_TRACKING))
855 pr_err("WARNING: retbleed=stuff depends on spectre_v2=retpoline\n");
857 pr_err("WARNING: kernel not compiled with CALL_DEPTH_TRACKING.\n");
864 case RETBLEED_CMD_AUTO:
866 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
867 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
868 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY))
869 retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
870 else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY) && boot_cpu_has(X86_FEATURE_IBPB))
871 retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
875 * The Intel mitigation (IBRS or eIBRS) was already selected in
876 * spectre_v2_select_mitigation(). 'retbleed_mitigation' will
877 * be set accordingly below.
883 switch (retbleed_mitigation) {
884 case RETBLEED_MITIGATION_UNRET:
885 setup_force_cpu_cap(X86_FEATURE_RETHUNK);
886 setup_force_cpu_cap(X86_FEATURE_UNRET);
888 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
889 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
890 pr_err(RETBLEED_UNTRAIN_MSG);
895 case RETBLEED_MITIGATION_IBPB:
896 setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB);
900 case RETBLEED_MITIGATION_STUFF:
901 setup_force_cpu_cap(X86_FEATURE_RETHUNK);
902 setup_force_cpu_cap(X86_FEATURE_CALL_DEPTH);
903 x86_set_skl_return_thunk();
910 if (mitigate_smt && !boot_cpu_has(X86_FEATURE_STIBP) &&
911 (retbleed_nosmt || cpu_mitigations_auto_nosmt()))
912 cpu_smt_disable(false);
915 * Let IBRS trump all on Intel without affecting the effects of the
916 * retbleed= cmdline option except for call depth based stuffing
918 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
919 switch (spectre_v2_enabled) {
920 case SPECTRE_V2_IBRS:
921 retbleed_mitigation = RETBLEED_MITIGATION_IBRS;
923 case SPECTRE_V2_EIBRS:
924 case SPECTRE_V2_EIBRS_RETPOLINE:
925 case SPECTRE_V2_EIBRS_LFENCE:
926 retbleed_mitigation = RETBLEED_MITIGATION_EIBRS;
929 if (retbleed_mitigation != RETBLEED_MITIGATION_STUFF)
930 pr_err(RETBLEED_INTEL_MSG);
934 pr_info("%s\n", retbleed_strings[retbleed_mitigation]);
938 #define pr_fmt(fmt) "Spectre V2 : " fmt
940 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
941 SPECTRE_V2_USER_NONE;
942 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
943 SPECTRE_V2_USER_NONE;
945 #ifdef CONFIG_RETPOLINE
946 static bool spectre_v2_bad_module;
948 bool retpoline_module_ok(bool has_retpoline)
950 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
953 pr_err("System may be vulnerable to spectre v2\n");
954 spectre_v2_bad_module = true;
958 static inline const char *spectre_v2_module_string(void)
960 return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
963 static inline const char *spectre_v2_module_string(void) { return ""; }
966 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
967 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
968 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
969 #define SPECTRE_V2_IBRS_PERF_MSG "WARNING: IBRS mitigation selected on Enhanced IBRS CPU, this may cause unnecessary performance loss\n"
971 #ifdef CONFIG_BPF_SYSCALL
972 void unpriv_ebpf_notify(int new_state)
977 /* Unprivileged eBPF is enabled */
979 switch (spectre_v2_enabled) {
980 case SPECTRE_V2_EIBRS:
981 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
983 case SPECTRE_V2_EIBRS_LFENCE:
984 if (sched_smt_active())
985 pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
993 static inline bool match_option(const char *arg, int arglen, const char *opt)
995 int len = strlen(opt);
997 return len == arglen && !strncmp(arg, opt, len);
1000 /* The kernel command line selection for spectre v2 */
1001 enum spectre_v2_mitigation_cmd {
1002 SPECTRE_V2_CMD_NONE,
1003 SPECTRE_V2_CMD_AUTO,
1004 SPECTRE_V2_CMD_FORCE,
1005 SPECTRE_V2_CMD_RETPOLINE,
1006 SPECTRE_V2_CMD_RETPOLINE_GENERIC,
1007 SPECTRE_V2_CMD_RETPOLINE_LFENCE,
1008 SPECTRE_V2_CMD_EIBRS,
1009 SPECTRE_V2_CMD_EIBRS_RETPOLINE,
1010 SPECTRE_V2_CMD_EIBRS_LFENCE,
1011 SPECTRE_V2_CMD_IBRS,
1014 enum spectre_v2_user_cmd {
1015 SPECTRE_V2_USER_CMD_NONE,
1016 SPECTRE_V2_USER_CMD_AUTO,
1017 SPECTRE_V2_USER_CMD_FORCE,
1018 SPECTRE_V2_USER_CMD_PRCTL,
1019 SPECTRE_V2_USER_CMD_PRCTL_IBPB,
1020 SPECTRE_V2_USER_CMD_SECCOMP,
1021 SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
1024 static const char * const spectre_v2_user_strings[] = {
1025 [SPECTRE_V2_USER_NONE] = "User space: Vulnerable",
1026 [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection",
1027 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection",
1028 [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl",
1029 [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl",
1032 static const struct {
1034 enum spectre_v2_user_cmd cmd;
1036 } v2_user_options[] __initconst = {
1037 { "auto", SPECTRE_V2_USER_CMD_AUTO, false },
1038 { "off", SPECTRE_V2_USER_CMD_NONE, false },
1039 { "on", SPECTRE_V2_USER_CMD_FORCE, true },
1040 { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false },
1041 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false },
1042 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false },
1043 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false },
1046 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
1048 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1049 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
1052 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd;
1054 static enum spectre_v2_user_cmd __init
1055 spectre_v2_parse_user_cmdline(void)
1060 switch (spectre_v2_cmd) {
1061 case SPECTRE_V2_CMD_NONE:
1062 return SPECTRE_V2_USER_CMD_NONE;
1063 case SPECTRE_V2_CMD_FORCE:
1064 return SPECTRE_V2_USER_CMD_FORCE;
1069 ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
1072 return SPECTRE_V2_USER_CMD_AUTO;
1074 for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
1075 if (match_option(arg, ret, v2_user_options[i].option)) {
1076 spec_v2_user_print_cond(v2_user_options[i].option,
1077 v2_user_options[i].secure);
1078 return v2_user_options[i].cmd;
1082 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
1083 return SPECTRE_V2_USER_CMD_AUTO;
1086 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)
1088 return spectre_v2_in_eibrs_mode(mode) || mode == SPECTRE_V2_IBRS;
1092 spectre_v2_user_select_mitigation(void)
1094 enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
1095 bool smt_possible = IS_ENABLED(CONFIG_SMP);
1096 enum spectre_v2_user_cmd cmd;
1098 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
1101 if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
1102 cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
1103 smt_possible = false;
1105 cmd = spectre_v2_parse_user_cmdline();
1107 case SPECTRE_V2_USER_CMD_NONE:
1109 case SPECTRE_V2_USER_CMD_FORCE:
1110 mode = SPECTRE_V2_USER_STRICT;
1112 case SPECTRE_V2_USER_CMD_AUTO:
1113 case SPECTRE_V2_USER_CMD_PRCTL:
1114 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1115 mode = SPECTRE_V2_USER_PRCTL;
1117 case SPECTRE_V2_USER_CMD_SECCOMP:
1118 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1119 if (IS_ENABLED(CONFIG_SECCOMP))
1120 mode = SPECTRE_V2_USER_SECCOMP;
1122 mode = SPECTRE_V2_USER_PRCTL;
1126 /* Initialize Indirect Branch Prediction Barrier */
1127 if (boot_cpu_has(X86_FEATURE_IBPB)) {
1128 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
1130 spectre_v2_user_ibpb = mode;
1132 case SPECTRE_V2_USER_CMD_FORCE:
1133 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1134 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1135 static_branch_enable(&switch_mm_always_ibpb);
1136 spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
1138 case SPECTRE_V2_USER_CMD_PRCTL:
1139 case SPECTRE_V2_USER_CMD_AUTO:
1140 case SPECTRE_V2_USER_CMD_SECCOMP:
1141 static_branch_enable(&switch_mm_cond_ibpb);
1147 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
1148 static_key_enabled(&switch_mm_always_ibpb) ?
1149 "always-on" : "conditional");
1153 * If no STIBP, enhanced IBRS is enabled, or SMT impossible, STIBP
1156 * Enhanced IBRS also protects against cross-thread branch target
1157 * injection in user-mode as the IBRS bit remains always set which
1158 * implicitly enables cross-thread protections. However, in legacy IBRS
1159 * mode, the IBRS bit is set only on kernel entry and cleared on return
1160 * to userspace. This disables the implicit cross-thread protection,
1161 * so allow for STIBP to be selected in that case.
1163 if (!boot_cpu_has(X86_FEATURE_STIBP) ||
1165 spectre_v2_in_eibrs_mode(spectre_v2_enabled))
1169 * At this point, an STIBP mode other than "off" has been set.
1170 * If STIBP support is not being forced, check if STIBP always-on
1173 if (mode != SPECTRE_V2_USER_STRICT &&
1174 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
1175 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1177 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
1178 retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
1179 if (mode != SPECTRE_V2_USER_STRICT &&
1180 mode != SPECTRE_V2_USER_STRICT_PREFERRED)
1181 pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n");
1182 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1185 spectre_v2_user_stibp = mode;
1188 pr_info("%s\n", spectre_v2_user_strings[mode]);
1191 static const char * const spectre_v2_strings[] = {
1192 [SPECTRE_V2_NONE] = "Vulnerable",
1193 [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines",
1194 [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE",
1195 [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced / Automatic IBRS",
1196 [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced / Automatic IBRS + LFENCE",
1197 [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced / Automatic IBRS + Retpolines",
1198 [SPECTRE_V2_IBRS] = "Mitigation: IBRS",
1201 static const struct {
1203 enum spectre_v2_mitigation_cmd cmd;
1205 } mitigation_options[] __initconst = {
1206 { "off", SPECTRE_V2_CMD_NONE, false },
1207 { "on", SPECTRE_V2_CMD_FORCE, true },
1208 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
1209 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
1210 { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
1211 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
1212 { "eibrs", SPECTRE_V2_CMD_EIBRS, false },
1213 { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false },
1214 { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false },
1215 { "auto", SPECTRE_V2_CMD_AUTO, false },
1216 { "ibrs", SPECTRE_V2_CMD_IBRS, false },
1219 static void __init spec_v2_print_cond(const char *reason, bool secure)
1221 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1222 pr_info("%s selected on command line.\n", reason);
1225 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
1227 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
1231 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
1232 cpu_mitigations_off())
1233 return SPECTRE_V2_CMD_NONE;
1235 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
1237 return SPECTRE_V2_CMD_AUTO;
1239 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
1240 if (!match_option(arg, ret, mitigation_options[i].option))
1242 cmd = mitigation_options[i].cmd;
1246 if (i >= ARRAY_SIZE(mitigation_options)) {
1247 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1248 return SPECTRE_V2_CMD_AUTO;
1251 if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
1252 cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1253 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC ||
1254 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1255 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1256 !IS_ENABLED(CONFIG_RETPOLINE)) {
1257 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1258 mitigation_options[i].option);
1259 return SPECTRE_V2_CMD_AUTO;
1262 if ((cmd == SPECTRE_V2_CMD_EIBRS ||
1263 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1264 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1265 !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1266 pr_err("%s selected but CPU doesn't have Enhanced or Automatic IBRS. Switching to AUTO select\n",
1267 mitigation_options[i].option);
1268 return SPECTRE_V2_CMD_AUTO;
1271 if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1272 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) &&
1273 !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
1274 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
1275 mitigation_options[i].option);
1276 return SPECTRE_V2_CMD_AUTO;
1279 if (cmd == SPECTRE_V2_CMD_IBRS && !IS_ENABLED(CONFIG_CPU_IBRS_ENTRY)) {
1280 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1281 mitigation_options[i].option);
1282 return SPECTRE_V2_CMD_AUTO;
1285 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1286 pr_err("%s selected but not Intel CPU. Switching to AUTO select\n",
1287 mitigation_options[i].option);
1288 return SPECTRE_V2_CMD_AUTO;
1291 if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) {
1292 pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n",
1293 mitigation_options[i].option);
1294 return SPECTRE_V2_CMD_AUTO;
1297 if (cmd == SPECTRE_V2_CMD_IBRS && cpu_feature_enabled(X86_FEATURE_XENPV)) {
1298 pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n",
1299 mitigation_options[i].option);
1300 return SPECTRE_V2_CMD_AUTO;
1303 spec_v2_print_cond(mitigation_options[i].option,
1304 mitigation_options[i].secure);
1308 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
1310 if (!IS_ENABLED(CONFIG_RETPOLINE)) {
1311 pr_err("Kernel not compiled with retpoline; no mitigation available!");
1312 return SPECTRE_V2_NONE;
1315 return SPECTRE_V2_RETPOLINE;
1318 /* Disable in-kernel use of non-RSB RET predictors */
1319 static void __init spec_ctrl_disable_kernel_rrsba(void)
1323 if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL))
1326 ia32_cap = x86_read_arch_cap_msr();
1328 if (ia32_cap & ARCH_CAP_RRSBA) {
1329 x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;
1330 update_spec_ctrl(x86_spec_ctrl_base);
1334 static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)
1337 * Similar to context switches, there are two types of RSB attacks
1342 * 2) Poisoned RSB entry
1344 * When retpoline is enabled, both are mitigated by filling/clearing
1347 * When IBRS is enabled, while #1 would be mitigated by the IBRS branch
1348 * prediction isolation protections, RSB still needs to be cleared
1349 * because of #2. Note that SMEP provides no protection here, unlike
1350 * user-space-poisoned RSB entries.
1352 * eIBRS should protect against RSB poisoning, but if the EIBRS_PBRSB
1353 * bug is present then a LITE version of RSB protection is required,
1354 * just a single call needs to retire before a RET is executed.
1357 case SPECTRE_V2_NONE:
1360 case SPECTRE_V2_EIBRS_LFENCE:
1361 case SPECTRE_V2_EIBRS:
1362 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
1363 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT_LITE);
1364 pr_info("Spectre v2 / PBRSB-eIBRS: Retire a single CALL on VMEXIT\n");
1368 case SPECTRE_V2_EIBRS_RETPOLINE:
1369 case SPECTRE_V2_RETPOLINE:
1370 case SPECTRE_V2_LFENCE:
1371 case SPECTRE_V2_IBRS:
1372 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT);
1373 pr_info("Spectre v2 / SpectreRSB : Filling RSB on VMEXIT\n");
1377 pr_warn_once("Unknown Spectre v2 mode, disabling RSB mitigation at VM exit");
1381 static void __init spectre_v2_select_mitigation(void)
1383 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
1384 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
1387 * If the CPU is not affected and the command line mode is NONE or AUTO
1388 * then nothing to do.
1390 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
1391 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
1395 case SPECTRE_V2_CMD_NONE:
1398 case SPECTRE_V2_CMD_FORCE:
1399 case SPECTRE_V2_CMD_AUTO:
1400 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1401 mode = SPECTRE_V2_EIBRS;
1405 if (IS_ENABLED(CONFIG_CPU_IBRS_ENTRY) &&
1406 boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1407 retbleed_cmd != RETBLEED_CMD_OFF &&
1408 retbleed_cmd != RETBLEED_CMD_STUFF &&
1409 boot_cpu_has(X86_FEATURE_IBRS) &&
1410 boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
1411 mode = SPECTRE_V2_IBRS;
1415 mode = spectre_v2_select_retpoline();
1418 case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
1419 pr_err(SPECTRE_V2_LFENCE_MSG);
1420 mode = SPECTRE_V2_LFENCE;
1423 case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
1424 mode = SPECTRE_V2_RETPOLINE;
1427 case SPECTRE_V2_CMD_RETPOLINE:
1428 mode = spectre_v2_select_retpoline();
1431 case SPECTRE_V2_CMD_IBRS:
1432 mode = SPECTRE_V2_IBRS;
1435 case SPECTRE_V2_CMD_EIBRS:
1436 mode = SPECTRE_V2_EIBRS;
1439 case SPECTRE_V2_CMD_EIBRS_LFENCE:
1440 mode = SPECTRE_V2_EIBRS_LFENCE;
1443 case SPECTRE_V2_CMD_EIBRS_RETPOLINE:
1444 mode = SPECTRE_V2_EIBRS_RETPOLINE;
1448 if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
1449 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1451 if (spectre_v2_in_ibrs_mode(mode)) {
1452 if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) {
1453 msr_set_bit(MSR_EFER, _EFER_AUTOIBRS);
1455 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
1456 update_spec_ctrl(x86_spec_ctrl_base);
1461 case SPECTRE_V2_NONE:
1462 case SPECTRE_V2_EIBRS:
1465 case SPECTRE_V2_IBRS:
1466 setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS);
1467 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED))
1468 pr_warn(SPECTRE_V2_IBRS_PERF_MSG);
1471 case SPECTRE_V2_LFENCE:
1472 case SPECTRE_V2_EIBRS_LFENCE:
1473 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);
1476 case SPECTRE_V2_RETPOLINE:
1477 case SPECTRE_V2_EIBRS_RETPOLINE:
1478 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
1483 * Disable alternate RSB predictions in kernel when indirect CALLs and
1484 * JMPs gets protection against BHI and Intramode-BTI, but RET
1485 * prediction from a non-RSB predictor is still a risk.
1487 if (mode == SPECTRE_V2_EIBRS_LFENCE ||
1488 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1489 mode == SPECTRE_V2_RETPOLINE)
1490 spec_ctrl_disable_kernel_rrsba();
1492 spectre_v2_enabled = mode;
1493 pr_info("%s\n", spectre_v2_strings[mode]);
1496 * If Spectre v2 protection has been enabled, fill the RSB during a
1497 * context switch. In general there are two types of RSB attacks
1498 * across context switches, for which the CALLs/RETs may be unbalanced.
1502 * Some Intel parts have "bottomless RSB". When the RSB is empty,
1503 * speculated return targets may come from the branch predictor,
1504 * which could have a user-poisoned BTB or BHB entry.
1506 * AMD has it even worse: *all* returns are speculated from the BTB,
1507 * regardless of the state of the RSB.
1509 * When IBRS or eIBRS is enabled, the "user -> kernel" attack
1510 * scenario is mitigated by the IBRS branch prediction isolation
1511 * properties, so the RSB buffer filling wouldn't be necessary to
1512 * protect against this type of attack.
1514 * The "user -> user" attack scenario is mitigated by RSB filling.
1516 * 2) Poisoned RSB entry
1518 * If the 'next' in-kernel return stack is shorter than 'prev',
1519 * 'next' could be tricked into speculating with a user-poisoned RSB
1522 * The "user -> kernel" attack scenario is mitigated by SMEP and
1525 * The "user -> user" scenario, also known as SpectreBHB, requires
1528 * So to mitigate all cases, unconditionally fill RSB on context
1531 * FIXME: Is this pointless for retbleed-affected AMD?
1533 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
1534 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
1536 spectre_v2_determine_rsb_fill_type_at_vmexit(mode);
1539 * Retpoline protects the kernel, but doesn't protect firmware. IBRS
1540 * and Enhanced IBRS protect firmware too, so enable IBRS around
1541 * firmware calls only when IBRS / Enhanced / Automatic IBRS aren't
1542 * otherwise enabled.
1544 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
1545 * the user might select retpoline on the kernel command line and if
1546 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
1547 * enable IBRS around firmware calls.
1549 if (boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1550 boot_cpu_has(X86_FEATURE_IBPB) &&
1551 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1552 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)) {
1554 if (retbleed_cmd != RETBLEED_CMD_IBPB) {
1555 setup_force_cpu_cap(X86_FEATURE_USE_IBPB_FW);
1556 pr_info("Enabling Speculation Barrier for firmware calls\n");
1559 } else if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) {
1560 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
1561 pr_info("Enabling Restricted Speculation for firmware calls\n");
1564 /* Set up IBPB and STIBP depending on the general spectre V2 command */
1565 spectre_v2_cmd = cmd;
1568 static void update_stibp_msr(void * __unused)
1570 u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP);
1571 update_spec_ctrl(val);
1574 /* Update x86_spec_ctrl_base in case SMT state changed. */
1575 static void update_stibp_strict(void)
1577 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
1579 if (sched_smt_active())
1580 mask |= SPEC_CTRL_STIBP;
1582 if (mask == x86_spec_ctrl_base)
1585 pr_info("Update user space SMT mitigation: STIBP %s\n",
1586 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
1587 x86_spec_ctrl_base = mask;
1588 on_each_cpu(update_stibp_msr, NULL, 1);
1591 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
1592 static void update_indir_branch_cond(void)
1594 if (sched_smt_active())
1595 static_branch_enable(&switch_to_cond_stibp);
1597 static_branch_disable(&switch_to_cond_stibp);
1601 #define pr_fmt(fmt) fmt
1603 /* Update the static key controlling the MDS CPU buffer clear in idle */
1604 static void update_mds_branch_idle(void)
1606 u64 ia32_cap = x86_read_arch_cap_msr();
1609 * Enable the idle clearing if SMT is active on CPUs which are
1610 * affected only by MSBDS and not any other MDS variant.
1612 * The other variants cannot be mitigated when SMT is enabled, so
1613 * clearing the buffers on idle just to prevent the Store Buffer
1614 * repartitioning leak would be a window dressing exercise.
1616 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1619 if (sched_smt_active()) {
1620 static_branch_enable(&mds_idle_clear);
1621 } else if (mmio_mitigation == MMIO_MITIGATION_OFF ||
1622 (ia32_cap & ARCH_CAP_FBSDP_NO)) {
1623 static_branch_disable(&mds_idle_clear);
1627 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1628 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1629 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
1631 void cpu_bugs_smt_update(void)
1633 mutex_lock(&spec_ctrl_mutex);
1635 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1636 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
1637 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1639 switch (spectre_v2_user_stibp) {
1640 case SPECTRE_V2_USER_NONE:
1642 case SPECTRE_V2_USER_STRICT:
1643 case SPECTRE_V2_USER_STRICT_PREFERRED:
1644 update_stibp_strict();
1646 case SPECTRE_V2_USER_PRCTL:
1647 case SPECTRE_V2_USER_SECCOMP:
1648 update_indir_branch_cond();
1652 switch (mds_mitigation) {
1653 case MDS_MITIGATION_FULL:
1654 case MDS_MITIGATION_VMWERV:
1655 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1656 pr_warn_once(MDS_MSG_SMT);
1657 update_mds_branch_idle();
1659 case MDS_MITIGATION_OFF:
1663 switch (taa_mitigation) {
1664 case TAA_MITIGATION_VERW:
1665 case TAA_MITIGATION_UCODE_NEEDED:
1666 if (sched_smt_active())
1667 pr_warn_once(TAA_MSG_SMT);
1669 case TAA_MITIGATION_TSX_DISABLED:
1670 case TAA_MITIGATION_OFF:
1674 switch (mmio_mitigation) {
1675 case MMIO_MITIGATION_VERW:
1676 case MMIO_MITIGATION_UCODE_NEEDED:
1677 if (sched_smt_active())
1678 pr_warn_once(MMIO_MSG_SMT);
1680 case MMIO_MITIGATION_OFF:
1684 mutex_unlock(&spec_ctrl_mutex);
1688 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
1690 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1692 /* The kernel command line selection */
1693 enum ssb_mitigation_cmd {
1694 SPEC_STORE_BYPASS_CMD_NONE,
1695 SPEC_STORE_BYPASS_CMD_AUTO,
1696 SPEC_STORE_BYPASS_CMD_ON,
1697 SPEC_STORE_BYPASS_CMD_PRCTL,
1698 SPEC_STORE_BYPASS_CMD_SECCOMP,
1701 static const char * const ssb_strings[] = {
1702 [SPEC_STORE_BYPASS_NONE] = "Vulnerable",
1703 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
1704 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
1705 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1708 static const struct {
1710 enum ssb_mitigation_cmd cmd;
1711 } ssb_mitigation_options[] __initconst = {
1712 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
1713 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
1714 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
1715 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
1716 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1719 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1721 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1725 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1726 cpu_mitigations_off()) {
1727 return SPEC_STORE_BYPASS_CMD_NONE;
1729 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1732 return SPEC_STORE_BYPASS_CMD_AUTO;
1734 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1735 if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1738 cmd = ssb_mitigation_options[i].cmd;
1742 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1743 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1744 return SPEC_STORE_BYPASS_CMD_AUTO;
1751 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1753 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1754 enum ssb_mitigation_cmd cmd;
1756 if (!boot_cpu_has(X86_FEATURE_SSBD))
1759 cmd = ssb_parse_cmdline();
1760 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1761 (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1762 cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1766 case SPEC_STORE_BYPASS_CMD_SECCOMP:
1768 * Choose prctl+seccomp as the default mode if seccomp is
1771 if (IS_ENABLED(CONFIG_SECCOMP))
1772 mode = SPEC_STORE_BYPASS_SECCOMP;
1774 mode = SPEC_STORE_BYPASS_PRCTL;
1776 case SPEC_STORE_BYPASS_CMD_ON:
1777 mode = SPEC_STORE_BYPASS_DISABLE;
1779 case SPEC_STORE_BYPASS_CMD_AUTO:
1780 case SPEC_STORE_BYPASS_CMD_PRCTL:
1781 mode = SPEC_STORE_BYPASS_PRCTL;
1783 case SPEC_STORE_BYPASS_CMD_NONE:
1788 * We have three CPU feature flags that are in play here:
1789 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1790 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1791 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1793 if (mode == SPEC_STORE_BYPASS_DISABLE) {
1794 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1796 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1797 * use a completely different MSR and bit dependent on family.
1799 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1800 !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1801 x86_amd_ssb_disable();
1803 x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1804 update_spec_ctrl(x86_spec_ctrl_base);
1811 static void ssb_select_mitigation(void)
1813 ssb_mode = __ssb_select_mitigation();
1815 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1816 pr_info("%s\n", ssb_strings[ssb_mode]);
1820 #define pr_fmt(fmt) "Speculation prctl: " fmt
1822 static void task_update_spec_tif(struct task_struct *tsk)
1824 /* Force the update of the real TIF bits */
1825 set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1828 * Immediately update the speculation control MSRs for the current
1829 * task, but for a non-current task delay setting the CPU
1830 * mitigation until it is scheduled next.
1832 * This can only happen for SECCOMP mitigation. For PRCTL it's
1833 * always the current task.
1836 speculation_ctrl_update_current();
1839 static int l1d_flush_prctl_set(struct task_struct *task, unsigned long ctrl)
1842 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
1846 case PR_SPEC_ENABLE:
1847 set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
1849 case PR_SPEC_DISABLE:
1850 clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
1857 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1859 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1860 ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1864 case PR_SPEC_ENABLE:
1865 /* If speculation is force disabled, enable is not allowed */
1866 if (task_spec_ssb_force_disable(task))
1868 task_clear_spec_ssb_disable(task);
1869 task_clear_spec_ssb_noexec(task);
1870 task_update_spec_tif(task);
1872 case PR_SPEC_DISABLE:
1873 task_set_spec_ssb_disable(task);
1874 task_clear_spec_ssb_noexec(task);
1875 task_update_spec_tif(task);
1877 case PR_SPEC_FORCE_DISABLE:
1878 task_set_spec_ssb_disable(task);
1879 task_set_spec_ssb_force_disable(task);
1880 task_clear_spec_ssb_noexec(task);
1881 task_update_spec_tif(task);
1883 case PR_SPEC_DISABLE_NOEXEC:
1884 if (task_spec_ssb_force_disable(task))
1886 task_set_spec_ssb_disable(task);
1887 task_set_spec_ssb_noexec(task);
1888 task_update_spec_tif(task);
1896 static bool is_spec_ib_user_controlled(void)
1898 return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1899 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1900 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1901 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1904 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1907 case PR_SPEC_ENABLE:
1908 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1909 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1913 * With strict mode for both IBPB and STIBP, the instruction
1914 * code paths avoid checking this task flag and instead,
1915 * unconditionally run the instruction. However, STIBP and IBPB
1916 * are independent and either can be set to conditionally
1917 * enabled regardless of the mode of the other.
1919 * If either is set to conditional, allow the task flag to be
1920 * updated, unless it was force-disabled by a previous prctl
1921 * call. Currently, this is possible on an AMD CPU which has the
1922 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1923 * kernel is booted with 'spectre_v2_user=seccomp', then
1924 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1925 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1927 if (!is_spec_ib_user_controlled() ||
1928 task_spec_ib_force_disable(task))
1931 task_clear_spec_ib_disable(task);
1932 task_update_spec_tif(task);
1934 case PR_SPEC_DISABLE:
1935 case PR_SPEC_FORCE_DISABLE:
1937 * Indirect branch speculation is always allowed when
1938 * mitigation is force disabled.
1940 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1941 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1944 if (!is_spec_ib_user_controlled())
1947 task_set_spec_ib_disable(task);
1948 if (ctrl == PR_SPEC_FORCE_DISABLE)
1949 task_set_spec_ib_force_disable(task);
1950 task_update_spec_tif(task);
1951 if (task == current)
1952 indirect_branch_prediction_barrier();
1960 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1964 case PR_SPEC_STORE_BYPASS:
1965 return ssb_prctl_set(task, ctrl);
1966 case PR_SPEC_INDIRECT_BRANCH:
1967 return ib_prctl_set(task, ctrl);
1968 case PR_SPEC_L1D_FLUSH:
1969 return l1d_flush_prctl_set(task, ctrl);
1975 #ifdef CONFIG_SECCOMP
1976 void arch_seccomp_spec_mitigate(struct task_struct *task)
1978 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1979 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1980 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1981 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1982 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1986 static int l1d_flush_prctl_get(struct task_struct *task)
1988 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
1989 return PR_SPEC_FORCE_DISABLE;
1991 if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH))
1992 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1994 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1997 static int ssb_prctl_get(struct task_struct *task)
2000 case SPEC_STORE_BYPASS_DISABLE:
2001 return PR_SPEC_DISABLE;
2002 case SPEC_STORE_BYPASS_SECCOMP:
2003 case SPEC_STORE_BYPASS_PRCTL:
2004 if (task_spec_ssb_force_disable(task))
2005 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
2006 if (task_spec_ssb_noexec(task))
2007 return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC;
2008 if (task_spec_ssb_disable(task))
2009 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
2010 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
2012 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
2013 return PR_SPEC_ENABLE;
2014 return PR_SPEC_NOT_AFFECTED;
2018 static int ib_prctl_get(struct task_struct *task)
2020 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
2021 return PR_SPEC_NOT_AFFECTED;
2023 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
2024 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
2025 return PR_SPEC_ENABLE;
2026 else if (is_spec_ib_user_controlled()) {
2027 if (task_spec_ib_force_disable(task))
2028 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
2029 if (task_spec_ib_disable(task))
2030 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
2031 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
2032 } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
2033 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
2034 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
2035 return PR_SPEC_DISABLE;
2037 return PR_SPEC_NOT_AFFECTED;
2040 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
2043 case PR_SPEC_STORE_BYPASS:
2044 return ssb_prctl_get(task);
2045 case PR_SPEC_INDIRECT_BRANCH:
2046 return ib_prctl_get(task);
2047 case PR_SPEC_L1D_FLUSH:
2048 return l1d_flush_prctl_get(task);
2054 void x86_spec_ctrl_setup_ap(void)
2056 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
2057 update_spec_ctrl(x86_spec_ctrl_base);
2059 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
2060 x86_amd_ssb_disable();
2063 bool itlb_multihit_kvm_mitigation;
2064 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
2067 #define pr_fmt(fmt) "L1TF: " fmt
2069 /* Default mitigation for L1TF-affected CPUs */
2070 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
2071 #if IS_ENABLED(CONFIG_KVM_INTEL)
2072 EXPORT_SYMBOL_GPL(l1tf_mitigation);
2074 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
2075 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
2078 * These CPUs all support 44bits physical address space internally in the
2079 * cache but CPUID can report a smaller number of physical address bits.
2081 * The L1TF mitigation uses the top most address bit for the inversion of
2082 * non present PTEs. When the installed memory reaches into the top most
2083 * address bit due to memory holes, which has been observed on machines
2084 * which report 36bits physical address bits and have 32G RAM installed,
2085 * then the mitigation range check in l1tf_select_mitigation() triggers.
2086 * This is a false positive because the mitigation is still possible due to
2087 * the fact that the cache uses 44bit internally. Use the cache bits
2088 * instead of the reported physical bits and adjust them on the affected
2089 * machines to 44bit if the reported bits are less than 44.
2091 static void override_cache_bits(struct cpuinfo_x86 *c)
2096 switch (c->x86_model) {
2097 case INTEL_FAM6_NEHALEM:
2098 case INTEL_FAM6_WESTMERE:
2099 case INTEL_FAM6_SANDYBRIDGE:
2100 case INTEL_FAM6_IVYBRIDGE:
2101 case INTEL_FAM6_HASWELL:
2102 case INTEL_FAM6_HASWELL_L:
2103 case INTEL_FAM6_HASWELL_G:
2104 case INTEL_FAM6_BROADWELL:
2105 case INTEL_FAM6_BROADWELL_G:
2106 case INTEL_FAM6_SKYLAKE_L:
2107 case INTEL_FAM6_SKYLAKE:
2108 case INTEL_FAM6_KABYLAKE_L:
2109 case INTEL_FAM6_KABYLAKE:
2110 if (c->x86_cache_bits < 44)
2111 c->x86_cache_bits = 44;
2116 static void __init l1tf_select_mitigation(void)
2120 if (!boot_cpu_has_bug(X86_BUG_L1TF))
2123 if (cpu_mitigations_off())
2124 l1tf_mitigation = L1TF_MITIGATION_OFF;
2125 else if (cpu_mitigations_auto_nosmt())
2126 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2128 override_cache_bits(&boot_cpu_data);
2130 switch (l1tf_mitigation) {
2131 case L1TF_MITIGATION_OFF:
2132 case L1TF_MITIGATION_FLUSH_NOWARN:
2133 case L1TF_MITIGATION_FLUSH:
2135 case L1TF_MITIGATION_FLUSH_NOSMT:
2136 case L1TF_MITIGATION_FULL:
2137 cpu_smt_disable(false);
2139 case L1TF_MITIGATION_FULL_FORCE:
2140 cpu_smt_disable(true);
2144 #if CONFIG_PGTABLE_LEVELS == 2
2145 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
2149 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
2150 if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
2151 e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
2152 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
2153 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
2155 pr_info("However, doing so will make a part of your RAM unusable.\n");
2156 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
2160 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
2163 static int __init l1tf_cmdline(char *str)
2165 if (!boot_cpu_has_bug(X86_BUG_L1TF))
2171 if (!strcmp(str, "off"))
2172 l1tf_mitigation = L1TF_MITIGATION_OFF;
2173 else if (!strcmp(str, "flush,nowarn"))
2174 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
2175 else if (!strcmp(str, "flush"))
2176 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
2177 else if (!strcmp(str, "flush,nosmt"))
2178 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2179 else if (!strcmp(str, "full"))
2180 l1tf_mitigation = L1TF_MITIGATION_FULL;
2181 else if (!strcmp(str, "full,force"))
2182 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
2186 early_param("l1tf", l1tf_cmdline);
2189 #define pr_fmt(fmt) fmt
2193 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
2195 #if IS_ENABLED(CONFIG_KVM_INTEL)
2196 static const char * const l1tf_vmx_states[] = {
2197 [VMENTER_L1D_FLUSH_AUTO] = "auto",
2198 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable",
2199 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes",
2200 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes",
2201 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled",
2202 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary"
2205 static ssize_t l1tf_show_state(char *buf)
2207 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
2208 return sysfs_emit(buf, "%s\n", L1TF_DEFAULT_MSG);
2210 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
2211 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
2212 sched_smt_active())) {
2213 return sysfs_emit(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
2214 l1tf_vmx_states[l1tf_vmx_mitigation]);
2217 return sysfs_emit(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
2218 l1tf_vmx_states[l1tf_vmx_mitigation],
2219 sched_smt_active() ? "vulnerable" : "disabled");
2222 static ssize_t itlb_multihit_show_state(char *buf)
2224 if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2225 !boot_cpu_has(X86_FEATURE_VMX))
2226 return sysfs_emit(buf, "KVM: Mitigation: VMX unsupported\n");
2227 else if (!(cr4_read_shadow() & X86_CR4_VMXE))
2228 return sysfs_emit(buf, "KVM: Mitigation: VMX disabled\n");
2229 else if (itlb_multihit_kvm_mitigation)
2230 return sysfs_emit(buf, "KVM: Mitigation: Split huge pages\n");
2232 return sysfs_emit(buf, "KVM: Vulnerable\n");
2235 static ssize_t l1tf_show_state(char *buf)
2237 return sysfs_emit(buf, "%s\n", L1TF_DEFAULT_MSG);
2240 static ssize_t itlb_multihit_show_state(char *buf)
2242 return sysfs_emit(buf, "Processor vulnerable\n");
2246 static ssize_t mds_show_state(char *buf)
2248 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2249 return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2250 mds_strings[mds_mitigation]);
2253 if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
2254 return sysfs_emit(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2255 (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
2256 sched_smt_active() ? "mitigated" : "disabled"));
2259 return sysfs_emit(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2260 sched_smt_active() ? "vulnerable" : "disabled");
2263 static ssize_t tsx_async_abort_show_state(char *buf)
2265 if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
2266 (taa_mitigation == TAA_MITIGATION_OFF))
2267 return sysfs_emit(buf, "%s\n", taa_strings[taa_mitigation]);
2269 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2270 return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2271 taa_strings[taa_mitigation]);
2274 return sysfs_emit(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
2275 sched_smt_active() ? "vulnerable" : "disabled");
2278 static ssize_t mmio_stale_data_show_state(char *buf)
2280 if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2281 return sysfs_emit(buf, "Unknown: No mitigations\n");
2283 if (mmio_mitigation == MMIO_MITIGATION_OFF)
2284 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
2286 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2287 return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2288 mmio_strings[mmio_mitigation]);
2291 return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation],
2292 sched_smt_active() ? "vulnerable" : "disabled");
2295 static char *stibp_state(void)
2297 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled))
2300 switch (spectre_v2_user_stibp) {
2301 case SPECTRE_V2_USER_NONE:
2302 return ", STIBP: disabled";
2303 case SPECTRE_V2_USER_STRICT:
2304 return ", STIBP: forced";
2305 case SPECTRE_V2_USER_STRICT_PREFERRED:
2306 return ", STIBP: always-on";
2307 case SPECTRE_V2_USER_PRCTL:
2308 case SPECTRE_V2_USER_SECCOMP:
2309 if (static_key_enabled(&switch_to_cond_stibp))
2310 return ", STIBP: conditional";
2315 static char *ibpb_state(void)
2317 if (boot_cpu_has(X86_FEATURE_IBPB)) {
2318 if (static_key_enabled(&switch_mm_always_ibpb))
2319 return ", IBPB: always-on";
2320 if (static_key_enabled(&switch_mm_cond_ibpb))
2321 return ", IBPB: conditional";
2322 return ", IBPB: disabled";
2327 static char *pbrsb_eibrs_state(void)
2329 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
2330 if (boot_cpu_has(X86_FEATURE_RSB_VMEXIT_LITE) ||
2331 boot_cpu_has(X86_FEATURE_RSB_VMEXIT))
2332 return ", PBRSB-eIBRS: SW sequence";
2334 return ", PBRSB-eIBRS: Vulnerable";
2336 return ", PBRSB-eIBRS: Not affected";
2340 static ssize_t spectre_v2_show_state(char *buf)
2342 if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
2343 return sysfs_emit(buf, "Vulnerable: LFENCE\n");
2345 if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
2346 return sysfs_emit(buf, "Vulnerable: eIBRS with unprivileged eBPF\n");
2348 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
2349 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
2350 return sysfs_emit(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
2352 return sysfs_emit(buf, "%s%s%s%s%s%s%s\n",
2353 spectre_v2_strings[spectre_v2_enabled],
2355 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
2357 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
2358 pbrsb_eibrs_state(),
2359 spectre_v2_module_string());
2362 static ssize_t srbds_show_state(char *buf)
2364 return sysfs_emit(buf, "%s\n", srbds_strings[srbds_mitigation]);
2367 static ssize_t retbleed_show_state(char *buf)
2369 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
2370 retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
2371 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
2372 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
2373 return sysfs_emit(buf, "Vulnerable: untrained return thunk / IBPB on non-AMD based uarch\n");
2375 return sysfs_emit(buf, "%s; SMT %s\n", retbleed_strings[retbleed_mitigation],
2376 !sched_smt_active() ? "disabled" :
2377 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
2378 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ?
2379 "enabled with STIBP protection" : "vulnerable");
2382 return sysfs_emit(buf, "%s\n", retbleed_strings[retbleed_mitigation]);
2385 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
2386 char *buf, unsigned int bug)
2388 if (!boot_cpu_has_bug(bug))
2389 return sysfs_emit(buf, "Not affected\n");
2392 case X86_BUG_CPU_MELTDOWN:
2393 if (boot_cpu_has(X86_FEATURE_PTI))
2394 return sysfs_emit(buf, "Mitigation: PTI\n");
2396 if (hypervisor_is_type(X86_HYPER_XEN_PV))
2397 return sysfs_emit(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
2401 case X86_BUG_SPECTRE_V1:
2402 return sysfs_emit(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
2404 case X86_BUG_SPECTRE_V2:
2405 return spectre_v2_show_state(buf);
2407 case X86_BUG_SPEC_STORE_BYPASS:
2408 return sysfs_emit(buf, "%s\n", ssb_strings[ssb_mode]);
2411 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
2412 return l1tf_show_state(buf);
2416 return mds_show_state(buf);
2419 return tsx_async_abort_show_state(buf);
2421 case X86_BUG_ITLB_MULTIHIT:
2422 return itlb_multihit_show_state(buf);
2425 return srbds_show_state(buf);
2427 case X86_BUG_MMIO_STALE_DATA:
2428 case X86_BUG_MMIO_UNKNOWN:
2429 return mmio_stale_data_show_state(buf);
2431 case X86_BUG_RETBLEED:
2432 return retbleed_show_state(buf);
2438 return sysfs_emit(buf, "Vulnerable\n");
2441 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
2443 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
2446 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
2448 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
2451 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
2453 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
2456 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
2458 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
2461 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
2463 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
2466 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
2468 return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
2471 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
2473 return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
2476 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
2478 return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
2481 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
2483 return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
2486 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
2488 if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2489 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN);
2491 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
2494 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf)
2496 return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED);