1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
18 #include <linux/pgtable.h>
19 #include <linux/bpf.h>
21 #include <asm/spec-ctrl.h>
22 #include <asm/cmdline.h>
24 #include <asm/processor.h>
25 #include <asm/processor-flags.h>
26 #include <asm/fpu/api.h>
29 #include <asm/paravirt.h>
30 #include <asm/alternative.h>
31 #include <asm/set_memory.h>
32 #include <asm/intel-family.h>
33 #include <asm/e820/api.h>
34 #include <asm/hypervisor.h>
35 #include <asm/tlbflush.h>
39 static void __init spectre_v1_select_mitigation(void);
40 static void __init spectre_v2_select_mitigation(void);
41 static void __init retbleed_select_mitigation(void);
42 static void __init spectre_v2_user_select_mitigation(void);
43 static void __init ssb_select_mitigation(void);
44 static void __init l1tf_select_mitigation(void);
45 static void __init mds_select_mitigation(void);
46 static void __init md_clear_update_mitigation(void);
47 static void __init md_clear_select_mitigation(void);
48 static void __init taa_select_mitigation(void);
49 static void __init mmio_select_mitigation(void);
50 static void __init srbds_select_mitigation(void);
51 static void __init l1d_flush_select_mitigation(void);
53 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
54 u64 x86_spec_ctrl_base;
55 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
57 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
58 DEFINE_PER_CPU(u64, x86_spec_ctrl_current);
59 EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);
61 static DEFINE_MUTEX(spec_ctrl_mutex);
64 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ
65 * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
67 void write_spec_ctrl_current(u64 val, bool force)
69 if (this_cpu_read(x86_spec_ctrl_current) == val)
72 this_cpu_write(x86_spec_ctrl_current, val);
75 * When KERNEL_IBRS this MSR is written on return-to-user, unless
76 * forced the update can be delayed until that time.
78 if (force || !cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
79 wrmsrl(MSR_IA32_SPEC_CTRL, val);
82 u64 spec_ctrl_current(void)
84 return this_cpu_read(x86_spec_ctrl_current);
86 EXPORT_SYMBOL_GPL(spec_ctrl_current);
89 * AMD specific MSR info for Speculative Store Bypass control.
90 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
92 u64 __ro_after_init x86_amd_ls_cfg_base;
93 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
95 /* Control conditional STIBP in switch_to() */
96 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
97 /* Control conditional IBPB in switch_mm() */
98 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
99 /* Control unconditional IBPB in switch_mm() */
100 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
102 /* Control MDS CPU buffer clear before returning to user space */
103 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
104 EXPORT_SYMBOL_GPL(mds_user_clear);
105 /* Control MDS CPU buffer clear before idling (halt, mwait) */
106 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
107 EXPORT_SYMBOL_GPL(mds_idle_clear);
110 * Controls whether l1d flush based mitigations are enabled,
111 * based on hw features and admin setting via boot parameter
114 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
116 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
117 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear);
118 EXPORT_SYMBOL_GPL(mmio_stale_data_clear);
120 void __init check_bugs(void)
125 * identify_boot_cpu() initialized SMT support information, let the
128 cpu_smt_check_topology();
130 if (!IS_ENABLED(CONFIG_SMP)) {
132 print_cpu_info(&boot_cpu_data);
136 * Read the SPEC_CTRL MSR to account for reserved bits which may
137 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
138 * init code as it is not enumerated and depends on the family.
140 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
141 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
143 /* Select the proper CPU mitigations before patching alternatives: */
144 spectre_v1_select_mitigation();
145 spectre_v2_select_mitigation();
147 * retbleed_select_mitigation() relies on the state set by
148 * spectre_v2_select_mitigation(); specifically it wants to know about
151 retbleed_select_mitigation();
153 * spectre_v2_user_select_mitigation() relies on the state set by
154 * retbleed_select_mitigation(); specifically the STIBP selection is
155 * forced for UNRET or IBPB.
157 spectre_v2_user_select_mitigation();
158 ssb_select_mitigation();
159 l1tf_select_mitigation();
160 md_clear_select_mitigation();
161 srbds_select_mitigation();
162 l1d_flush_select_mitigation();
168 * Check whether we are able to run this kernel safely on SMP.
170 * - i386 is no longer supported.
171 * - In order to run on anything without a TSC, we need to be
172 * compiled for a i486.
174 if (boot_cpu_data.x86 < 4)
175 panic("Kernel requires i486+ for 'invlpg' and other features");
177 init_utsname()->machine[1] =
178 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
179 alternative_instructions();
181 fpu__init_check_bugs();
182 #else /* CONFIG_X86_64 */
183 alternative_instructions();
186 * Make sure the first 2MB area is not mapped by huge pages
187 * There are typically fixed size MTRRs in there and overlapping
188 * MTRRs into large pages causes slow downs.
190 * Right now we don't do that with gbpages because there seems
191 * very little benefit for that case.
194 set_memory_4k((unsigned long)__va(0), 1);
199 * NOTE: This function is *only* called for SVM. VMX spec_ctrl handling is
203 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
205 u64 msrval, guestval = guest_spec_ctrl, hostval = spec_ctrl_current();
206 struct thread_info *ti = current_thread_info();
208 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
209 if (hostval != guestval) {
210 msrval = setguest ? guestval : hostval;
211 wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
216 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
217 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
219 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
220 !static_cpu_has(X86_FEATURE_VIRT_SSBD))
224 * If the host has SSBD mitigation enabled, force it in the host's
225 * virtual MSR value. If its not permanently enabled, evaluate
226 * current's TIF_SSBD thread flag.
228 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
229 hostval = SPEC_CTRL_SSBD;
231 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
233 /* Sanitize the guest value */
234 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
236 if (hostval != guestval) {
239 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
240 ssbd_spec_ctrl_to_tif(hostval);
242 speculation_ctrl_update(tif);
245 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
247 static void x86_amd_ssb_disable(void)
249 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
251 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
252 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
253 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
254 wrmsrl(MSR_AMD64_LS_CFG, msrval);
258 #define pr_fmt(fmt) "MDS: " fmt
260 /* Default mitigation for MDS-affected CPUs */
261 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
262 static bool mds_nosmt __ro_after_init = false;
264 static const char * const mds_strings[] = {
265 [MDS_MITIGATION_OFF] = "Vulnerable",
266 [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers",
267 [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
270 static void __init mds_select_mitigation(void)
272 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
273 mds_mitigation = MDS_MITIGATION_OFF;
277 if (mds_mitigation == MDS_MITIGATION_FULL) {
278 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
279 mds_mitigation = MDS_MITIGATION_VMWERV;
281 static_branch_enable(&mds_user_clear);
283 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
284 (mds_nosmt || cpu_mitigations_auto_nosmt()))
285 cpu_smt_disable(false);
289 static int __init mds_cmdline(char *str)
291 if (!boot_cpu_has_bug(X86_BUG_MDS))
297 if (!strcmp(str, "off"))
298 mds_mitigation = MDS_MITIGATION_OFF;
299 else if (!strcmp(str, "full"))
300 mds_mitigation = MDS_MITIGATION_FULL;
301 else if (!strcmp(str, "full,nosmt")) {
302 mds_mitigation = MDS_MITIGATION_FULL;
308 early_param("mds", mds_cmdline);
311 #define pr_fmt(fmt) "TAA: " fmt
313 enum taa_mitigations {
315 TAA_MITIGATION_UCODE_NEEDED,
317 TAA_MITIGATION_TSX_DISABLED,
320 /* Default mitigation for TAA-affected CPUs */
321 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
322 static bool taa_nosmt __ro_after_init;
324 static const char * const taa_strings[] = {
325 [TAA_MITIGATION_OFF] = "Vulnerable",
326 [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
327 [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
328 [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled",
331 static void __init taa_select_mitigation(void)
335 if (!boot_cpu_has_bug(X86_BUG_TAA)) {
336 taa_mitigation = TAA_MITIGATION_OFF;
340 /* TSX previously disabled by tsx=off */
341 if (!boot_cpu_has(X86_FEATURE_RTM)) {
342 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
346 if (cpu_mitigations_off()) {
347 taa_mitigation = TAA_MITIGATION_OFF;
352 * TAA mitigation via VERW is turned off if both
353 * tsx_async_abort=off and mds=off are specified.
355 if (taa_mitigation == TAA_MITIGATION_OFF &&
356 mds_mitigation == MDS_MITIGATION_OFF)
359 if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
360 taa_mitigation = TAA_MITIGATION_VERW;
362 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
365 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
366 * A microcode update fixes this behavior to clear CPU buffers. It also
367 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
368 * ARCH_CAP_TSX_CTRL_MSR bit.
370 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
371 * update is required.
373 ia32_cap = x86_read_arch_cap_msr();
374 if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
375 !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
376 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
379 * TSX is enabled, select alternate mitigation for TAA which is
380 * the same as MDS. Enable MDS static branch to clear CPU buffers.
382 * For guests that can't determine whether the correct microcode is
383 * present on host, enable the mitigation for UCODE_NEEDED as well.
385 static_branch_enable(&mds_user_clear);
387 if (taa_nosmt || cpu_mitigations_auto_nosmt())
388 cpu_smt_disable(false);
391 static int __init tsx_async_abort_parse_cmdline(char *str)
393 if (!boot_cpu_has_bug(X86_BUG_TAA))
399 if (!strcmp(str, "off")) {
400 taa_mitigation = TAA_MITIGATION_OFF;
401 } else if (!strcmp(str, "full")) {
402 taa_mitigation = TAA_MITIGATION_VERW;
403 } else if (!strcmp(str, "full,nosmt")) {
404 taa_mitigation = TAA_MITIGATION_VERW;
410 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
413 #define pr_fmt(fmt) "MMIO Stale Data: " fmt
415 enum mmio_mitigations {
417 MMIO_MITIGATION_UCODE_NEEDED,
418 MMIO_MITIGATION_VERW,
421 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */
422 static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW;
423 static bool mmio_nosmt __ro_after_init = false;
425 static const char * const mmio_strings[] = {
426 [MMIO_MITIGATION_OFF] = "Vulnerable",
427 [MMIO_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
428 [MMIO_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
431 static void __init mmio_select_mitigation(void)
435 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
436 boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) ||
437 cpu_mitigations_off()) {
438 mmio_mitigation = MMIO_MITIGATION_OFF;
442 if (mmio_mitigation == MMIO_MITIGATION_OFF)
445 ia32_cap = x86_read_arch_cap_msr();
448 * Enable CPU buffer clear mitigation for host and VMM, if also affected
449 * by MDS or TAA. Otherwise, enable mitigation for VMM only.
451 if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) &&
452 boot_cpu_has(X86_FEATURE_RTM)))
453 static_branch_enable(&mds_user_clear);
455 static_branch_enable(&mmio_stale_data_clear);
458 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can
459 * be propagated to uncore buffers, clearing the Fill buffers on idle
460 * is required irrespective of SMT state.
462 if (!(ia32_cap & ARCH_CAP_FBSDP_NO))
463 static_branch_enable(&mds_idle_clear);
466 * Check if the system has the right microcode.
468 * CPU Fill buffer clear mitigation is enumerated by either an explicit
469 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
472 if ((ia32_cap & ARCH_CAP_FB_CLEAR) ||
473 (boot_cpu_has(X86_FEATURE_MD_CLEAR) &&
474 boot_cpu_has(X86_FEATURE_FLUSH_L1D) &&
475 !(ia32_cap & ARCH_CAP_MDS_NO)))
476 mmio_mitigation = MMIO_MITIGATION_VERW;
478 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED;
480 if (mmio_nosmt || cpu_mitigations_auto_nosmt())
481 cpu_smt_disable(false);
484 static int __init mmio_stale_data_parse_cmdline(char *str)
486 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
492 if (!strcmp(str, "off")) {
493 mmio_mitigation = MMIO_MITIGATION_OFF;
494 } else if (!strcmp(str, "full")) {
495 mmio_mitigation = MMIO_MITIGATION_VERW;
496 } else if (!strcmp(str, "full,nosmt")) {
497 mmio_mitigation = MMIO_MITIGATION_VERW;
503 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline);
506 #define pr_fmt(fmt) "" fmt
508 static void __init md_clear_update_mitigation(void)
510 if (cpu_mitigations_off())
513 if (!static_key_enabled(&mds_user_clear))
517 * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data
518 * mitigation, if necessary.
520 if (mds_mitigation == MDS_MITIGATION_OFF &&
521 boot_cpu_has_bug(X86_BUG_MDS)) {
522 mds_mitigation = MDS_MITIGATION_FULL;
523 mds_select_mitigation();
525 if (taa_mitigation == TAA_MITIGATION_OFF &&
526 boot_cpu_has_bug(X86_BUG_TAA)) {
527 taa_mitigation = TAA_MITIGATION_VERW;
528 taa_select_mitigation();
530 if (mmio_mitigation == MMIO_MITIGATION_OFF &&
531 boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) {
532 mmio_mitigation = MMIO_MITIGATION_VERW;
533 mmio_select_mitigation();
536 if (boot_cpu_has_bug(X86_BUG_MDS))
537 pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
538 if (boot_cpu_has_bug(X86_BUG_TAA))
539 pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
540 if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
541 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
542 else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
543 pr_info("MMIO Stale Data: Unknown: No mitigations\n");
546 static void __init md_clear_select_mitigation(void)
548 mds_select_mitigation();
549 taa_select_mitigation();
550 mmio_select_mitigation();
553 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
554 * and print their mitigation after MDS, TAA and MMIO Stale Data
555 * mitigation selection is done.
557 md_clear_update_mitigation();
561 #define pr_fmt(fmt) "SRBDS: " fmt
563 enum srbds_mitigations {
564 SRBDS_MITIGATION_OFF,
565 SRBDS_MITIGATION_UCODE_NEEDED,
566 SRBDS_MITIGATION_FULL,
567 SRBDS_MITIGATION_TSX_OFF,
568 SRBDS_MITIGATION_HYPERVISOR,
571 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
573 static const char * const srbds_strings[] = {
574 [SRBDS_MITIGATION_OFF] = "Vulnerable",
575 [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
576 [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode",
577 [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled",
578 [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status",
581 static bool srbds_off;
583 void update_srbds_msr(void)
587 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
590 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
593 if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
597 * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX
598 * being disabled and it hasn't received the SRBDS MSR microcode.
600 if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
603 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
605 switch (srbds_mitigation) {
606 case SRBDS_MITIGATION_OFF:
607 case SRBDS_MITIGATION_TSX_OFF:
608 mcu_ctrl |= RNGDS_MITG_DIS;
610 case SRBDS_MITIGATION_FULL:
611 mcu_ctrl &= ~RNGDS_MITG_DIS;
617 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
620 static void __init srbds_select_mitigation(void)
624 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
628 * Check to see if this is one of the MDS_NO systems supporting TSX that
629 * are only exposed to SRBDS when TSX is enabled or when CPU is affected
630 * by Processor MMIO Stale Data vulnerability.
632 ia32_cap = x86_read_arch_cap_msr();
633 if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
634 !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
635 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
636 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
637 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
638 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
639 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
640 else if (cpu_mitigations_off() || srbds_off)
641 srbds_mitigation = SRBDS_MITIGATION_OFF;
644 pr_info("%s\n", srbds_strings[srbds_mitigation]);
647 static int __init srbds_parse_cmdline(char *str)
652 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
655 srbds_off = !strcmp(str, "off");
658 early_param("srbds", srbds_parse_cmdline);
661 #define pr_fmt(fmt) "L1D Flush : " fmt
663 enum l1d_flush_mitigations {
668 static enum l1d_flush_mitigations l1d_flush_mitigation __initdata = L1D_FLUSH_OFF;
670 static void __init l1d_flush_select_mitigation(void)
672 if (!l1d_flush_mitigation || !boot_cpu_has(X86_FEATURE_FLUSH_L1D))
675 static_branch_enable(&switch_mm_cond_l1d_flush);
676 pr_info("Conditional flush on switch_mm() enabled\n");
679 static int __init l1d_flush_parse_cmdline(char *str)
681 if (!strcmp(str, "on"))
682 l1d_flush_mitigation = L1D_FLUSH_ON;
686 early_param("l1d_flush", l1d_flush_parse_cmdline);
689 #define pr_fmt(fmt) "Spectre V1 : " fmt
691 enum spectre_v1_mitigation {
692 SPECTRE_V1_MITIGATION_NONE,
693 SPECTRE_V1_MITIGATION_AUTO,
696 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
697 SPECTRE_V1_MITIGATION_AUTO;
699 static const char * const spectre_v1_strings[] = {
700 [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
701 [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
705 * Does SMAP provide full mitigation against speculative kernel access to
708 static bool smap_works_speculatively(void)
710 if (!boot_cpu_has(X86_FEATURE_SMAP))
714 * On CPUs which are vulnerable to Meltdown, SMAP does not
715 * prevent speculative access to user data in the L1 cache.
716 * Consider SMAP to be non-functional as a mitigation on these
719 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
725 static void __init spectre_v1_select_mitigation(void)
727 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
728 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
732 if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
734 * With Spectre v1, a user can speculatively control either
735 * path of a conditional swapgs with a user-controlled GS
736 * value. The mitigation is to add lfences to both code paths.
738 * If FSGSBASE is enabled, the user can put a kernel address in
739 * GS, in which case SMAP provides no protection.
741 * If FSGSBASE is disabled, the user can only put a user space
742 * address in GS. That makes an attack harder, but still
743 * possible if there's no SMAP protection.
745 if (boot_cpu_has(X86_FEATURE_FSGSBASE) ||
746 !smap_works_speculatively()) {
748 * Mitigation can be provided from SWAPGS itself or
749 * PTI as the CR3 write in the Meltdown mitigation
752 * If neither is there, mitigate with an LFENCE to
753 * stop speculation through swapgs.
755 if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
756 !boot_cpu_has(X86_FEATURE_PTI))
757 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
760 * Enable lfences in the kernel entry (non-swapgs)
761 * paths, to prevent user entry from speculatively
764 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
768 pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
771 static int __init nospectre_v1_cmdline(char *str)
773 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
776 early_param("nospectre_v1", nospectre_v1_cmdline);
778 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
782 #define pr_fmt(fmt) "RETBleed: " fmt
784 enum retbleed_mitigation {
785 RETBLEED_MITIGATION_NONE,
786 RETBLEED_MITIGATION_UNRET,
787 RETBLEED_MITIGATION_IBPB,
788 RETBLEED_MITIGATION_IBRS,
789 RETBLEED_MITIGATION_EIBRS,
792 enum retbleed_mitigation_cmd {
799 static const char * const retbleed_strings[] = {
800 [RETBLEED_MITIGATION_NONE] = "Vulnerable",
801 [RETBLEED_MITIGATION_UNRET] = "Mitigation: untrained return thunk",
802 [RETBLEED_MITIGATION_IBPB] = "Mitigation: IBPB",
803 [RETBLEED_MITIGATION_IBRS] = "Mitigation: IBRS",
804 [RETBLEED_MITIGATION_EIBRS] = "Mitigation: Enhanced IBRS",
807 static enum retbleed_mitigation retbleed_mitigation __ro_after_init =
808 RETBLEED_MITIGATION_NONE;
809 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =
812 static int __ro_after_init retbleed_nosmt = false;
814 static int __init retbleed_parse_cmdline(char *str)
820 char *next = strchr(str, ',');
826 if (!strcmp(str, "off")) {
827 retbleed_cmd = RETBLEED_CMD_OFF;
828 } else if (!strcmp(str, "auto")) {
829 retbleed_cmd = RETBLEED_CMD_AUTO;
830 } else if (!strcmp(str, "unret")) {
831 retbleed_cmd = RETBLEED_CMD_UNRET;
832 } else if (!strcmp(str, "ibpb")) {
833 retbleed_cmd = RETBLEED_CMD_IBPB;
834 } else if (!strcmp(str, "nosmt")) {
835 retbleed_nosmt = true;
837 pr_err("Ignoring unknown retbleed option (%s).", str);
845 early_param("retbleed", retbleed_parse_cmdline);
847 #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n"
848 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n"
850 static void __init retbleed_select_mitigation(void)
852 bool mitigate_smt = false;
854 if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off())
857 switch (retbleed_cmd) {
858 case RETBLEED_CMD_OFF:
861 case RETBLEED_CMD_UNRET:
862 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY)) {
863 retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
865 pr_err("WARNING: kernel not compiled with CPU_UNRET_ENTRY.\n");
870 case RETBLEED_CMD_IBPB:
871 if (!boot_cpu_has(X86_FEATURE_IBPB)) {
872 pr_err("WARNING: CPU does not support IBPB.\n");
874 } else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY)) {
875 retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
877 pr_err("WARNING: kernel not compiled with CPU_IBPB_ENTRY.\n");
883 case RETBLEED_CMD_AUTO:
885 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
886 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
887 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY))
888 retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
889 else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY) && boot_cpu_has(X86_FEATURE_IBPB))
890 retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
894 * The Intel mitigation (IBRS or eIBRS) was already selected in
895 * spectre_v2_select_mitigation(). 'retbleed_mitigation' will
896 * be set accordingly below.
902 switch (retbleed_mitigation) {
903 case RETBLEED_MITIGATION_UNRET:
904 setup_force_cpu_cap(X86_FEATURE_RETHUNK);
905 setup_force_cpu_cap(X86_FEATURE_UNRET);
907 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
908 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
909 pr_err(RETBLEED_UNTRAIN_MSG);
914 case RETBLEED_MITIGATION_IBPB:
915 setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB);
923 if (mitigate_smt && !boot_cpu_has(X86_FEATURE_STIBP) &&
924 (retbleed_nosmt || cpu_mitigations_auto_nosmt()))
925 cpu_smt_disable(false);
928 * Let IBRS trump all on Intel without affecting the effects of the
929 * retbleed= cmdline option.
931 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
932 switch (spectre_v2_enabled) {
933 case SPECTRE_V2_IBRS:
934 retbleed_mitigation = RETBLEED_MITIGATION_IBRS;
936 case SPECTRE_V2_EIBRS:
937 case SPECTRE_V2_EIBRS_RETPOLINE:
938 case SPECTRE_V2_EIBRS_LFENCE:
939 retbleed_mitigation = RETBLEED_MITIGATION_EIBRS;
942 pr_err(RETBLEED_INTEL_MSG);
946 pr_info("%s\n", retbleed_strings[retbleed_mitigation]);
950 #define pr_fmt(fmt) "Spectre V2 : " fmt
952 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
953 SPECTRE_V2_USER_NONE;
954 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
955 SPECTRE_V2_USER_NONE;
957 #ifdef CONFIG_RETPOLINE
958 static bool spectre_v2_bad_module;
960 bool retpoline_module_ok(bool has_retpoline)
962 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
965 pr_err("System may be vulnerable to spectre v2\n");
966 spectre_v2_bad_module = true;
970 static inline const char *spectre_v2_module_string(void)
972 return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
975 static inline const char *spectre_v2_module_string(void) { return ""; }
978 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
979 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
980 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
981 #define SPECTRE_V2_IBRS_PERF_MSG "WARNING: IBRS mitigation selected on Enhanced IBRS CPU, this may cause unnecessary performance loss\n"
983 #ifdef CONFIG_BPF_SYSCALL
984 void unpriv_ebpf_notify(int new_state)
989 /* Unprivileged eBPF is enabled */
991 switch (spectre_v2_enabled) {
992 case SPECTRE_V2_EIBRS:
993 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
995 case SPECTRE_V2_EIBRS_LFENCE:
996 if (sched_smt_active())
997 pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1005 static inline bool match_option(const char *arg, int arglen, const char *opt)
1007 int len = strlen(opt);
1009 return len == arglen && !strncmp(arg, opt, len);
1012 /* The kernel command line selection for spectre v2 */
1013 enum spectre_v2_mitigation_cmd {
1014 SPECTRE_V2_CMD_NONE,
1015 SPECTRE_V2_CMD_AUTO,
1016 SPECTRE_V2_CMD_FORCE,
1017 SPECTRE_V2_CMD_RETPOLINE,
1018 SPECTRE_V2_CMD_RETPOLINE_GENERIC,
1019 SPECTRE_V2_CMD_RETPOLINE_LFENCE,
1020 SPECTRE_V2_CMD_EIBRS,
1021 SPECTRE_V2_CMD_EIBRS_RETPOLINE,
1022 SPECTRE_V2_CMD_EIBRS_LFENCE,
1023 SPECTRE_V2_CMD_IBRS,
1026 enum spectre_v2_user_cmd {
1027 SPECTRE_V2_USER_CMD_NONE,
1028 SPECTRE_V2_USER_CMD_AUTO,
1029 SPECTRE_V2_USER_CMD_FORCE,
1030 SPECTRE_V2_USER_CMD_PRCTL,
1031 SPECTRE_V2_USER_CMD_PRCTL_IBPB,
1032 SPECTRE_V2_USER_CMD_SECCOMP,
1033 SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
1036 static const char * const spectre_v2_user_strings[] = {
1037 [SPECTRE_V2_USER_NONE] = "User space: Vulnerable",
1038 [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection",
1039 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection",
1040 [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl",
1041 [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl",
1044 static const struct {
1046 enum spectre_v2_user_cmd cmd;
1048 } v2_user_options[] __initconst = {
1049 { "auto", SPECTRE_V2_USER_CMD_AUTO, false },
1050 { "off", SPECTRE_V2_USER_CMD_NONE, false },
1051 { "on", SPECTRE_V2_USER_CMD_FORCE, true },
1052 { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false },
1053 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false },
1054 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false },
1055 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false },
1058 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
1060 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1061 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
1064 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd;
1066 static enum spectre_v2_user_cmd __init
1067 spectre_v2_parse_user_cmdline(void)
1072 switch (spectre_v2_cmd) {
1073 case SPECTRE_V2_CMD_NONE:
1074 return SPECTRE_V2_USER_CMD_NONE;
1075 case SPECTRE_V2_CMD_FORCE:
1076 return SPECTRE_V2_USER_CMD_FORCE;
1081 ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
1084 return SPECTRE_V2_USER_CMD_AUTO;
1086 for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
1087 if (match_option(arg, ret, v2_user_options[i].option)) {
1088 spec_v2_user_print_cond(v2_user_options[i].option,
1089 v2_user_options[i].secure);
1090 return v2_user_options[i].cmd;
1094 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
1095 return SPECTRE_V2_USER_CMD_AUTO;
1098 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)
1100 return mode == SPECTRE_V2_IBRS ||
1101 mode == SPECTRE_V2_EIBRS ||
1102 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1103 mode == SPECTRE_V2_EIBRS_LFENCE;
1107 spectre_v2_user_select_mitigation(void)
1109 enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
1110 bool smt_possible = IS_ENABLED(CONFIG_SMP);
1111 enum spectre_v2_user_cmd cmd;
1113 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
1116 if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
1117 cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
1118 smt_possible = false;
1120 cmd = spectre_v2_parse_user_cmdline();
1122 case SPECTRE_V2_USER_CMD_NONE:
1124 case SPECTRE_V2_USER_CMD_FORCE:
1125 mode = SPECTRE_V2_USER_STRICT;
1127 case SPECTRE_V2_USER_CMD_AUTO:
1128 case SPECTRE_V2_USER_CMD_PRCTL:
1129 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1130 mode = SPECTRE_V2_USER_PRCTL;
1132 case SPECTRE_V2_USER_CMD_SECCOMP:
1133 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1134 if (IS_ENABLED(CONFIG_SECCOMP))
1135 mode = SPECTRE_V2_USER_SECCOMP;
1137 mode = SPECTRE_V2_USER_PRCTL;
1141 /* Initialize Indirect Branch Prediction Barrier */
1142 if (boot_cpu_has(X86_FEATURE_IBPB)) {
1143 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
1145 spectre_v2_user_ibpb = mode;
1147 case SPECTRE_V2_USER_CMD_FORCE:
1148 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1149 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1150 static_branch_enable(&switch_mm_always_ibpb);
1151 spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
1153 case SPECTRE_V2_USER_CMD_PRCTL:
1154 case SPECTRE_V2_USER_CMD_AUTO:
1155 case SPECTRE_V2_USER_CMD_SECCOMP:
1156 static_branch_enable(&switch_mm_cond_ibpb);
1162 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
1163 static_key_enabled(&switch_mm_always_ibpb) ?
1164 "always-on" : "conditional");
1168 * If no STIBP, IBRS or enhanced IBRS is enabled, or SMT impossible,
1169 * STIBP is not required.
1171 if (!boot_cpu_has(X86_FEATURE_STIBP) ||
1173 spectre_v2_in_ibrs_mode(spectre_v2_enabled))
1177 * At this point, an STIBP mode other than "off" has been set.
1178 * If STIBP support is not being forced, check if STIBP always-on
1181 if (mode != SPECTRE_V2_USER_STRICT &&
1182 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
1183 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1185 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
1186 retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
1187 if (mode != SPECTRE_V2_USER_STRICT &&
1188 mode != SPECTRE_V2_USER_STRICT_PREFERRED)
1189 pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n");
1190 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1193 spectre_v2_user_stibp = mode;
1196 pr_info("%s\n", spectre_v2_user_strings[mode]);
1199 static const char * const spectre_v2_strings[] = {
1200 [SPECTRE_V2_NONE] = "Vulnerable",
1201 [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines",
1202 [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE",
1203 [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced IBRS",
1204 [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced IBRS + LFENCE",
1205 [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced IBRS + Retpolines",
1206 [SPECTRE_V2_IBRS] = "Mitigation: IBRS",
1209 static const struct {
1211 enum spectre_v2_mitigation_cmd cmd;
1213 } mitigation_options[] __initconst = {
1214 { "off", SPECTRE_V2_CMD_NONE, false },
1215 { "on", SPECTRE_V2_CMD_FORCE, true },
1216 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
1217 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
1218 { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
1219 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
1220 { "eibrs", SPECTRE_V2_CMD_EIBRS, false },
1221 { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false },
1222 { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false },
1223 { "auto", SPECTRE_V2_CMD_AUTO, false },
1224 { "ibrs", SPECTRE_V2_CMD_IBRS, false },
1227 static void __init spec_v2_print_cond(const char *reason, bool secure)
1229 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1230 pr_info("%s selected on command line.\n", reason);
1233 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
1235 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
1239 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
1240 cpu_mitigations_off())
1241 return SPECTRE_V2_CMD_NONE;
1243 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
1245 return SPECTRE_V2_CMD_AUTO;
1247 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
1248 if (!match_option(arg, ret, mitigation_options[i].option))
1250 cmd = mitigation_options[i].cmd;
1254 if (i >= ARRAY_SIZE(mitigation_options)) {
1255 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1256 return SPECTRE_V2_CMD_AUTO;
1259 if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
1260 cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1261 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC ||
1262 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1263 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1264 !IS_ENABLED(CONFIG_RETPOLINE)) {
1265 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1266 mitigation_options[i].option);
1267 return SPECTRE_V2_CMD_AUTO;
1270 if ((cmd == SPECTRE_V2_CMD_EIBRS ||
1271 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1272 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1273 !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1274 pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n",
1275 mitigation_options[i].option);
1276 return SPECTRE_V2_CMD_AUTO;
1279 if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1280 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) &&
1281 !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
1282 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
1283 mitigation_options[i].option);
1284 return SPECTRE_V2_CMD_AUTO;
1287 if (cmd == SPECTRE_V2_CMD_IBRS && !IS_ENABLED(CONFIG_CPU_IBRS_ENTRY)) {
1288 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1289 mitigation_options[i].option);
1290 return SPECTRE_V2_CMD_AUTO;
1293 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1294 pr_err("%s selected but not Intel CPU. Switching to AUTO select\n",
1295 mitigation_options[i].option);
1296 return SPECTRE_V2_CMD_AUTO;
1299 if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) {
1300 pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n",
1301 mitigation_options[i].option);
1302 return SPECTRE_V2_CMD_AUTO;
1305 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_XENPV)) {
1306 pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n",
1307 mitigation_options[i].option);
1308 return SPECTRE_V2_CMD_AUTO;
1311 spec_v2_print_cond(mitigation_options[i].option,
1312 mitigation_options[i].secure);
1316 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
1318 if (!IS_ENABLED(CONFIG_RETPOLINE)) {
1319 pr_err("Kernel not compiled with retpoline; no mitigation available!");
1320 return SPECTRE_V2_NONE;
1323 return SPECTRE_V2_RETPOLINE;
1326 /* Disable in-kernel use of non-RSB RET predictors */
1327 static void __init spec_ctrl_disable_kernel_rrsba(void)
1331 if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL))
1334 ia32_cap = x86_read_arch_cap_msr();
1336 if (ia32_cap & ARCH_CAP_RRSBA) {
1337 x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;
1338 write_spec_ctrl_current(x86_spec_ctrl_base, true);
1342 static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)
1345 * Similar to context switches, there are two types of RSB attacks
1350 * 2) Poisoned RSB entry
1352 * When retpoline is enabled, both are mitigated by filling/clearing
1355 * When IBRS is enabled, while #1 would be mitigated by the IBRS branch
1356 * prediction isolation protections, RSB still needs to be cleared
1357 * because of #2. Note that SMEP provides no protection here, unlike
1358 * user-space-poisoned RSB entries.
1360 * eIBRS should protect against RSB poisoning, but if the EIBRS_PBRSB
1361 * bug is present then a LITE version of RSB protection is required,
1362 * just a single call needs to retire before a RET is executed.
1365 case SPECTRE_V2_NONE:
1368 case SPECTRE_V2_EIBRS_LFENCE:
1369 case SPECTRE_V2_EIBRS:
1370 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
1371 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT_LITE);
1372 pr_info("Spectre v2 / PBRSB-eIBRS: Retire a single CALL on VMEXIT\n");
1376 case SPECTRE_V2_EIBRS_RETPOLINE:
1377 case SPECTRE_V2_RETPOLINE:
1378 case SPECTRE_V2_LFENCE:
1379 case SPECTRE_V2_IBRS:
1380 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT);
1381 pr_info("Spectre v2 / SpectreRSB : Filling RSB on VMEXIT\n");
1385 pr_warn_once("Unknown Spectre v2 mode, disabling RSB mitigation at VM exit");
1389 static void __init spectre_v2_select_mitigation(void)
1391 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
1392 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
1395 * If the CPU is not affected and the command line mode is NONE or AUTO
1396 * then nothing to do.
1398 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
1399 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
1403 case SPECTRE_V2_CMD_NONE:
1406 case SPECTRE_V2_CMD_FORCE:
1407 case SPECTRE_V2_CMD_AUTO:
1408 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1409 mode = SPECTRE_V2_EIBRS;
1413 if (IS_ENABLED(CONFIG_CPU_IBRS_ENTRY) &&
1414 boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1415 retbleed_cmd != RETBLEED_CMD_OFF &&
1416 boot_cpu_has(X86_FEATURE_IBRS) &&
1417 boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
1418 mode = SPECTRE_V2_IBRS;
1422 mode = spectre_v2_select_retpoline();
1425 case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
1426 pr_err(SPECTRE_V2_LFENCE_MSG);
1427 mode = SPECTRE_V2_LFENCE;
1430 case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
1431 mode = SPECTRE_V2_RETPOLINE;
1434 case SPECTRE_V2_CMD_RETPOLINE:
1435 mode = spectre_v2_select_retpoline();
1438 case SPECTRE_V2_CMD_IBRS:
1439 mode = SPECTRE_V2_IBRS;
1442 case SPECTRE_V2_CMD_EIBRS:
1443 mode = SPECTRE_V2_EIBRS;
1446 case SPECTRE_V2_CMD_EIBRS_LFENCE:
1447 mode = SPECTRE_V2_EIBRS_LFENCE;
1450 case SPECTRE_V2_CMD_EIBRS_RETPOLINE:
1451 mode = SPECTRE_V2_EIBRS_RETPOLINE;
1455 if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
1456 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1458 if (spectre_v2_in_ibrs_mode(mode)) {
1459 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
1460 write_spec_ctrl_current(x86_spec_ctrl_base, true);
1464 case SPECTRE_V2_NONE:
1465 case SPECTRE_V2_EIBRS:
1468 case SPECTRE_V2_IBRS:
1469 setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS);
1470 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED))
1471 pr_warn(SPECTRE_V2_IBRS_PERF_MSG);
1474 case SPECTRE_V2_LFENCE:
1475 case SPECTRE_V2_EIBRS_LFENCE:
1476 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);
1479 case SPECTRE_V2_RETPOLINE:
1480 case SPECTRE_V2_EIBRS_RETPOLINE:
1481 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
1486 * Disable alternate RSB predictions in kernel when indirect CALLs and
1487 * JMPs gets protection against BHI and Intramode-BTI, but RET
1488 * prediction from a non-RSB predictor is still a risk.
1490 if (mode == SPECTRE_V2_EIBRS_LFENCE ||
1491 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1492 mode == SPECTRE_V2_RETPOLINE)
1493 spec_ctrl_disable_kernel_rrsba();
1495 spectre_v2_enabled = mode;
1496 pr_info("%s\n", spectre_v2_strings[mode]);
1499 * If Spectre v2 protection has been enabled, fill the RSB during a
1500 * context switch. In general there are two types of RSB attacks
1501 * across context switches, for which the CALLs/RETs may be unbalanced.
1505 * Some Intel parts have "bottomless RSB". When the RSB is empty,
1506 * speculated return targets may come from the branch predictor,
1507 * which could have a user-poisoned BTB or BHB entry.
1509 * AMD has it even worse: *all* returns are speculated from the BTB,
1510 * regardless of the state of the RSB.
1512 * When IBRS or eIBRS is enabled, the "user -> kernel" attack
1513 * scenario is mitigated by the IBRS branch prediction isolation
1514 * properties, so the RSB buffer filling wouldn't be necessary to
1515 * protect against this type of attack.
1517 * The "user -> user" attack scenario is mitigated by RSB filling.
1519 * 2) Poisoned RSB entry
1521 * If the 'next' in-kernel return stack is shorter than 'prev',
1522 * 'next' could be tricked into speculating with a user-poisoned RSB
1525 * The "user -> kernel" attack scenario is mitigated by SMEP and
1528 * The "user -> user" scenario, also known as SpectreBHB, requires
1531 * So to mitigate all cases, unconditionally fill RSB on context
1534 * FIXME: Is this pointless for retbleed-affected AMD?
1536 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
1537 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
1539 spectre_v2_determine_rsb_fill_type_at_vmexit(mode);
1542 * Retpoline protects the kernel, but doesn't protect firmware. IBRS
1543 * and Enhanced IBRS protect firmware too, so enable IBRS around
1544 * firmware calls only when IBRS / Enhanced IBRS aren't otherwise
1547 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
1548 * the user might select retpoline on the kernel command line and if
1549 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
1550 * enable IBRS around firmware calls.
1552 if (boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1553 boot_cpu_has(X86_FEATURE_IBPB) &&
1554 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1555 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)) {
1557 if (retbleed_cmd != RETBLEED_CMD_IBPB) {
1558 setup_force_cpu_cap(X86_FEATURE_USE_IBPB_FW);
1559 pr_info("Enabling Speculation Barrier for firmware calls\n");
1562 } else if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) {
1563 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
1564 pr_info("Enabling Restricted Speculation for firmware calls\n");
1567 /* Set up IBPB and STIBP depending on the general spectre V2 command */
1568 spectre_v2_cmd = cmd;
1571 static void update_stibp_msr(void * __unused)
1573 u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP);
1574 write_spec_ctrl_current(val, true);
1577 /* Update x86_spec_ctrl_base in case SMT state changed. */
1578 static void update_stibp_strict(void)
1580 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
1582 if (sched_smt_active())
1583 mask |= SPEC_CTRL_STIBP;
1585 if (mask == x86_spec_ctrl_base)
1588 pr_info("Update user space SMT mitigation: STIBP %s\n",
1589 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
1590 x86_spec_ctrl_base = mask;
1591 on_each_cpu(update_stibp_msr, NULL, 1);
1594 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
1595 static void update_indir_branch_cond(void)
1597 if (sched_smt_active())
1598 static_branch_enable(&switch_to_cond_stibp);
1600 static_branch_disable(&switch_to_cond_stibp);
1604 #define pr_fmt(fmt) fmt
1606 /* Update the static key controlling the MDS CPU buffer clear in idle */
1607 static void update_mds_branch_idle(void)
1609 u64 ia32_cap = x86_read_arch_cap_msr();
1612 * Enable the idle clearing if SMT is active on CPUs which are
1613 * affected only by MSBDS and not any other MDS variant.
1615 * The other variants cannot be mitigated when SMT is enabled, so
1616 * clearing the buffers on idle just to prevent the Store Buffer
1617 * repartitioning leak would be a window dressing exercise.
1619 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1622 if (sched_smt_active()) {
1623 static_branch_enable(&mds_idle_clear);
1624 } else if (mmio_mitigation == MMIO_MITIGATION_OFF ||
1625 (ia32_cap & ARCH_CAP_FBSDP_NO)) {
1626 static_branch_disable(&mds_idle_clear);
1630 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1631 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1632 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
1634 void cpu_bugs_smt_update(void)
1636 mutex_lock(&spec_ctrl_mutex);
1638 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1639 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
1640 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1642 switch (spectre_v2_user_stibp) {
1643 case SPECTRE_V2_USER_NONE:
1645 case SPECTRE_V2_USER_STRICT:
1646 case SPECTRE_V2_USER_STRICT_PREFERRED:
1647 update_stibp_strict();
1649 case SPECTRE_V2_USER_PRCTL:
1650 case SPECTRE_V2_USER_SECCOMP:
1651 update_indir_branch_cond();
1655 switch (mds_mitigation) {
1656 case MDS_MITIGATION_FULL:
1657 case MDS_MITIGATION_VMWERV:
1658 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1659 pr_warn_once(MDS_MSG_SMT);
1660 update_mds_branch_idle();
1662 case MDS_MITIGATION_OFF:
1666 switch (taa_mitigation) {
1667 case TAA_MITIGATION_VERW:
1668 case TAA_MITIGATION_UCODE_NEEDED:
1669 if (sched_smt_active())
1670 pr_warn_once(TAA_MSG_SMT);
1672 case TAA_MITIGATION_TSX_DISABLED:
1673 case TAA_MITIGATION_OFF:
1677 switch (mmio_mitigation) {
1678 case MMIO_MITIGATION_VERW:
1679 case MMIO_MITIGATION_UCODE_NEEDED:
1680 if (sched_smt_active())
1681 pr_warn_once(MMIO_MSG_SMT);
1683 case MMIO_MITIGATION_OFF:
1687 mutex_unlock(&spec_ctrl_mutex);
1691 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
1693 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1695 /* The kernel command line selection */
1696 enum ssb_mitigation_cmd {
1697 SPEC_STORE_BYPASS_CMD_NONE,
1698 SPEC_STORE_BYPASS_CMD_AUTO,
1699 SPEC_STORE_BYPASS_CMD_ON,
1700 SPEC_STORE_BYPASS_CMD_PRCTL,
1701 SPEC_STORE_BYPASS_CMD_SECCOMP,
1704 static const char * const ssb_strings[] = {
1705 [SPEC_STORE_BYPASS_NONE] = "Vulnerable",
1706 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
1707 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
1708 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1711 static const struct {
1713 enum ssb_mitigation_cmd cmd;
1714 } ssb_mitigation_options[] __initconst = {
1715 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
1716 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
1717 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
1718 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
1719 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1722 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1724 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1728 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1729 cpu_mitigations_off()) {
1730 return SPEC_STORE_BYPASS_CMD_NONE;
1732 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1735 return SPEC_STORE_BYPASS_CMD_AUTO;
1737 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1738 if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1741 cmd = ssb_mitigation_options[i].cmd;
1745 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1746 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1747 return SPEC_STORE_BYPASS_CMD_AUTO;
1754 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1756 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1757 enum ssb_mitigation_cmd cmd;
1759 if (!boot_cpu_has(X86_FEATURE_SSBD))
1762 cmd = ssb_parse_cmdline();
1763 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1764 (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1765 cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1769 case SPEC_STORE_BYPASS_CMD_SECCOMP:
1771 * Choose prctl+seccomp as the default mode if seccomp is
1774 if (IS_ENABLED(CONFIG_SECCOMP))
1775 mode = SPEC_STORE_BYPASS_SECCOMP;
1777 mode = SPEC_STORE_BYPASS_PRCTL;
1779 case SPEC_STORE_BYPASS_CMD_ON:
1780 mode = SPEC_STORE_BYPASS_DISABLE;
1782 case SPEC_STORE_BYPASS_CMD_AUTO:
1783 case SPEC_STORE_BYPASS_CMD_PRCTL:
1784 mode = SPEC_STORE_BYPASS_PRCTL;
1786 case SPEC_STORE_BYPASS_CMD_NONE:
1791 * We have three CPU feature flags that are in play here:
1792 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1793 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1794 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1796 if (mode == SPEC_STORE_BYPASS_DISABLE) {
1797 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1799 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1800 * use a completely different MSR and bit dependent on family.
1802 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1803 !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1804 x86_amd_ssb_disable();
1806 x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1807 write_spec_ctrl_current(x86_spec_ctrl_base, true);
1814 static void ssb_select_mitigation(void)
1816 ssb_mode = __ssb_select_mitigation();
1818 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1819 pr_info("%s\n", ssb_strings[ssb_mode]);
1823 #define pr_fmt(fmt) "Speculation prctl: " fmt
1825 static void task_update_spec_tif(struct task_struct *tsk)
1827 /* Force the update of the real TIF bits */
1828 set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1831 * Immediately update the speculation control MSRs for the current
1832 * task, but for a non-current task delay setting the CPU
1833 * mitigation until it is scheduled next.
1835 * This can only happen for SECCOMP mitigation. For PRCTL it's
1836 * always the current task.
1839 speculation_ctrl_update_current();
1842 static int l1d_flush_prctl_set(struct task_struct *task, unsigned long ctrl)
1845 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
1849 case PR_SPEC_ENABLE:
1850 set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
1852 case PR_SPEC_DISABLE:
1853 clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
1860 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1862 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1863 ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1867 case PR_SPEC_ENABLE:
1868 /* If speculation is force disabled, enable is not allowed */
1869 if (task_spec_ssb_force_disable(task))
1871 task_clear_spec_ssb_disable(task);
1872 task_clear_spec_ssb_noexec(task);
1873 task_update_spec_tif(task);
1875 case PR_SPEC_DISABLE:
1876 task_set_spec_ssb_disable(task);
1877 task_clear_spec_ssb_noexec(task);
1878 task_update_spec_tif(task);
1880 case PR_SPEC_FORCE_DISABLE:
1881 task_set_spec_ssb_disable(task);
1882 task_set_spec_ssb_force_disable(task);
1883 task_clear_spec_ssb_noexec(task);
1884 task_update_spec_tif(task);
1886 case PR_SPEC_DISABLE_NOEXEC:
1887 if (task_spec_ssb_force_disable(task))
1889 task_set_spec_ssb_disable(task);
1890 task_set_spec_ssb_noexec(task);
1891 task_update_spec_tif(task);
1899 static bool is_spec_ib_user_controlled(void)
1901 return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1902 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1903 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1904 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1907 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1910 case PR_SPEC_ENABLE:
1911 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1912 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1916 * With strict mode for both IBPB and STIBP, the instruction
1917 * code paths avoid checking this task flag and instead,
1918 * unconditionally run the instruction. However, STIBP and IBPB
1919 * are independent and either can be set to conditionally
1920 * enabled regardless of the mode of the other.
1922 * If either is set to conditional, allow the task flag to be
1923 * updated, unless it was force-disabled by a previous prctl
1924 * call. Currently, this is possible on an AMD CPU which has the
1925 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1926 * kernel is booted with 'spectre_v2_user=seccomp', then
1927 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1928 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1930 if (!is_spec_ib_user_controlled() ||
1931 task_spec_ib_force_disable(task))
1934 task_clear_spec_ib_disable(task);
1935 task_update_spec_tif(task);
1937 case PR_SPEC_DISABLE:
1938 case PR_SPEC_FORCE_DISABLE:
1940 * Indirect branch speculation is always allowed when
1941 * mitigation is force disabled.
1943 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1944 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1947 if (!is_spec_ib_user_controlled())
1950 task_set_spec_ib_disable(task);
1951 if (ctrl == PR_SPEC_FORCE_DISABLE)
1952 task_set_spec_ib_force_disable(task);
1953 task_update_spec_tif(task);
1961 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1965 case PR_SPEC_STORE_BYPASS:
1966 return ssb_prctl_set(task, ctrl);
1967 case PR_SPEC_INDIRECT_BRANCH:
1968 return ib_prctl_set(task, ctrl);
1969 case PR_SPEC_L1D_FLUSH:
1970 return l1d_flush_prctl_set(task, ctrl);
1976 #ifdef CONFIG_SECCOMP
1977 void arch_seccomp_spec_mitigate(struct task_struct *task)
1979 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1980 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1981 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1982 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1983 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1987 static int l1d_flush_prctl_get(struct task_struct *task)
1989 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
1990 return PR_SPEC_FORCE_DISABLE;
1992 if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH))
1993 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1995 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1998 static int ssb_prctl_get(struct task_struct *task)
2001 case SPEC_STORE_BYPASS_DISABLE:
2002 return PR_SPEC_DISABLE;
2003 case SPEC_STORE_BYPASS_SECCOMP:
2004 case SPEC_STORE_BYPASS_PRCTL:
2005 if (task_spec_ssb_force_disable(task))
2006 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
2007 if (task_spec_ssb_noexec(task))
2008 return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC;
2009 if (task_spec_ssb_disable(task))
2010 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
2011 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
2013 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
2014 return PR_SPEC_ENABLE;
2015 return PR_SPEC_NOT_AFFECTED;
2019 static int ib_prctl_get(struct task_struct *task)
2021 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
2022 return PR_SPEC_NOT_AFFECTED;
2024 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
2025 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
2026 return PR_SPEC_ENABLE;
2027 else if (is_spec_ib_user_controlled()) {
2028 if (task_spec_ib_force_disable(task))
2029 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
2030 if (task_spec_ib_disable(task))
2031 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
2032 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
2033 } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
2034 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
2035 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
2036 return PR_SPEC_DISABLE;
2038 return PR_SPEC_NOT_AFFECTED;
2041 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
2044 case PR_SPEC_STORE_BYPASS:
2045 return ssb_prctl_get(task);
2046 case PR_SPEC_INDIRECT_BRANCH:
2047 return ib_prctl_get(task);
2048 case PR_SPEC_L1D_FLUSH:
2049 return l1d_flush_prctl_get(task);
2055 void x86_spec_ctrl_setup_ap(void)
2057 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
2058 write_spec_ctrl_current(x86_spec_ctrl_base, true);
2060 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
2061 x86_amd_ssb_disable();
2064 bool itlb_multihit_kvm_mitigation;
2065 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
2068 #define pr_fmt(fmt) "L1TF: " fmt
2070 /* Default mitigation for L1TF-affected CPUs */
2071 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
2072 #if IS_ENABLED(CONFIG_KVM_INTEL)
2073 EXPORT_SYMBOL_GPL(l1tf_mitigation);
2075 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
2076 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
2079 * These CPUs all support 44bits physical address space internally in the
2080 * cache but CPUID can report a smaller number of physical address bits.
2082 * The L1TF mitigation uses the top most address bit for the inversion of
2083 * non present PTEs. When the installed memory reaches into the top most
2084 * address bit due to memory holes, which has been observed on machines
2085 * which report 36bits physical address bits and have 32G RAM installed,
2086 * then the mitigation range check in l1tf_select_mitigation() triggers.
2087 * This is a false positive because the mitigation is still possible due to
2088 * the fact that the cache uses 44bit internally. Use the cache bits
2089 * instead of the reported physical bits and adjust them on the affected
2090 * machines to 44bit if the reported bits are less than 44.
2092 static void override_cache_bits(struct cpuinfo_x86 *c)
2097 switch (c->x86_model) {
2098 case INTEL_FAM6_NEHALEM:
2099 case INTEL_FAM6_WESTMERE:
2100 case INTEL_FAM6_SANDYBRIDGE:
2101 case INTEL_FAM6_IVYBRIDGE:
2102 case INTEL_FAM6_HASWELL:
2103 case INTEL_FAM6_HASWELL_L:
2104 case INTEL_FAM6_HASWELL_G:
2105 case INTEL_FAM6_BROADWELL:
2106 case INTEL_FAM6_BROADWELL_G:
2107 case INTEL_FAM6_SKYLAKE_L:
2108 case INTEL_FAM6_SKYLAKE:
2109 case INTEL_FAM6_KABYLAKE_L:
2110 case INTEL_FAM6_KABYLAKE:
2111 if (c->x86_cache_bits < 44)
2112 c->x86_cache_bits = 44;
2117 static void __init l1tf_select_mitigation(void)
2121 if (!boot_cpu_has_bug(X86_BUG_L1TF))
2124 if (cpu_mitigations_off())
2125 l1tf_mitigation = L1TF_MITIGATION_OFF;
2126 else if (cpu_mitigations_auto_nosmt())
2127 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2129 override_cache_bits(&boot_cpu_data);
2131 switch (l1tf_mitigation) {
2132 case L1TF_MITIGATION_OFF:
2133 case L1TF_MITIGATION_FLUSH_NOWARN:
2134 case L1TF_MITIGATION_FLUSH:
2136 case L1TF_MITIGATION_FLUSH_NOSMT:
2137 case L1TF_MITIGATION_FULL:
2138 cpu_smt_disable(false);
2140 case L1TF_MITIGATION_FULL_FORCE:
2141 cpu_smt_disable(true);
2145 #if CONFIG_PGTABLE_LEVELS == 2
2146 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
2150 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
2151 if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
2152 e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
2153 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
2154 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
2156 pr_info("However, doing so will make a part of your RAM unusable.\n");
2157 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
2161 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
2164 static int __init l1tf_cmdline(char *str)
2166 if (!boot_cpu_has_bug(X86_BUG_L1TF))
2172 if (!strcmp(str, "off"))
2173 l1tf_mitigation = L1TF_MITIGATION_OFF;
2174 else if (!strcmp(str, "flush,nowarn"))
2175 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
2176 else if (!strcmp(str, "flush"))
2177 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
2178 else if (!strcmp(str, "flush,nosmt"))
2179 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2180 else if (!strcmp(str, "full"))
2181 l1tf_mitigation = L1TF_MITIGATION_FULL;
2182 else if (!strcmp(str, "full,force"))
2183 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
2187 early_param("l1tf", l1tf_cmdline);
2190 #define pr_fmt(fmt) fmt
2194 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
2196 #if IS_ENABLED(CONFIG_KVM_INTEL)
2197 static const char * const l1tf_vmx_states[] = {
2198 [VMENTER_L1D_FLUSH_AUTO] = "auto",
2199 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable",
2200 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes",
2201 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes",
2202 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled",
2203 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary"
2206 static ssize_t l1tf_show_state(char *buf)
2208 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
2209 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2211 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
2212 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
2213 sched_smt_active())) {
2214 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
2215 l1tf_vmx_states[l1tf_vmx_mitigation]);
2218 return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
2219 l1tf_vmx_states[l1tf_vmx_mitigation],
2220 sched_smt_active() ? "vulnerable" : "disabled");
2223 static ssize_t itlb_multihit_show_state(char *buf)
2225 if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2226 !boot_cpu_has(X86_FEATURE_VMX))
2227 return sprintf(buf, "KVM: Mitigation: VMX unsupported\n");
2228 else if (!(cr4_read_shadow() & X86_CR4_VMXE))
2229 return sprintf(buf, "KVM: Mitigation: VMX disabled\n");
2230 else if (itlb_multihit_kvm_mitigation)
2231 return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
2233 return sprintf(buf, "KVM: Vulnerable\n");
2236 static ssize_t l1tf_show_state(char *buf)
2238 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2241 static ssize_t itlb_multihit_show_state(char *buf)
2243 return sprintf(buf, "Processor vulnerable\n");
2247 static ssize_t mds_show_state(char *buf)
2249 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2250 return sprintf(buf, "%s; SMT Host state unknown\n",
2251 mds_strings[mds_mitigation]);
2254 if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
2255 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2256 (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
2257 sched_smt_active() ? "mitigated" : "disabled"));
2260 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2261 sched_smt_active() ? "vulnerable" : "disabled");
2264 static ssize_t tsx_async_abort_show_state(char *buf)
2266 if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
2267 (taa_mitigation == TAA_MITIGATION_OFF))
2268 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
2270 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2271 return sprintf(buf, "%s; SMT Host state unknown\n",
2272 taa_strings[taa_mitigation]);
2275 return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
2276 sched_smt_active() ? "vulnerable" : "disabled");
2279 static ssize_t mmio_stale_data_show_state(char *buf)
2281 if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2282 return sysfs_emit(buf, "Unknown: No mitigations\n");
2284 if (mmio_mitigation == MMIO_MITIGATION_OFF)
2285 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
2287 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2288 return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2289 mmio_strings[mmio_mitigation]);
2292 return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation],
2293 sched_smt_active() ? "vulnerable" : "disabled");
2296 static char *stibp_state(void)
2298 if (spectre_v2_in_ibrs_mode(spectre_v2_enabled))
2301 switch (spectre_v2_user_stibp) {
2302 case SPECTRE_V2_USER_NONE:
2303 return ", STIBP: disabled";
2304 case SPECTRE_V2_USER_STRICT:
2305 return ", STIBP: forced";
2306 case SPECTRE_V2_USER_STRICT_PREFERRED:
2307 return ", STIBP: always-on";
2308 case SPECTRE_V2_USER_PRCTL:
2309 case SPECTRE_V2_USER_SECCOMP:
2310 if (static_key_enabled(&switch_to_cond_stibp))
2311 return ", STIBP: conditional";
2316 static char *ibpb_state(void)
2318 if (boot_cpu_has(X86_FEATURE_IBPB)) {
2319 if (static_key_enabled(&switch_mm_always_ibpb))
2320 return ", IBPB: always-on";
2321 if (static_key_enabled(&switch_mm_cond_ibpb))
2322 return ", IBPB: conditional";
2323 return ", IBPB: disabled";
2328 static char *pbrsb_eibrs_state(void)
2330 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
2331 if (boot_cpu_has(X86_FEATURE_RSB_VMEXIT_LITE) ||
2332 boot_cpu_has(X86_FEATURE_RSB_VMEXIT))
2333 return ", PBRSB-eIBRS: SW sequence";
2335 return ", PBRSB-eIBRS: Vulnerable";
2337 return ", PBRSB-eIBRS: Not affected";
2341 static ssize_t spectre_v2_show_state(char *buf)
2343 if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
2344 return sprintf(buf, "Vulnerable: LFENCE\n");
2346 if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
2347 return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n");
2349 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
2350 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
2351 return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
2353 return sprintf(buf, "%s%s%s%s%s%s%s\n",
2354 spectre_v2_strings[spectre_v2_enabled],
2356 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
2358 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
2359 pbrsb_eibrs_state(),
2360 spectre_v2_module_string());
2363 static ssize_t srbds_show_state(char *buf)
2365 return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
2368 static ssize_t retbleed_show_state(char *buf)
2370 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
2371 retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
2372 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
2373 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
2374 return sprintf(buf, "Vulnerable: untrained return thunk / IBPB on non-AMD based uarch\n");
2376 return sprintf(buf, "%s; SMT %s\n",
2377 retbleed_strings[retbleed_mitigation],
2378 !sched_smt_active() ? "disabled" :
2379 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
2380 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ?
2381 "enabled with STIBP protection" : "vulnerable");
2384 return sprintf(buf, "%s\n", retbleed_strings[retbleed_mitigation]);
2387 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
2388 char *buf, unsigned int bug)
2390 if (!boot_cpu_has_bug(bug))
2391 return sprintf(buf, "Not affected\n");
2394 case X86_BUG_CPU_MELTDOWN:
2395 if (boot_cpu_has(X86_FEATURE_PTI))
2396 return sprintf(buf, "Mitigation: PTI\n");
2398 if (hypervisor_is_type(X86_HYPER_XEN_PV))
2399 return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
2403 case X86_BUG_SPECTRE_V1:
2404 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
2406 case X86_BUG_SPECTRE_V2:
2407 return spectre_v2_show_state(buf);
2409 case X86_BUG_SPEC_STORE_BYPASS:
2410 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
2413 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
2414 return l1tf_show_state(buf);
2418 return mds_show_state(buf);
2421 return tsx_async_abort_show_state(buf);
2423 case X86_BUG_ITLB_MULTIHIT:
2424 return itlb_multihit_show_state(buf);
2427 return srbds_show_state(buf);
2429 case X86_BUG_MMIO_STALE_DATA:
2430 case X86_BUG_MMIO_UNKNOWN:
2431 return mmio_stale_data_show_state(buf);
2433 case X86_BUG_RETBLEED:
2434 return retbleed_show_state(buf);
2440 return sprintf(buf, "Vulnerable\n");
2443 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
2445 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
2448 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
2450 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
2453 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
2455 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
2458 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
2460 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
2463 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
2465 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
2468 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
2470 return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
2473 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
2475 return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
2478 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
2480 return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
2483 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
2485 return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
2488 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
2490 if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2491 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN);
2493 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
2496 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf)
2498 return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED);