arch/x86/kernel/cpu/bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1994  Linus Torvalds
   4  *
   5  *  Cyrix stuff, June 1998 by:
   6  *      - Rafael R. Reilova (moved everything from head.S),
   7  *        <rreilova@ececs.uc.edu>
   8  *      - Channing Corn (tests & fixes),
   9  *      - Andrew D. Balsa (code cleanup).
  10  */
  11 #include <linux/init.h>
  12 #include <linux/utsname.h>
  13 #include <linux/cpu.h>
  14 #include <linux/module.h>
  15 #include <linux/nospec.h>
  16 #include <linux/prctl.h>
  17
  18 #include <asm/spec-ctrl.h>
  19 #include <asm/cmdline.h>
  20 #include <asm/bugs.h>
  21 #include <asm/processor.h>
  22 #include <asm/processor-flags.h>
  23 #include <asm/fpu/internal.h>
  24 #include <asm/msr.h>
  25 #include <asm/paravirt.h>
  26 #include <asm/alternative.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/set_memory.h>
  29 #include <asm/intel-family.h>
  30
  31 static void __init spectre_v2_select_mitigation(void);
  32 static void __init ssb_select_mitigation(void);
  33
  34 /*
  35  * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
  36  * writes to SPEC_CTRL contain whatever reserved bits have been set.
  37  */
  38 u64 __ro_after_init x86_spec_ctrl_base;
  39 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  40
  41 /*
  42  * The vendor and possibly platform specific bits which can be modified in
  43  * x86_spec_ctrl_base.
  44  */
  45 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
  46
  47 /*
  48  * AMD specific MSR info for Speculative Store Bypass control.
  49  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  50  */
  51 u64 __ro_after_init x86_amd_ls_cfg_base;
  52 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  53
  54 void __init check_bugs(void)
  55 {
  56         identify_boot_cpu();
  57
  58         if (!IS_ENABLED(CONFIG_SMP)) {
  59                 pr_info("CPU: ");
  60                 print_cpu_info(&boot_cpu_data);
  61         }
  62
  63         /*
  64          * Read the SPEC_CTRL MSR to account for reserved bits which may
  65          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  66          * init code as it is not enumerated and depends on the family.
  67          */
  68         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  69                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  70
  71         /* Allow STIBP in MSR_SPEC_CTRL if supported */
  72         if (boot_cpu_has(X86_FEATURE_STIBP))
  73                 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
  74
  75         /* Select the proper spectre mitigation before patching alternatives */
  76         spectre_v2_select_mitigation();
  77
  78         /*
  79          * Select proper mitigation for any exposure to the Speculative Store
  80          * Bypass vulnerability.
  81          */
  82         ssb_select_mitigation();
  83
  84 #ifdef CONFIG_X86_32
  85         /*
  86          * Check whether we are able to run this kernel safely on SMP.
  87          *
  88          * - i386 is no longer supported.
  89          * - In order to run on anything without a TSC, we need to be
  90          *   compiled for a i486.
  91          */
  92         if (boot_cpu_data.x86 < 4)
  93                 panic("Kernel requires i486+ for 'invlpg' and other features");
  94
  95         init_utsname()->machine[1] =
  96                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
  97         alternative_instructions();
  98
  99         fpu__init_check_bugs();
 100 #else /* CONFIG_X86_64 */
 101         alternative_instructions();
 102
 103         /*
 104          * Make sure the first 2MB area is not mapped by huge pages
 105          * There are typically fixed size MTRRs in there and overlapping
 106          * MTRRs into large pages causes slow downs.
 107          *
 108          * Right now we don't do that with gbpages because there seems
 109          * very little benefit for that case.
 110          */
 111         if (!direct_gbpages)
 112                 set_memory_4k((unsigned long)__va(0), 1);
 113 #endif
 114 }
 115
 116 /* The kernel command line selection */
 117 enum spectre_v2_mitigation_cmd {
 118         SPECTRE_V2_CMD_NONE,
 119         SPECTRE_V2_CMD_AUTO,
 120         SPECTRE_V2_CMD_FORCE,
 121         SPECTRE_V2_CMD_RETPOLINE,
 122         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 123         SPECTRE_V2_CMD_RETPOLINE_AMD,
 124 };
 125
 126 static const char *spectre_v2_strings[] = {
 127         [SPECTRE_V2_NONE]                       = "Vulnerable",
 128         [SPECTRE_V2_RETPOLINE_MINIMAL]          = "Vulnerable: Minimal generic ASM retpoline",
 129         [SPECTRE_V2_RETPOLINE_MINIMAL_AMD]      = "Vulnerable: Minimal AMD ASM retpoline",
 130         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 131         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 132 };
 133
 134 #undef pr_fmt
 135 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 136
 137 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 138         SPECTRE_V2_NONE;
 139
 140 void
 141 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 142 {
 143         u64 msrval, guestval, hostval = x86_spec_ctrl_base;
 144         struct thread_info *ti = current_thread_info();
 145
 146         /* Is MSR_SPEC_CTRL implemented ? */
 147         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 148                 /*
 149                  * Restrict guest_spec_ctrl to supported values. Clear the
 150                  * modifiable bits in the host base value and or the
 151                  * modifiable bits from the guest value.
 152                  */
 153                 guestval = hostval & ~x86_spec_ctrl_mask;
 154                 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 155
 156                 /* SSBD controlled in MSR_SPEC_CTRL */
 157                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
 158                         hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 159
 160                 if (hostval != guestval) {
 161                         msrval = setguest ? guestval : hostval;
 162                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
 163                 }
 164         }
 165 }
 166 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 167
 168 static void x86_amd_ssb_disable(void)
 169 {
 170         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 171
 172         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 173                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 174         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 175                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 176 }
 177
 178 #ifdef RETPOLINE
 179 static bool spectre_v2_bad_module;
 180
 181 bool retpoline_module_ok(bool has_retpoline)
 182 {
 183         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 184                 return true;
 185
 186         pr_err("System may be vulnerable to spectre v2\n");
 187         spectre_v2_bad_module = true;
 188         return false;
 189 }
 190
 191 static inline const char *spectre_v2_module_string(void)
 192 {
 193         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 194 }
 195 #else
 196 static inline const char *spectre_v2_module_string(void) { return ""; }
 197 #endif
 198
 199 static void __init spec2_print_if_insecure(const char *reason)
 200 {
 201         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 202                 pr_info("%s selected on command line.\n", reason);
 203 }
 204
 205 static void __init spec2_print_if_secure(const char *reason)
 206 {
 207         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 208                 pr_info("%s selected on command line.\n", reason);
 209 }
 210
 211 static inline bool retp_compiler(void)
 212 {
 213         return __is_defined(RETPOLINE);
 214 }
 215
 216 static inline bool match_option(const char *arg, int arglen, const char *opt)
 217 {
 218         int len = strlen(opt);
 219
 220         return len == arglen && !strncmp(arg, opt, len);
 221 }
 222
 223 static const struct {
 224         const char *option;
 225         enum spectre_v2_mitigation_cmd cmd;
 226         bool secure;
 227 } mitigation_options[] = {
 228         { "off",               SPECTRE_V2_CMD_NONE,              false },
 229         { "on",                SPECTRE_V2_CMD_FORCE,             true },
 230         { "retpoline",         SPECTRE_V2_CMD_RETPOLINE,         false },
 231         { "retpoline,amd",     SPECTRE_V2_CMD_RETPOLINE_AMD,     false },
 232         { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
 233         { "auto",              SPECTRE_V2_CMD_AUTO,              false },
 234 };
 235
 236 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 237 {
 238         char arg[20];
 239         int ret, i;
 240         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
 241
 242         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
 243                 return SPECTRE_V2_CMD_NONE;
 244         else {
 245                 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
 246                 if (ret < 0)
 247                         return SPECTRE_V2_CMD_AUTO;
 248
 249                 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
 250                         if (!match_option(arg, ret, mitigation_options[i].option))
 251                                 continue;
 252                         cmd = mitigation_options[i].cmd;
 253                         break;
 254                 }
 255
 256                 if (i >= ARRAY_SIZE(mitigation_options)) {
 257                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 258                         return SPECTRE_V2_CMD_AUTO;
 259                 }
 260         }
 261
 262         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
 263              cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
 264              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
 265             !IS_ENABLED(CONFIG_RETPOLINE)) {
 266                 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
 267                 return SPECTRE_V2_CMD_AUTO;
 268         }
 269
 270         if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
 271             boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 272                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 273                 return SPECTRE_V2_CMD_AUTO;
 274         }
 275
 276         if (mitigation_options[i].secure)
 277                 spec2_print_if_secure(mitigation_options[i].option);
 278         else
 279                 spec2_print_if_insecure(mitigation_options[i].option);
 280
 281         return cmd;
 282 }
 283
 284 /* Check for Skylake-like CPUs (for RSB handling) */
 285 static bool __init is_skylake_era(void)
 286 {
 287         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 288             boot_cpu_data.x86 == 6) {
 289                 switch (boot_cpu_data.x86_model) {
 290                 case INTEL_FAM6_SKYLAKE_MOBILE:
 291                 case INTEL_FAM6_SKYLAKE_DESKTOP:
 292                 case INTEL_FAM6_SKYLAKE_X:
 293                 case INTEL_FAM6_KABYLAKE_MOBILE:
 294                 case INTEL_FAM6_KABYLAKE_DESKTOP:
 295                         return true;
 296                 }
 297         }
 298         return false;
 299 }
 300
 301 static void __init spectre_v2_select_mitigation(void)
 302 {
 303         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 304         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 305
 306         /*
 307          * If the CPU is not affected and the command line mode is NONE or AUTO
 308          * then nothing to do.
 309          */
 310         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 311             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 312                 return;
 313
 314         switch (cmd) {
 315         case SPECTRE_V2_CMD_NONE:
 316                 return;
 317
 318         case SPECTRE_V2_CMD_FORCE:
 319         case SPECTRE_V2_CMD_AUTO:
 320                 if (IS_ENABLED(CONFIG_RETPOLINE))
 321                         goto retpoline_auto;
 322                 break;
 323         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 324                 if (IS_ENABLED(CONFIG_RETPOLINE))
 325                         goto retpoline_amd;
 326                 break;
 327         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 328                 if (IS_ENABLED(CONFIG_RETPOLINE))
 329                         goto retpoline_generic;
 330                 break;
 331         case SPECTRE_V2_CMD_RETPOLINE:
 332                 if (IS_ENABLED(CONFIG_RETPOLINE))
 333                         goto retpoline_auto;
 334                 break;
 335         }
 336         pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
 337         return;
 338
 339 retpoline_auto:
 340         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 341         retpoline_amd:
 342                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 343                         pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
 344                         goto retpoline_generic;
 345                 }
 346                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
 347                                          SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
 348                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 349                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 350         } else {
 351         retpoline_generic:
 352                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
 353                                          SPECTRE_V2_RETPOLINE_MINIMAL;
 354                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 355         }
 356
 357         spectre_v2_enabled = mode;
 358         pr_info("%s\n", spectre_v2_strings[mode]);
 359
 360         /*
 361          * If neither SMEP nor PTI are available, there is a risk of
 362          * hitting userspace addresses in the RSB after a context switch
 363          * from a shallow call stack to a deeper one. To prevent this fill
 364          * the entire RSB, even when using IBRS.
 365          *
 366          * Skylake era CPUs have a separate issue with *underflow* of the
 367          * RSB, when they will predict 'ret' targets from the generic BTB.
 368          * The proper mitigation for this is IBRS. If IBRS is not supported
 369          * or deactivated in favour of retpolines the RSB fill on context
 370          * switch is required.
 371          */
 372         if ((!boot_cpu_has(X86_FEATURE_PTI) &&
 373              !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
 374                 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 375                 pr_info("Spectre v2 mitigation: Filling RSB on context switch\n");
 376         }
 377
 378         /* Initialize Indirect Branch Prediction Barrier if supported */
 379         if (boot_cpu_has(X86_FEATURE_IBPB)) {
 380                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
 381                 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
 382         }
 383
 384         /*
 385          * Retpoline means the kernel is safe because it has no indirect
 386          * branches. But firmware isn't, so use IBRS to protect that.
 387          */
 388         if (boot_cpu_has(X86_FEATURE_IBRS)) {
 389                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
 390                 pr_info("Enabling Restricted Speculation for firmware calls\n");
 391         }
 392 }
 393
 394 #undef pr_fmt
 395 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
 396
 397 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
 398
 399 /* The kernel command line selection */
 400 enum ssb_mitigation_cmd {
 401         SPEC_STORE_BYPASS_CMD_NONE,
 402         SPEC_STORE_BYPASS_CMD_AUTO,
 403         SPEC_STORE_BYPASS_CMD_ON,
 404         SPEC_STORE_BYPASS_CMD_PRCTL,
 405         SPEC_STORE_BYPASS_CMD_SECCOMP,
 406 };
 407
 408 static const char *ssb_strings[] = {
 409         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
 410         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
 411         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
 412         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
 413 };
 414
 415 static const struct {
 416         const char *option;
 417         enum ssb_mitigation_cmd cmd;
 418 } ssb_mitigation_options[] = {
 419         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
 420         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
 421         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
 422         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
 423         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
 424 };
 425
 426 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 427 {
 428         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
 429         char arg[20];
 430         int ret, i;
 431
 432         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
 433                 return SPEC_STORE_BYPASS_CMD_NONE;
 434         } else {
 435                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
 436                                           arg, sizeof(arg));
 437                 if (ret < 0)
 438                         return SPEC_STORE_BYPASS_CMD_AUTO;
 439
 440                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
 441                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
 442                                 continue;
 443
 444                         cmd = ssb_mitigation_options[i].cmd;
 445                         break;
 446                 }
 447
 448                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
 449                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 450                         return SPEC_STORE_BYPASS_CMD_AUTO;
 451                 }
 452         }
 453
 454         return cmd;
 455 }
 456
 457 static enum ssb_mitigation __init __ssb_select_mitigation(void)
 458 {
 459         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
 460         enum ssb_mitigation_cmd cmd;
 461
 462         if (!boot_cpu_has(X86_FEATURE_SSBD))
 463                 return mode;
 464
 465         cmd = ssb_parse_cmdline();
 466         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
 467             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
 468              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
 469                 return mode;
 470
 471         switch (cmd) {
 472         case SPEC_STORE_BYPASS_CMD_AUTO:
 473         case SPEC_STORE_BYPASS_CMD_SECCOMP:
 474                 /*
 475                  * Choose prctl+seccomp as the default mode if seccomp is
 476                  * enabled.
 477                  */
 478                 if (IS_ENABLED(CONFIG_SECCOMP))
 479                         mode = SPEC_STORE_BYPASS_SECCOMP;
 480                 else
 481                         mode = SPEC_STORE_BYPASS_PRCTL;
 482                 break;
 483         case SPEC_STORE_BYPASS_CMD_ON:
 484                 mode = SPEC_STORE_BYPASS_DISABLE;
 485                 break;
 486         case SPEC_STORE_BYPASS_CMD_PRCTL:
 487                 mode = SPEC_STORE_BYPASS_PRCTL;
 488                 break;
 489         case SPEC_STORE_BYPASS_CMD_NONE:
 490                 break;
 491         }
 492
 493         /*
 494          * We have three CPU feature flags that are in play here:
 495          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
 496          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
 497          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
 498          */
 499         if (mode == SPEC_STORE_BYPASS_DISABLE) {
 500                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 501                 /*
 502                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
 503                  * a completely different MSR and bit dependent on family.
 504                  */
 505                 switch (boot_cpu_data.x86_vendor) {
 506                 case X86_VENDOR_INTEL:
 507                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 508                         x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
 509                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 510                         break;
 511                 case X86_VENDOR_AMD:
 512                         x86_amd_ssb_disable();
 513                         break;
 514                 }
 515         }
 516
 517         return mode;
 518 }
 519
 520 static void ssb_select_mitigation(void)
 521 {
 522         ssb_mode = __ssb_select_mitigation();
 523
 524         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 525                 pr_info("%s\n", ssb_strings[ssb_mode]);
 526 }
 527
 528 #undef pr_fmt
 529 #define pr_fmt(fmt)     "Speculation prctl: " fmt
 530
 531 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 532 {
 533         bool update;
 534
 535         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
 536             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
 537                 return -ENXIO;
 538
 539         switch (ctrl) {
 540         case PR_SPEC_ENABLE:
 541                 /* If speculation is force disabled, enable is not allowed */
 542                 if (task_spec_ssb_force_disable(task))
 543                         return -EPERM;
 544                 task_clear_spec_ssb_disable(task);
 545                 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
 546                 break;
 547         case PR_SPEC_DISABLE:
 548                 task_set_spec_ssb_disable(task);
 549                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 550                 break;
 551         case PR_SPEC_FORCE_DISABLE:
 552                 task_set_spec_ssb_disable(task);
 553                 task_set_spec_ssb_force_disable(task);
 554                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 555                 break;
 556         default:
 557                 return -ERANGE;
 558         }
 559
 560         /*
 561          * If being set on non-current task, delay setting the CPU
 562          * mitigation until it is next scheduled.
 563          */
 564         if (task == current && update)
 565                 speculative_store_bypass_update_current();
 566
 567         return 0;
 568 }
 569
 570 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
 571                              unsigned long ctrl)
 572 {
 573         switch (which) {
 574         case PR_SPEC_STORE_BYPASS:
 575                 return ssb_prctl_set(task, ctrl);
 576         default:
 577                 return -ENODEV;
 578         }
 579 }
 580
 581 #ifdef CONFIG_SECCOMP
 582 void arch_seccomp_spec_mitigate(struct task_struct *task)
 583 {
 584         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
 585                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
 586 }
 587 #endif
 588
 589 static int ssb_prctl_get(struct task_struct *task)
 590 {
 591         switch (ssb_mode) {
 592         case SPEC_STORE_BYPASS_DISABLE:
 593                 return PR_SPEC_DISABLE;
 594         case SPEC_STORE_BYPASS_SECCOMP:
 595         case SPEC_STORE_BYPASS_PRCTL:
 596                 if (task_spec_ssb_force_disable(task))
 597                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 598                 if (task_spec_ssb_disable(task))
 599                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 600                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 601         default:
 602                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 603                         return PR_SPEC_ENABLE;
 604                 return PR_SPEC_NOT_AFFECTED;
 605         }
 606 }
 607
 608 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
 609 {
 610         switch (which) {
 611         case PR_SPEC_STORE_BYPASS:
 612                 return ssb_prctl_get(task);
 613         default:
 614                 return -ENODEV;
 615         }
 616 }
 617
 618 void x86_spec_ctrl_setup_ap(void)
 619 {
 620         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 621                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 622
 623         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
 624                 x86_amd_ssb_disable();
 625 }
 626
 627 #ifdef CONFIG_SYSFS
 628
 629 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
 630                                char *buf, unsigned int bug)
 631 {
 632         if (!boot_cpu_has_bug(bug))
 633                 return sprintf(buf, "Not affected\n");
 634
 635         switch (bug) {
 636         case X86_BUG_CPU_MELTDOWN:
 637                 if (boot_cpu_has(X86_FEATURE_PTI))
 638                         return sprintf(buf, "Mitigation: PTI\n");
 639
 640                 break;
 641
 642         case X86_BUG_SPECTRE_V1:
 643                 return sprintf(buf, "Mitigation: __user pointer sanitization\n");
 644
 645         case X86_BUG_SPECTRE_V2:
 646                 return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
 647                                boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "",
 648                                boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
 649                                spectre_v2_module_string());
 650
 651         case X86_BUG_SPEC_STORE_BYPASS:
 652                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
 653
 654         default:
 655                 break;
 656         }
 657
 658         return sprintf(buf, "Vulnerable\n");
 659 }
 660
 661 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
 662 {
 663         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
 664 }
 665
 666 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
 667 {
 668         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
 669 }
 670
 671 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
 672 {
 673         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
 674 }
 675
 676 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
 677 {
 678         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
 679 }
 680 #endif