1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
18 #include <asm/spec-ctrl.h>
19 #include <asm/cmdline.h>
21 #include <asm/processor.h>
22 #include <asm/processor-flags.h>
23 #include <asm/fpu/internal.h>
25 #include <asm/paravirt.h>
26 #include <asm/alternative.h>
27 #include <asm/pgtable.h>
28 #include <asm/set_memory.h>
29 #include <asm/intel-family.h>
31 static void __init spectre_v2_select_mitigation(void);
32 static void __init ssb_select_mitigation(void);
35 * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
36 * writes to SPEC_CTRL contain whatever reserved bits have been set.
38 u64 __ro_after_init x86_spec_ctrl_base;
39 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
42 * The vendor and possibly platform specific bits which can be modified in
45 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
48 * AMD specific MSR info for Speculative Store Bypass control.
49 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
51 u64 __ro_after_init x86_amd_ls_cfg_base;
52 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
54 void __init check_bugs(void)
58 if (!IS_ENABLED(CONFIG_SMP)) {
60 print_cpu_info(&boot_cpu_data);
64 * Read the SPEC_CTRL MSR to account for reserved bits which may
65 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
66 * init code as it is not enumerated and depends on the family.
68 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
69 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
71 /* Allow STIBP in MSR_SPEC_CTRL if supported */
72 if (boot_cpu_has(X86_FEATURE_STIBP))
73 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
75 /* Select the proper spectre mitigation before patching alternatives */
76 spectre_v2_select_mitigation();
79 * Select proper mitigation for any exposure to the Speculative Store
80 * Bypass vulnerability.
82 ssb_select_mitigation();
86 * Check whether we are able to run this kernel safely on SMP.
88 * - i386 is no longer supported.
89 * - In order to run on anything without a TSC, we need to be
90 * compiled for a i486.
92 if (boot_cpu_data.x86 < 4)
93 panic("Kernel requires i486+ for 'invlpg' and other features");
95 init_utsname()->machine[1] =
96 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
97 alternative_instructions();
99 fpu__init_check_bugs();
100 #else /* CONFIG_X86_64 */
101 alternative_instructions();
104 * Make sure the first 2MB area is not mapped by huge pages
105 * There are typically fixed size MTRRs in there and overlapping
106 * MTRRs into large pages causes slow downs.
108 * Right now we don't do that with gbpages because there seems
109 * very little benefit for that case.
112 set_memory_4k((unsigned long)__va(0), 1);
116 /* The kernel command line selection */
117 enum spectre_v2_mitigation_cmd {
120 SPECTRE_V2_CMD_FORCE,
121 SPECTRE_V2_CMD_RETPOLINE,
122 SPECTRE_V2_CMD_RETPOLINE_GENERIC,
123 SPECTRE_V2_CMD_RETPOLINE_AMD,
126 static const char *spectre_v2_strings[] = {
127 [SPECTRE_V2_NONE] = "Vulnerable",
128 [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline",
129 [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline",
130 [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline",
131 [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline",
135 #define pr_fmt(fmt) "Spectre V2 : " fmt
137 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
141 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
143 u64 msrval, guestval, hostval = x86_spec_ctrl_base;
144 struct thread_info *ti = current_thread_info();
146 /* Is MSR_SPEC_CTRL implemented ? */
147 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
149 * Restrict guest_spec_ctrl to supported values. Clear the
150 * modifiable bits in the host base value and or the
151 * modifiable bits from the guest value.
153 guestval = hostval & ~x86_spec_ctrl_mask;
154 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
156 /* SSBD controlled in MSR_SPEC_CTRL */
157 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
158 hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
160 if (hostval != guestval) {
161 msrval = setguest ? guestval : hostval;
162 wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
167 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
168 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
170 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
171 !static_cpu_has(X86_FEATURE_VIRT_SSBD))
175 * If the host has SSBD mitigation enabled, force it in the host's
176 * virtual MSR value. If its not permanently enabled, evaluate
177 * current's TIF_SSBD thread flag.
179 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
180 hostval = SPEC_CTRL_SSBD;
182 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
184 /* Sanitize the guest value */
185 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
187 if (hostval != guestval) {
190 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
191 ssbd_spec_ctrl_to_tif(hostval);
193 speculative_store_bypass_update(tif);
196 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
198 static void x86_amd_ssb_disable(void)
200 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
202 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
203 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
204 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
205 wrmsrl(MSR_AMD64_LS_CFG, msrval);
209 static bool spectre_v2_bad_module;
211 bool retpoline_module_ok(bool has_retpoline)
213 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
216 pr_err("System may be vulnerable to spectre v2\n");
217 spectre_v2_bad_module = true;
221 static inline const char *spectre_v2_module_string(void)
223 return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
226 static inline const char *spectre_v2_module_string(void) { return ""; }
229 static void __init spec2_print_if_insecure(const char *reason)
231 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
232 pr_info("%s selected on command line.\n", reason);
235 static void __init spec2_print_if_secure(const char *reason)
237 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
238 pr_info("%s selected on command line.\n", reason);
241 static inline bool retp_compiler(void)
243 return __is_defined(RETPOLINE);
246 static inline bool match_option(const char *arg, int arglen, const char *opt)
248 int len = strlen(opt);
250 return len == arglen && !strncmp(arg, opt, len);
253 static const struct {
255 enum spectre_v2_mitigation_cmd cmd;
257 } mitigation_options[] = {
258 { "off", SPECTRE_V2_CMD_NONE, false },
259 { "on", SPECTRE_V2_CMD_FORCE, true },
260 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
261 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false },
262 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
263 { "auto", SPECTRE_V2_CMD_AUTO, false },
266 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
270 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
272 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
273 return SPECTRE_V2_CMD_NONE;
275 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
277 return SPECTRE_V2_CMD_AUTO;
279 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
280 if (!match_option(arg, ret, mitigation_options[i].option))
282 cmd = mitigation_options[i].cmd;
286 if (i >= ARRAY_SIZE(mitigation_options)) {
287 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
288 return SPECTRE_V2_CMD_AUTO;
292 if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
293 cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
294 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
295 !IS_ENABLED(CONFIG_RETPOLINE)) {
296 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
297 return SPECTRE_V2_CMD_AUTO;
300 if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
301 boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
302 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
303 return SPECTRE_V2_CMD_AUTO;
306 if (mitigation_options[i].secure)
307 spec2_print_if_secure(mitigation_options[i].option);
309 spec2_print_if_insecure(mitigation_options[i].option);
314 /* Check for Skylake-like CPUs (for RSB handling) */
315 static bool __init is_skylake_era(void)
317 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
318 boot_cpu_data.x86 == 6) {
319 switch (boot_cpu_data.x86_model) {
320 case INTEL_FAM6_SKYLAKE_MOBILE:
321 case INTEL_FAM6_SKYLAKE_DESKTOP:
322 case INTEL_FAM6_SKYLAKE_X:
323 case INTEL_FAM6_KABYLAKE_MOBILE:
324 case INTEL_FAM6_KABYLAKE_DESKTOP:
331 static void __init spectre_v2_select_mitigation(void)
333 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
334 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
337 * If the CPU is not affected and the command line mode is NONE or AUTO
338 * then nothing to do.
340 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
341 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
345 case SPECTRE_V2_CMD_NONE:
348 case SPECTRE_V2_CMD_FORCE:
349 case SPECTRE_V2_CMD_AUTO:
350 if (IS_ENABLED(CONFIG_RETPOLINE))
353 case SPECTRE_V2_CMD_RETPOLINE_AMD:
354 if (IS_ENABLED(CONFIG_RETPOLINE))
357 case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
358 if (IS_ENABLED(CONFIG_RETPOLINE))
359 goto retpoline_generic;
361 case SPECTRE_V2_CMD_RETPOLINE:
362 if (IS_ENABLED(CONFIG_RETPOLINE))
366 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
370 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
372 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
373 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
374 goto retpoline_generic;
376 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
377 SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
378 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
379 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
382 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
383 SPECTRE_V2_RETPOLINE_MINIMAL;
384 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
387 spectre_v2_enabled = mode;
388 pr_info("%s\n", spectre_v2_strings[mode]);
391 * If neither SMEP nor PTI are available, there is a risk of
392 * hitting userspace addresses in the RSB after a context switch
393 * from a shallow call stack to a deeper one. To prevent this fill
394 * the entire RSB, even when using IBRS.
396 * Skylake era CPUs have a separate issue with *underflow* of the
397 * RSB, when they will predict 'ret' targets from the generic BTB.
398 * The proper mitigation for this is IBRS. If IBRS is not supported
399 * or deactivated in favour of retpolines the RSB fill on context
400 * switch is required.
402 if ((!boot_cpu_has(X86_FEATURE_PTI) &&
403 !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
404 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
405 pr_info("Spectre v2 mitigation: Filling RSB on context switch\n");
408 /* Initialize Indirect Branch Prediction Barrier if supported */
409 if (boot_cpu_has(X86_FEATURE_IBPB)) {
410 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
411 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
415 * Retpoline means the kernel is safe because it has no indirect
416 * branches. But firmware isn't, so use IBRS to protect that.
418 if (boot_cpu_has(X86_FEATURE_IBRS)) {
419 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
420 pr_info("Enabling Restricted Speculation for firmware calls\n");
425 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
427 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
429 /* The kernel command line selection */
430 enum ssb_mitigation_cmd {
431 SPEC_STORE_BYPASS_CMD_NONE,
432 SPEC_STORE_BYPASS_CMD_AUTO,
433 SPEC_STORE_BYPASS_CMD_ON,
434 SPEC_STORE_BYPASS_CMD_PRCTL,
435 SPEC_STORE_BYPASS_CMD_SECCOMP,
438 static const char *ssb_strings[] = {
439 [SPEC_STORE_BYPASS_NONE] = "Vulnerable",
440 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
441 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
442 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
445 static const struct {
447 enum ssb_mitigation_cmd cmd;
448 } ssb_mitigation_options[] = {
449 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
450 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
451 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
452 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
453 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
456 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
458 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
462 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
463 return SPEC_STORE_BYPASS_CMD_NONE;
465 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
468 return SPEC_STORE_BYPASS_CMD_AUTO;
470 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
471 if (!match_option(arg, ret, ssb_mitigation_options[i].option))
474 cmd = ssb_mitigation_options[i].cmd;
478 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
479 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
480 return SPEC_STORE_BYPASS_CMD_AUTO;
487 static enum ssb_mitigation __init __ssb_select_mitigation(void)
489 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
490 enum ssb_mitigation_cmd cmd;
492 if (!boot_cpu_has(X86_FEATURE_SSBD))
495 cmd = ssb_parse_cmdline();
496 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
497 (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
498 cmd == SPEC_STORE_BYPASS_CMD_AUTO))
502 case SPEC_STORE_BYPASS_CMD_AUTO:
503 case SPEC_STORE_BYPASS_CMD_SECCOMP:
505 * Choose prctl+seccomp as the default mode if seccomp is
508 if (IS_ENABLED(CONFIG_SECCOMP))
509 mode = SPEC_STORE_BYPASS_SECCOMP;
511 mode = SPEC_STORE_BYPASS_PRCTL;
513 case SPEC_STORE_BYPASS_CMD_ON:
514 mode = SPEC_STORE_BYPASS_DISABLE;
516 case SPEC_STORE_BYPASS_CMD_PRCTL:
517 mode = SPEC_STORE_BYPASS_PRCTL;
519 case SPEC_STORE_BYPASS_CMD_NONE:
524 * We have three CPU feature flags that are in play here:
525 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
526 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
527 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
529 if (mode == SPEC_STORE_BYPASS_DISABLE) {
530 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
532 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
533 * use a completely different MSR and bit dependent on family.
535 switch (boot_cpu_data.x86_vendor) {
536 case X86_VENDOR_INTEL:
538 if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
539 x86_amd_ssb_disable();
542 x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
543 x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
544 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
552 static void ssb_select_mitigation(void)
554 ssb_mode = __ssb_select_mitigation();
556 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
557 pr_info("%s\n", ssb_strings[ssb_mode]);
561 #define pr_fmt(fmt) "Speculation prctl: " fmt
563 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
567 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
568 ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
573 /* If speculation is force disabled, enable is not allowed */
574 if (task_spec_ssb_force_disable(task))
576 task_clear_spec_ssb_disable(task);
577 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
579 case PR_SPEC_DISABLE:
580 task_set_spec_ssb_disable(task);
581 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
583 case PR_SPEC_FORCE_DISABLE:
584 task_set_spec_ssb_disable(task);
585 task_set_spec_ssb_force_disable(task);
586 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
593 * If being set on non-current task, delay setting the CPU
594 * mitigation until it is next scheduled.
596 if (task == current && update)
597 speculative_store_bypass_update_current();
602 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
606 case PR_SPEC_STORE_BYPASS:
607 return ssb_prctl_set(task, ctrl);
613 #ifdef CONFIG_SECCOMP
614 void arch_seccomp_spec_mitigate(struct task_struct *task)
616 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
617 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
621 static int ssb_prctl_get(struct task_struct *task)
624 case SPEC_STORE_BYPASS_DISABLE:
625 return PR_SPEC_DISABLE;
626 case SPEC_STORE_BYPASS_SECCOMP:
627 case SPEC_STORE_BYPASS_PRCTL:
628 if (task_spec_ssb_force_disable(task))
629 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
630 if (task_spec_ssb_disable(task))
631 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
632 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
634 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
635 return PR_SPEC_ENABLE;
636 return PR_SPEC_NOT_AFFECTED;
640 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
643 case PR_SPEC_STORE_BYPASS:
644 return ssb_prctl_get(task);
650 void x86_spec_ctrl_setup_ap(void)
652 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
653 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
655 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
656 x86_amd_ssb_disable();
661 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
662 char *buf, unsigned int bug)
664 if (!boot_cpu_has_bug(bug))
665 return sprintf(buf, "Not affected\n");
668 case X86_BUG_CPU_MELTDOWN:
669 if (boot_cpu_has(X86_FEATURE_PTI))
670 return sprintf(buf, "Mitigation: PTI\n");
674 case X86_BUG_SPECTRE_V1:
675 return sprintf(buf, "Mitigation: __user pointer sanitization\n");
677 case X86_BUG_SPECTRE_V2:
678 return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
679 boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "",
680 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
681 spectre_v2_module_string());
683 case X86_BUG_SPEC_STORE_BYPASS:
684 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
690 return sprintf(buf, "Vulnerable\n");
693 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
695 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
698 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
700 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
703 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
705 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
708 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
710 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);