1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/export.h>
3 #include <linux/bitops.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/random.h>
11 #include <linux/topology.h>
12 #include <asm/processor.h>
14 #include <asm/cacheinfo.h>
16 #include <asm/spec-ctrl.h>
19 #include <asm/pci-direct.h>
20 #include <asm/delay.h>
21 #include <asm/debugreg.h>
22 #include <asm/resctrl.h>
25 # include <asm/mmconfig.h>
31 * nodes_per_socket: Stores the number of nodes per socket.
32 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
33 * Node Identifiers[10:8]
35 static u32 nodes_per_socket = 1;
40 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
41 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
42 * have an OSVW id assigned, which it takes as first argument. Both take a
43 * variable number of family-specific model-stepping ranges created by
48 * const int amd_erratum_319[] =
49 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
50 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
51 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
54 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
55 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
56 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
57 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
58 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
59 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
60 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
62 static const int amd_erratum_400[] =
63 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
64 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
66 static const int amd_erratum_383[] =
67 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
69 /* #1054: Instructions Retired Performance Counter May Be Inaccurate */
70 static const int amd_erratum_1054[] =
71 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
73 static const int amd_zenbleed[] =
74 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),
75 AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),
76 AMD_MODEL_RANGE(0x17, 0x90, 0x0, 0x91, 0xf),
77 AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
79 static const int amd_div0[] =
80 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x00, 0x0, 0x2f, 0xf),
81 AMD_MODEL_RANGE(0x17, 0x50, 0x0, 0x5f, 0xf));
83 static const int amd_erratum_1485[] =
84 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
85 AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));
87 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
89 int osvw_id = *erratum++;
93 if (osvw_id >= 0 && osvw_id < 65536 &&
94 cpu_has(cpu, X86_FEATURE_OSVW)) {
97 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
98 if (osvw_id < osvw_len) {
101 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
103 return osvw_bits & (1ULL << (osvw_id & 0x3f));
107 /* OSVW unavailable or ID unknown, match family-model-stepping range */
108 ms = (cpu->x86_model << 4) | cpu->x86_stepping;
109 while ((range = *erratum++))
110 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
111 (ms >= AMD_MODEL_RANGE_START(range)) &&
112 (ms <= AMD_MODEL_RANGE_END(range)))
118 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
123 WARN_ONCE((boot_cpu_data.x86 != 0xf),
124 "%s should only be used on K8!\n", __func__);
127 gprs[7] = 0x9c5a203a;
129 err = rdmsr_safe_regs(gprs);
131 *p = gprs[0] | ((u64)gprs[2] << 32);
136 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
140 WARN_ONCE((boot_cpu_data.x86 != 0xf),
141 "%s should only be used on K8!\n", __func__);
146 gprs[7] = 0x9c5a203a;
148 return wrmsr_safe_regs(gprs);
152 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
153 * misexecution of code under Linux. Owners of such processors should
154 * contact AMD for precise details and a CPU swap.
156 * See http://www.multimania.com/poulot/k6bug.html
157 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
158 * (Publication # 21266 Issue Date: August 1998)
160 * The following test is erm.. interesting. AMD neglected to up
161 * the chip setting when fixing the bug but they also tweaked some
162 * performance at the same time..
166 extern __visible void vide(void);
169 ".type vide, @function\n"
174 static void init_amd_k5(struct cpuinfo_x86 *c)
178 * General Systems BIOSen alias the cpu frequency registers
179 * of the Elan at 0x000df000. Unfortunately, one of the Linux
180 * drivers subsequently pokes it, and changes the CPU speed.
181 * Workaround : Remove the unneeded alias.
183 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
184 #define CBAR_ENB (0x80000000)
185 #define CBAR_KEY (0X000000CB)
186 if (c->x86_model == 9 || c->x86_model == 10) {
187 if (inl(CBAR) & CBAR_ENB)
188 outl(0 | CBAR_KEY, CBAR);
193 static void init_amd_k6(struct cpuinfo_x86 *c)
197 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
199 if (c->x86_model < 6) {
200 /* Based on AMD doc 20734R - June 2000 */
201 if (c->x86_model == 0) {
202 clear_cpu_cap(c, X86_FEATURE_APIC);
203 set_cpu_cap(c, X86_FEATURE_PGE);
208 if (c->x86_model == 6 && c->x86_stepping == 1) {
209 const int K6_BUG_LOOP = 1000000;
211 void (*f_vide)(void);
214 pr_info("AMD K6 stepping B detected - ");
217 * It looks like AMD fixed the 2.6.2 bug and improved indirect
218 * calls at the same time.
223 OPTIMIZER_HIDE_VAR(f_vide);
230 if (d > 20*K6_BUG_LOOP)
231 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
233 pr_cont("probably OK (after B9730xxxx).\n");
236 /* K6 with old style WHCR */
237 if (c->x86_model < 8 ||
238 (c->x86_model == 8 && c->x86_stepping < 8)) {
239 /* We can only write allocate on the low 508Mb */
243 rdmsr(MSR_K6_WHCR, l, h);
244 if ((l&0x0000FFFF) == 0) {
246 l = (1<<0)|((mbytes/4)<<1);
247 local_irq_save(flags);
249 wrmsr(MSR_K6_WHCR, l, h);
250 local_irq_restore(flags);
251 pr_info("Enabling old style K6 write allocation for %d Mb\n",
257 if ((c->x86_model == 8 && c->x86_stepping > 7) ||
258 c->x86_model == 9 || c->x86_model == 13) {
259 /* The more serious chips .. */
264 rdmsr(MSR_K6_WHCR, l, h);
265 if ((l&0xFFFF0000) == 0) {
267 l = ((mbytes>>2)<<22)|(1<<16);
268 local_irq_save(flags);
270 wrmsr(MSR_K6_WHCR, l, h);
271 local_irq_restore(flags);
272 pr_info("Enabling new style K6 write allocation for %d Mb\n",
279 if (c->x86_model == 10) {
280 /* AMD Geode LX is model 10 */
281 /* placeholder for any needed mods */
287 static void init_amd_k7(struct cpuinfo_x86 *c)
293 * Bit 15 of Athlon specific MSR 15, needs to be 0
294 * to enable SSE on Palomino/Morgan/Barton CPU's.
295 * If the BIOS didn't enable it already, enable it here.
297 if (c->x86_model >= 6 && c->x86_model <= 10) {
298 if (!cpu_has(c, X86_FEATURE_XMM)) {
299 pr_info("Enabling disabled K7/SSE Support.\n");
300 msr_clear_bit(MSR_K7_HWCR, 15);
301 set_cpu_cap(c, X86_FEATURE_XMM);
306 * It's been determined by AMD that Athlons since model 8 stepping 1
307 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
308 * As per AMD technical note 27212 0.2
310 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
311 rdmsr(MSR_K7_CLK_CTL, l, h);
312 if ((l & 0xfff00000) != 0x20000000) {
313 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
314 l, ((l & 0x000fffff)|0x20000000));
315 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
319 /* calling is from identify_secondary_cpu() ? */
324 * Certain Athlons might work (for various values of 'work') in SMP
325 * but they are not certified as MP capable.
327 /* Athlon 660/661 is valid. */
328 if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
329 (c->x86_stepping == 1)))
332 /* Duron 670 is valid */
333 if ((c->x86_model == 7) && (c->x86_stepping == 0))
337 * Athlon 662, Duron 671, and Athlon >model 7 have capability
338 * bit. It's worth noting that the A5 stepping (662) of some
339 * Athlon XP's have the MP bit set.
340 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
343 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
344 ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
346 if (cpu_has(c, X86_FEATURE_MP))
349 /* If we get here, not a certified SMP capable AMD system. */
352 * Don't taint if we are running SMP kernel on a single non-MP
355 WARN_ONCE(1, "WARNING: This combination of AMD"
356 " processors is not suitable for SMP.\n");
357 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
363 * To workaround broken NUMA config. Read the comment in
364 * srat_detect_node().
366 static int nearby_node(int apicid)
370 for (i = apicid - 1; i >= 0; i--) {
371 node = __apicid_to_node[i];
372 if (node != NUMA_NO_NODE && node_online(node))
375 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
376 node = __apicid_to_node[i];
377 if (node != NUMA_NO_NODE && node_online(node))
380 return first_node(node_online_map); /* Shouldn't happen */
385 * Fix up cpu_core_id for pre-F17h systems to be in the
386 * [0 .. cores_per_node - 1] range. Not really needed but
387 * kept so as not to break existing setups.
389 static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
396 cus_per_node = c->x86_max_cores / nodes_per_socket;
397 c->cpu_core_id %= cus_per_node;
401 * Fixup core topology information for
402 * (1) AMD multi-node processors
403 * Assumption: Number of cores in each internal node is the same.
404 * (2) AMD processors supporting compute units
406 static void amd_get_topology(struct cpuinfo_x86 *c)
408 int cpu = smp_processor_id();
410 /* get information required for multi-node processors */
411 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
413 u32 eax, ebx, ecx, edx;
415 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
417 c->cpu_die_id = ecx & 0xff;
420 c->cu_id = ebx & 0xff;
422 if (c->x86 >= 0x17) {
423 c->cpu_core_id = ebx & 0xff;
425 if (smp_num_siblings > 1)
426 c->x86_max_cores /= smp_num_siblings;
430 * In case leaf B is available, use it to derive
431 * topology information.
433 err = detect_extended_topology(c);
435 c->x86_coreid_bits = get_count_order(c->x86_max_cores);
437 cacheinfo_amd_init_llc_id(c, cpu);
439 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
442 rdmsrl(MSR_FAM10H_NODE_ID, value);
443 c->cpu_die_id = value & 7;
445 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
449 if (nodes_per_socket > 1) {
450 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
451 legacy_fixup_core_id(c);
456 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
457 * Assumes number of cores is a power of two.
459 static void amd_detect_cmp(struct cpuinfo_x86 *c)
462 int cpu = smp_processor_id();
464 bits = c->x86_coreid_bits;
465 /* Low order bits define the core id (index of core in socket) */
466 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
467 /* Convert the initial APIC ID into the socket ID */
468 c->phys_proc_id = c->initial_apicid >> bits;
469 /* use socket ID also for last level cache */
470 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
473 u32 amd_get_nodes_per_socket(void)
475 return nodes_per_socket;
477 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
479 static void srat_detect_node(struct cpuinfo_x86 *c)
482 int cpu = smp_processor_id();
484 unsigned apicid = c->apicid;
486 node = numa_cpu_node(cpu);
487 if (node == NUMA_NO_NODE)
488 node = get_llc_id(cpu);
491 * On multi-fabric platform (e.g. Numascale NumaChip) a
492 * platform-specific handler needs to be called to fixup some
495 if (x86_cpuinit.fixup_cpu_id)
496 x86_cpuinit.fixup_cpu_id(c, node);
498 if (!node_online(node)) {
500 * Two possibilities here:
502 * - The CPU is missing memory and no node was created. In
503 * that case try picking one from a nearby CPU.
505 * - The APIC IDs differ from the HyperTransport node IDs
506 * which the K8 northbridge parsing fills in. Assume
507 * they are all increased by a constant offset, but in
508 * the same order as the HT nodeids. If that doesn't
509 * result in a usable node fall back to the path for the
512 * This workaround operates directly on the mapping between
513 * APIC ID and NUMA node, assuming certain relationship
514 * between APIC ID, HT node ID and NUMA topology. As going
515 * through CPU mapping may alter the outcome, directly
516 * access __apicid_to_node[].
518 int ht_nodeid = c->initial_apicid;
520 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
521 node = __apicid_to_node[ht_nodeid];
522 /* Pick a nearby node */
523 if (!node_online(node))
524 node = nearby_node(apicid);
526 numa_set_node(cpu, node);
530 static void early_init_amd_mc(struct cpuinfo_x86 *c)
535 /* Multi core CPU? */
536 if (c->extended_cpuid_level < 0x80000008)
539 ecx = cpuid_ecx(0x80000008);
541 c->x86_max_cores = (ecx & 0xff) + 1;
543 /* CPU telling us the core id bits shift? */
544 bits = (ecx >> 12) & 0xF;
546 /* Otherwise recompute */
548 while ((1 << bits) < c->x86_max_cores)
552 c->x86_coreid_bits = bits;
556 static void bsp_init_amd(struct cpuinfo_x86 *c)
558 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
561 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
564 rdmsrl(MSR_K7_HWCR, val);
565 if (!(val & BIT(24)))
566 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
570 if (c->x86 == 0x15) {
571 unsigned long upperbit;
574 cpuid = cpuid_edx(0x80000005);
575 assoc = cpuid >> 16 & 0xff;
576 upperbit = ((cpuid >> 24) << 10) / assoc;
578 va_align.mask = (upperbit - 1) & PAGE_MASK;
579 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
581 /* A random value per boot for bit slice [12:upper_bit) */
582 va_align.bits = get_random_u32() & va_align.mask;
585 if (cpu_has(c, X86_FEATURE_MWAITX))
588 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
591 ecx = cpuid_ecx(0x8000001e);
592 __max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1;
593 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
596 rdmsrl(MSR_FAM10H_NODE_ID, value);
597 __max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1;
600 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
601 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
602 c->x86 >= 0x15 && c->x86 <= 0x17) {
606 case 0x15: bit = 54; break;
607 case 0x16: bit = 33; break;
608 case 0x17: bit = 10; break;
612 * Try to cache the base value so further operations can
613 * avoid RMW. If that faults, do not enable SSBD.
615 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
616 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
617 setup_force_cpu_cap(X86_FEATURE_SSBD);
618 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
622 resctrl_cpu_detect(c);
625 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
630 * BIOS support is required for SME and SEV.
631 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by
632 * the SME physical address space reduction value.
633 * If BIOS has not enabled SME then don't advertise the
634 * SME feature (set in scattered.c).
635 * If the kernel has not enabled SME via any means then
636 * don't advertise the SME feature.
637 * For SEV: If BIOS has not enabled SEV then don't advertise the
638 * SEV and SEV_ES feature (set in scattered.c).
640 * In all cases, since support for SME and SEV requires long mode,
641 * don't advertise the feature under CONFIG_X86_32.
643 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
644 /* Check if memory encryption is enabled */
645 rdmsrl(MSR_AMD64_SYSCFG, msr);
646 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
650 * Always adjust physical address bits. Even though this
651 * will be a value above 32-bits this is still done for
652 * CONFIG_X86_32 so that accurate values are reported.
654 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
656 if (IS_ENABLED(CONFIG_X86_32))
660 setup_clear_cpu_cap(X86_FEATURE_SME);
662 rdmsrl(MSR_K7_HWCR, msr);
663 if (!(msr & MSR_K7_HWCR_SMMLOCK))
669 setup_clear_cpu_cap(X86_FEATURE_SME);
671 setup_clear_cpu_cap(X86_FEATURE_SEV);
672 setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
676 static void early_init_amd(struct cpuinfo_x86 *c)
681 early_init_amd_mc(c);
684 set_cpu_cap(c, X86_FEATURE_K8);
686 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
689 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
690 * with P/T states and does not stop in deep C-states
692 if (c->x86_power & (1 << 8)) {
693 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
694 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
697 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
698 if (c->x86_power & BIT(12))
699 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
701 /* Bit 14 indicates the Runtime Average Power Limit interface. */
702 if (c->x86_power & BIT(14))
703 set_cpu_cap(c, X86_FEATURE_RAPL);
706 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
708 /* Set MTRR capability flag if appropriate */
710 if (c->x86_model == 13 || c->x86_model == 9 ||
711 (c->x86_model == 8 && c->x86_stepping >= 8))
712 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
714 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
716 * ApicID can always be treated as an 8-bit value for AMD APIC versions
717 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
718 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
721 if (boot_cpu_has(X86_FEATURE_APIC)) {
723 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
724 else if (c->x86 >= 0xf) {
725 /* check CPU config space for extended APIC ID */
728 val = read_pci_config(0, 24, 0, 0x68);
729 if ((val >> 17 & 0x3) == 0x3)
730 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
736 * This is only needed to tell the kernel whether to use VMCALL
737 * and VMMCALL. VMMCALL is never executed except under virt, so
738 * we can set it unconditionally.
740 set_cpu_cap(c, X86_FEATURE_VMMCALL);
742 /* F16h erratum 793, CVE-2013-6885 */
743 if (c->x86 == 0x16 && c->x86_model <= 0xf)
744 msr_set_bit(MSR_AMD64_LS_CFG, 15);
747 * Check whether the machine is affected by erratum 400. This is
748 * used to select the proper idle routine and to enable the check
749 * whether the machine is affected in arch_post_acpi_init(), which
750 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
752 if (cpu_has_amd_erratum(c, amd_erratum_400))
753 set_cpu_bug(c, X86_BUG_AMD_E400);
755 early_detect_mem_encrypt(c);
757 /* Re-enable TopologyExtensions if switched off by BIOS */
758 if (c->x86 == 0x15 &&
759 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) &&
760 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
762 if (msr_set_bit(0xc0011005, 54) > 0) {
763 rdmsrl(0xc0011005, value);
764 if (value & BIT_64(54)) {
765 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
766 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
771 if (cpu_has(c, X86_FEATURE_TOPOEXT))
772 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
774 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_IBPB_BRTYPE)) {
775 if (c->x86 == 0x17 && boot_cpu_has(X86_FEATURE_AMD_IBPB))
776 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE);
777 else if (c->x86 >= 0x19 && !wrmsrl_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) {
778 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE);
779 setup_force_cpu_cap(X86_FEATURE_SBPB);
784 static void init_amd_k8(struct cpuinfo_x86 *c)
789 /* On C+ stepping K8 rep microcode works well for copy/memset */
790 level = cpuid_eax(1);
791 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
792 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
795 * Some BIOSes incorrectly force this feature, but only K8 revision D
796 * (model = 0x14) and later actually support it.
797 * (AMD Erratum #110, docId: 25759).
799 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
800 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
801 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
802 value &= ~BIT_64(32);
803 wrmsrl_amd_safe(0xc001100d, value);
807 if (!c->x86_model_id[0])
808 strcpy(c->x86_model_id, "Hammer");
812 * Disable TLB flush filter by setting HWCR.FFDIS on K8
813 * bit 6 of msr C001_0015
815 * Errata 63 for SH-B3 steppings
816 * Errata 122 for all steppings (F+ have it disabled by default)
818 msr_set_bit(MSR_K7_HWCR, 6);
820 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
823 static void init_amd_gh(struct cpuinfo_x86 *c)
825 #ifdef CONFIG_MMCONF_FAM10H
826 /* do this for boot cpu */
827 if (c == &boot_cpu_data)
828 check_enable_amd_mmconf_dmi();
830 fam10h_check_enable_mmcfg();
834 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
835 * is always needed when GART is enabled, even in a kernel which has no
836 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
837 * If it doesn't, we do it here as suggested by the BKDG.
839 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
841 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
844 * On family 10h BIOS may not have properly enabled WC+ support, causing
845 * it to be converted to CD memtype. This may result in performance
846 * degradation for certain nested-paging guests. Prevent this conversion
847 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
849 * NOTE: we want to use the _safe accessors so as not to #GP kvm
850 * guests on older kvm hosts.
852 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
854 if (cpu_has_amd_erratum(c, amd_erratum_383))
855 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
858 static void init_amd_ln(struct cpuinfo_x86 *c)
861 * Apply erratum 665 fix unconditionally so machines without a BIOS
864 msr_set_bit(MSR_AMD64_DE_CFG, 31);
867 static bool rdrand_force;
869 static int __init rdrand_cmdline(char *str)
874 if (!strcmp(str, "force"))
881 early_param("rdrand", rdrand_cmdline);
883 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c)
886 * Saving of the MSR used to hide the RDRAND support during
887 * suspend/resume is done by arch/x86/power/cpu.c, which is
888 * dependent on CONFIG_PM_SLEEP.
890 if (!IS_ENABLED(CONFIG_PM_SLEEP))
894 * The self-test can clear X86_FEATURE_RDRAND, so check for
895 * RDRAND support using the CPUID function directly.
897 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force)
900 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62);
903 * Verify that the CPUID change has occurred in case the kernel is
904 * running virtualized and the hypervisor doesn't support the MSR.
906 if (cpuid_ecx(1) & BIT(30)) {
907 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n");
911 clear_cpu_cap(c, X86_FEATURE_RDRAND);
912 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n");
915 static void init_amd_jg(struct cpuinfo_x86 *c)
918 * Some BIOS implementations do not restore proper RDRAND support
919 * across suspend and resume. Check on whether to hide the RDRAND
920 * instruction support via CPUID.
922 clear_rdrand_cpuid_bit(c);
925 static void init_amd_bd(struct cpuinfo_x86 *c)
930 * The way access filter has a performance penalty on some workloads.
931 * Disable it on the affected CPUs.
933 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
934 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
936 wrmsrl_safe(MSR_F15H_IC_CFG, value);
941 * Some BIOS implementations do not restore proper RDRAND support
942 * across suspend and resume. Check on whether to hide the RDRAND
943 * instruction support via CPUID.
945 clear_rdrand_cpuid_bit(c);
948 void init_spectral_chicken(struct cpuinfo_x86 *c)
950 #ifdef CONFIG_CPU_UNRET_ENTRY
954 * On Zen2 we offer this chicken (bit) on the altar of Speculation.
956 * This suppresses speculation from the middle of a basic block, i.e. it
957 * suppresses non-branch predictions.
959 * We use STIBP as a heuristic to filter out Zen2 from the rest of F17H
961 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_AMD_STIBP)) {
962 if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) {
963 value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT;
964 wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value);
969 * Work around Erratum 1386. The XSAVES instruction malfunctions in
970 * certain circumstances on Zen1/2 uarch, and not all parts have had
971 * updated microcode at the time of writing (March 2023).
973 * Affected parts all have no supervisor XSAVE states, meaning that
974 * the XSAVEC instruction (which works fine) is equivalent.
976 clear_cpu_cap(c, X86_FEATURE_XSAVES);
979 static void init_amd_zn(struct cpuinfo_x86 *c)
981 set_cpu_cap(c, X86_FEATURE_ZEN);
984 node_reclaim_distance = 32;
987 /* Fix up CPUID bits, but only if not virtualised. */
988 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
990 /* Erratum 1076: CPB feature bit not being set in CPUID. */
991 if (!cpu_has(c, X86_FEATURE_CPB))
992 set_cpu_cap(c, X86_FEATURE_CPB);
995 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
996 * Branch Type Confusion, but predate the allocation of the
999 if (c->x86 == 0x19 && !cpu_has(c, X86_FEATURE_BTC_NO))
1000 set_cpu_cap(c, X86_FEATURE_BTC_NO);
1004 static bool cpu_has_zenbleed_microcode(void)
1008 switch (boot_cpu_data.x86_model) {
1009 case 0x30 ... 0x3f: good_rev = 0x0830107a; break;
1010 case 0x60 ... 0x67: good_rev = 0x0860010b; break;
1011 case 0x68 ... 0x6f: good_rev = 0x08608105; break;
1012 case 0x70 ... 0x7f: good_rev = 0x08701032; break;
1013 case 0xa0 ... 0xaf: good_rev = 0x08a00008; break;
1020 if (boot_cpu_data.microcode < good_rev)
1026 static void zenbleed_check(struct cpuinfo_x86 *c)
1028 if (!cpu_has_amd_erratum(c, amd_zenbleed))
1031 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
1034 if (!cpu_has(c, X86_FEATURE_AVX))
1037 if (!cpu_has_zenbleed_microcode()) {
1038 pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
1039 msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
1041 msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
1045 static void init_amd(struct cpuinfo_x86 *c)
1050 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
1051 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
1053 clear_cpu_cap(c, 0*32+31);
1056 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
1058 /* AMD FSRM also implies FSRS */
1059 if (cpu_has(c, X86_FEATURE_FSRM))
1060 set_cpu_cap(c, X86_FEATURE_FSRS);
1062 /* get apicid instead of initial apic id from cpuid */
1063 c->apicid = read_apic_id();
1065 /* K6s reports MCEs but don't actually have all the MSRs */
1067 clear_cpu_cap(c, X86_FEATURE_MCE);
1070 case 4: init_amd_k5(c); break;
1071 case 5: init_amd_k6(c); break;
1072 case 6: init_amd_k7(c); break;
1073 case 0xf: init_amd_k8(c); break;
1074 case 0x10: init_amd_gh(c); break;
1075 case 0x12: init_amd_ln(c); break;
1076 case 0x15: init_amd_bd(c); break;
1077 case 0x16: init_amd_jg(c); break;
1078 case 0x17: init_spectral_chicken(c);
1080 case 0x19: init_amd_zn(c); break;
1084 * Enable workaround for FXSAVE leak on CPUs
1085 * without a XSaveErPtr feature
1087 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))
1088 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
1090 cpu_detect_cache_sizes(c);
1093 amd_get_topology(c);
1094 srat_detect_node(c);
1096 init_amd_cacheinfo(c);
1098 if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) {
1100 * Use LFENCE for execution serialization. On families which
1101 * don't have that MSR, LFENCE is already serializing.
1102 * msr_set_bit() uses the safe accessors, too, even if the MSR
1105 msr_set_bit(MSR_AMD64_DE_CFG,
1106 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
1108 /* A serializing LFENCE stops RDTSC speculation */
1109 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
1113 * Family 0x12 and above processors have APIC timer
1114 * running in deep C states.
1117 set_cpu_cap(c, X86_FEATURE_ARAT);
1119 /* 3DNow or LM implies PREFETCHW */
1120 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
1121 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
1122 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
1124 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
1125 if (!cpu_feature_enabled(X86_FEATURE_XENPV))
1126 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
1129 * Turn on the Instructions Retired free counter on machines not
1130 * susceptible to erratum #1054 "Instructions Retired Performance
1131 * Counter May Be Inaccurate".
1133 if (cpu_has(c, X86_FEATURE_IRPERF) &&
1134 !cpu_has_amd_erratum(c, amd_erratum_1054))
1135 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
1137 check_null_seg_clears_base(c);
1140 * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up
1141 * using the trampoline code and as part of it, MSR_EFER gets prepared there in
1142 * order to be replicated onto them. Regardless, set it here again, if not set,
1143 * to protect against any future refactoring/code reorganization which might
1144 * miss setting this important bit.
1146 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
1147 cpu_has(c, X86_FEATURE_AUTOIBRS))
1148 WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS));
1152 if (cpu_has_amd_erratum(c, amd_div0)) {
1153 pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");
1154 setup_force_cpu_bug(X86_BUG_DIV0);
1157 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
1158 cpu_has_amd_erratum(c, amd_erratum_1485))
1159 msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
1162 #ifdef CONFIG_X86_32
1163 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1165 /* AMD errata T13 (order #21922) */
1168 if (c->x86_model == 3 && c->x86_stepping == 0)
1170 /* Tbird rev A1/A2 */
1171 if (c->x86_model == 4 &&
1172 (c->x86_stepping == 0 || c->x86_stepping == 1))
1179 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
1181 u32 ebx, eax, ecx, edx;
1187 if (c->extended_cpuid_level < 0x80000006)
1190 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1192 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
1193 tlb_lli_4k[ENTRIES] = ebx & mask;
1196 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
1197 * characteristics from the CPUID function 0x80000005 instead.
1199 if (c->x86 == 0xf) {
1200 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1204 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1205 if (!((eax >> 16) & mask))
1206 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
1208 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
1210 /* a 4M entry uses two 2M entries */
1211 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
1213 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1214 if (!(eax & mask)) {
1216 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
1217 tlb_lli_2m[ENTRIES] = 1024;
1219 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1220 tlb_lli_2m[ENTRIES] = eax & 0xff;
1223 tlb_lli_2m[ENTRIES] = eax & mask;
1225 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
1228 static const struct cpu_dev amd_cpu_dev = {
1230 .c_ident = { "AuthenticAMD" },
1231 #ifdef CONFIG_X86_32
1233 { .family = 4, .model_names =
1236 [7] = "486 DX/2-WB",
1238 [9] = "486 DX/4-WB",
1244 .legacy_cache_size = amd_size_cache,
1246 .c_early_init = early_init_amd,
1247 .c_detect_tlb = cpu_detect_tlb_amd,
1248 .c_bsp_init = bsp_init_amd,
1250 .c_x86_vendor = X86_VENDOR_AMD,
1253 cpu_dev_register(amd_cpu_dev);
1255 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask);
1257 static unsigned int amd_msr_dr_addr_masks[] = {
1258 MSR_F16H_DR0_ADDR_MASK,
1259 MSR_F16H_DR1_ADDR_MASK,
1260 MSR_F16H_DR1_ADDR_MASK + 1,
1261 MSR_F16H_DR1_ADDR_MASK + 2
1264 void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr)
1266 int cpu = smp_processor_id();
1268 if (!cpu_feature_enabled(X86_FEATURE_BPEXT))
1271 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks)))
1274 if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask)
1277 wrmsr(amd_msr_dr_addr_masks[dr], mask, 0);
1278 per_cpu(amd_dr_addr_mask, cpu)[dr] = mask;
1281 unsigned long amd_get_dr_addr_mask(unsigned int dr)
1283 if (!cpu_feature_enabled(X86_FEATURE_BPEXT))
1286 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks)))
1289 return per_cpu(amd_dr_addr_mask[dr], smp_processor_id());
1291 EXPORT_SYMBOL_GPL(amd_get_dr_addr_mask);
1293 u32 amd_get_highest_perf(void)
1295 struct cpuinfo_x86 *c = &boot_cpu_data;
1297 if (c->x86 == 0x17 && ((c->x86_model >= 0x30 && c->x86_model < 0x40) ||
1298 (c->x86_model >= 0x70 && c->x86_model < 0x80)))
1301 if (c->x86 == 0x19 && ((c->x86_model >= 0x20 && c->x86_model < 0x30) ||
1302 (c->x86_model >= 0x40 && c->x86_model < 0x70)))
1307 EXPORT_SYMBOL_GPL(amd_get_highest_perf);
1309 static void zenbleed_check_cpu(void *unused)
1311 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
1316 void amd_check_microcode(void)
1318 on_each_cpu(zenbleed_check_cpu, NULL, 1);
1322 * Issue a DIV 0/1 insn to clear any division data from previous DIV
1325 void noinstr amd_clear_divider(void)
1327 asm volatile(ALTERNATIVE("", "div %2\n\t", X86_BUG_DIV0)
1328 :: "a" (0), "d" (0), "r" (1));
1330 EXPORT_SYMBOL_GPL(amd_clear_divider);