arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/slab.h>
  21 #include <linux/cpu.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdebug.h>
  26 #include <linux/delay.h>
  27 #include <linux/crash_dump.h>
  28 #include <linux/reboot.h>
  29
  30 #include <asm/uv/uv_mmrs.h>
  31 #include <asm/uv/uv_hub.h>
  32 #include <asm/current.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/uv/bios.h>
  35 #include <asm/uv/uv.h>
  36 #include <asm/apic.h>
  37 #include <asm/ipi.h>
  38 #include <asm/smp.h>
  39 #include <asm/x86_init.h>
  40 #include <asm/nmi.h>
  41
  42 DEFINE_PER_CPU(int, x2apic_extra_bits);
  43
  44 #define PR_DEVEL(fmt, args...)  pr_devel("%s: " fmt, __func__, args)
  45
  46 static enum uv_system_type uv_system_type;
  47 static u64 gru_start_paddr, gru_end_paddr;
  48 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
  49 static u64 gru_dist_lmask, gru_dist_umask;
  50 static union uvh_apicid uvh_apicid;
  51
  52 /* info derived from CPUID */
  53 static struct {
  54         unsigned int apicid_shift;
  55         unsigned int apicid_mask;
  56         unsigned int socketid_shift;    /* aka pnode_shift for UV1/2/3 */
  57         unsigned int pnode_mask;
  58         unsigned int gpa_shift;
  59 } uv_cpuid;
  60
  61 int uv_min_hub_revision_id;
  62 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
  63 unsigned int uv_apicid_hibits;
  64 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
  65
  66 static struct apic apic_x2apic_uv_x;
  67 static struct uv_hub_info_s uv_hub_info_node0;
  68
  69 /* Set this to use hardware error handler instead of kernel panic */
  70 static int disable_uv_undefined_panic = 1;
  71 unsigned long uv_undefined(char *str)
  72 {
  73         if (likely(!disable_uv_undefined_panic))
  74                 panic("UV: error: undefined MMR: %s\n", str);
  75         else
  76                 pr_crit("UV: error: undefined MMR: %s\n", str);
  77         return ~0ul;    /* cause a machine fault  */
  78 }
  79 EXPORT_SYMBOL(uv_undefined);
  80
  81 static unsigned long __init uv_early_read_mmr(unsigned long addr)
  82 {
  83         unsigned long val, *mmr;
  84
  85         mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
  86         val = *mmr;
  87         early_iounmap(mmr, sizeof(*mmr));
  88         return val;
  89 }
  90
  91 static inline bool is_GRU_range(u64 start, u64 end)
  92 {
  93         if (gru_dist_base) {
  94                 u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */
  95                 u64 sl = start & gru_dist_lmask; /* base offset bits */
  96                 u64 eu = end & gru_dist_umask;
  97                 u64 el = end & gru_dist_lmask;
  98
  99                 /* Must reside completely within a single GRU range */
 100                 return (sl == gru_dist_base && el == gru_dist_base &&
 101                         su >= gru_first_node_paddr &&
 102                         su <= gru_last_node_paddr &&
 103                         eu == su);
 104         } else {
 105                 return start >= gru_start_paddr && end <= gru_end_paddr;
 106         }
 107 }
 108
 109 static bool uv_is_untracked_pat_range(u64 start, u64 end)
 110 {
 111         return is_ISA_range(start, end) || is_GRU_range(start, end);
 112 }
 113
 114 static int __init early_get_pnodeid(void)
 115 {
 116         union uvh_node_id_u node_id;
 117         union uvh_rh_gam_config_mmr_u  m_n_config;
 118         int pnode;
 119
 120         /* Currently, all blades have same revision number */
 121         node_id.v = uv_early_read_mmr(UVH_NODE_ID);
 122         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
 123         uv_min_hub_revision_id = node_id.s.revision;
 124
 125         switch (node_id.s.part_number) {
 126         case UV2_HUB_PART_NUMBER:
 127         case UV2_HUB_PART_NUMBER_X:
 128                 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
 129                 break;
 130         case UV3_HUB_PART_NUMBER:
 131         case UV3_HUB_PART_NUMBER_X:
 132                 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
 133                 break;
 134         case UV4_HUB_PART_NUMBER:
 135                 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
 136                 break;
 137         }
 138
 139         uv_hub_info->hub_revision = uv_min_hub_revision_id;
 140         uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
 141         pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
 142         uv_cpuid.gpa_shift = 46;        /* default unless changed */
 143
 144         pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
 145                 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
 146                 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
 147         return pnode;
 148 }
 149
 150 /* [copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
 151 #define SMT_LEVEL       0       /* leaf 0xb SMT level */
 152 #define INVALID_TYPE    0       /* leaf 0xb sub-leaf types */
 153 #define SMT_TYPE        1
 154 #define CORE_TYPE       2
 155 #define LEAFB_SUBTYPE(ecx)              (((ecx) >> 8) & 0xff)
 156 #define BITS_SHIFT_NEXT_LEVEL(eax)      ((eax) & 0x1f)
 157
 158 static void set_x2apic_bits(void)
 159 {
 160         unsigned int eax, ebx, ecx, edx, sub_index;
 161         unsigned int sid_shift;
 162
 163         cpuid(0, &eax, &ebx, &ecx, &edx);
 164         if (eax < 0xb) {
 165                 pr_info("UV: CPU does not have CPUID.11\n");
 166                 return;
 167         }
 168         cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
 169         if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
 170                 pr_info("UV: CPUID.11 not implemented\n");
 171                 return;
 172         }
 173         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
 174         sub_index = 1;
 175         do {
 176                 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
 177                 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
 178                         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
 179                         break;
 180                 }
 181                 sub_index++;
 182         } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
 183         uv_cpuid.apicid_shift = 0;
 184         uv_cpuid.apicid_mask = (~(-1 << sid_shift));
 185         uv_cpuid.socketid_shift = sid_shift;
 186 }
 187
 188 static void __init early_get_apic_socketid_shift(void)
 189 {
 190         if (is_uv2_hub() || is_uv3_hub())
 191                 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
 192
 193         set_x2apic_bits();
 194
 195         pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n",
 196                 uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
 197         pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n",
 198                 uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
 199 }
 200
 201 /*
 202  * Add an extra bit as dictated by bios to the destination apicid of
 203  * interrupts potentially passing through the UV HUB.  This prevents
 204  * a deadlock between interrupts and IO port operations.
 205  */
 206 static void __init uv_set_apicid_hibit(void)
 207 {
 208         union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
 209
 210         if (is_uv1_hub()) {
 211                 apicid_mask.v =
 212                         uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
 213                 uv_apicid_hibits =
 214                         apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
 215         }
 216 }
 217
 218 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 219 {
 220         int pnodeid;
 221         int uv_apic;
 222
 223         if (strncmp(oem_id, "SGI", 3) != 0)
 224                 return 0;
 225
 226         /* Setup early hub type field in uv_hub_info for Node 0 */
 227         uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
 228
 229         /*
 230          * Determine UV arch type.
 231          *   SGI: UV100/1000
 232          *   SGI2: UV2000/3000
 233          *   SGI3: UV300 (truncated to 4 chars because of different varieties)
 234          *   SGI4: UV400 (truncated to 4 chars because of different varieties)
 235          */
 236         uv_hub_info->hub_revision =
 237                 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
 238                 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
 239                 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
 240                 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
 241
 242         if (uv_hub_info->hub_revision == 0)
 243                 goto badbios;
 244
 245         pnodeid = early_get_pnodeid();
 246         early_get_apic_socketid_shift();
 247         x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
 248         x86_platform.nmi_init = uv_nmi_init;
 249
 250         if (!strcmp(oem_table_id, "UVX")) {             /* most common */
 251                 uv_system_type = UV_X2APIC;
 252                 uv_apic = 0;
 253
 254         } else if (!strcmp(oem_table_id, "UVH")) {      /* only UV1 systems */
 255                 uv_system_type = UV_NON_UNIQUE_APIC;
 256                 __this_cpu_write(x2apic_extra_bits,
 257                         pnodeid << uvh_apicid.s.pnode_shift);
 258                 uv_set_apicid_hibit();
 259                 uv_apic = 1;
 260
 261         } else  if (!strcmp(oem_table_id, "UVL")) {     /* only used for */
 262                 uv_system_type = UV_LEGACY_APIC;        /* very small systems */
 263                 uv_apic = 0;
 264
 265         } else {
 266                 goto badbios;
 267         }
 268
 269         pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n",
 270                 oem_id, oem_table_id, uv_system_type,
 271                 uv_min_hub_revision_id, uv_apic);
 272
 273         return uv_apic;
 274
 275 badbios:
 276         pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
 277         pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
 278         BUG();
 279 }
 280
 281 enum uv_system_type get_uv_system_type(void)
 282 {
 283         return uv_system_type;
 284 }
 285
 286 int is_uv_system(void)
 287 {
 288         return uv_system_type != UV_NONE;
 289 }
 290 EXPORT_SYMBOL_GPL(is_uv_system);
 291
 292 void **__uv_hub_info_list;
 293 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
 294
 295 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
 296 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
 297
 298 short uv_possible_blades;
 299 EXPORT_SYMBOL_GPL(uv_possible_blades);
 300
 301 unsigned long sn_rtc_cycles_per_second;
 302 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 303
 304 static __initdata unsigned short *_node_to_pnode;
 305
 306 extern int uv_hub_info_version(void)
 307 {
 308         return UV_HUB_INFO_VERSION;
 309 }
 310 EXPORT_SYMBOL(uv_hub_info_version);
 311
 312 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 313 {
 314         unsigned long val;
 315         int pnode;
 316
 317         pnode = uv_apicid_to_pnode(phys_apicid);
 318         phys_apicid |= uv_apicid_hibits;
 319         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 320             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 321             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 322             APIC_DM_INIT;
 323         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 324
 325         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 326             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 327             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 328             APIC_DM_STARTUP;
 329         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 330
 331         return 0;
 332 }
 333
 334 static void uv_send_IPI_one(int cpu, int vector)
 335 {
 336         unsigned long apicid;
 337         int pnode;
 338
 339         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 340         pnode = uv_apicid_to_pnode(apicid);
 341         uv_hub_send_ipi(pnode, apicid, vector);
 342 }
 343
 344 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 345 {
 346         unsigned int cpu;
 347
 348         for_each_cpu(cpu, mask)
 349                 uv_send_IPI_one(cpu, vector);
 350 }
 351
 352 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 353 {
 354         unsigned int this_cpu = smp_processor_id();
 355         unsigned int cpu;
 356
 357         for_each_cpu(cpu, mask) {
 358                 if (cpu != this_cpu)
 359                         uv_send_IPI_one(cpu, vector);
 360         }
 361 }
 362
 363 static void uv_send_IPI_allbutself(int vector)
 364 {
 365         unsigned int this_cpu = smp_processor_id();
 366         unsigned int cpu;
 367
 368         for_each_online_cpu(cpu) {
 369                 if (cpu != this_cpu)
 370                         uv_send_IPI_one(cpu, vector);
 371         }
 372 }
 373
 374 static void uv_send_IPI_all(int vector)
 375 {
 376         uv_send_IPI_mask(cpu_online_mask, vector);
 377 }
 378
 379 static int uv_apic_id_valid(int apicid)
 380 {
 381         return 1;
 382 }
 383
 384 static int uv_apic_id_registered(void)
 385 {
 386         return 1;
 387 }
 388
 389 static void uv_init_apic_ldr(void)
 390 {
 391 }
 392
 393 static int
 394 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 395                           const struct cpumask *andmask,
 396                           unsigned int *apicid)
 397 {
 398         int unsigned cpu;
 399
 400         /*
 401          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 402          * May as well be the first.
 403          */
 404         for_each_cpu_and(cpu, cpumask, andmask) {
 405                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 406                         break;
 407         }
 408
 409         if (likely(cpu < nr_cpu_ids)) {
 410                 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
 411                 return 0;
 412         }
 413
 414         return -EINVAL;
 415 }
 416
 417 static unsigned int x2apic_get_apic_id(unsigned long x)
 418 {
 419         unsigned int id;
 420
 421         WARN_ON(preemptible() && num_online_cpus() > 1);
 422         id = x | __this_cpu_read(x2apic_extra_bits);
 423
 424         return id;
 425 }
 426
 427 static unsigned long set_apic_id(unsigned int id)
 428 {
 429         unsigned long x;
 430
 431         /* maskout x2apic_extra_bits ? */
 432         x = id;
 433         return x;
 434 }
 435
 436 static unsigned int uv_read_apic_id(void)
 437 {
 438         return x2apic_get_apic_id(apic_read(APIC_ID));
 439 }
 440
 441 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 442 {
 443         return uv_read_apic_id() >> index_msb;
 444 }
 445
 446 static void uv_send_IPI_self(int vector)
 447 {
 448         apic_write(APIC_SELF_IPI, vector);
 449 }
 450
 451 static int uv_probe(void)
 452 {
 453         return apic == &apic_x2apic_uv_x;
 454 }
 455
 456 static struct apic __refdata apic_x2apic_uv_x = {
 457
 458         .name                           = "UV large system",
 459         .probe                          = uv_probe,
 460         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 461         .apic_id_valid                  = uv_apic_id_valid,
 462         .apic_id_registered             = uv_apic_id_registered,
 463
 464         .irq_delivery_mode              = dest_Fixed,
 465         .irq_dest_mode                  = 0, /* physical */
 466
 467         .target_cpus                    = online_target_cpus,
 468         .disable_esr                    = 0,
 469         .dest_logical                   = APIC_DEST_LOGICAL,
 470         .check_apicid_used              = NULL,
 471
 472         .vector_allocation_domain       = default_vector_allocation_domain,
 473         .init_apic_ldr                  = uv_init_apic_ldr,
 474
 475         .ioapic_phys_id_map             = NULL,
 476         .setup_apic_routing             = NULL,
 477         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 478         .apicid_to_cpu_present          = NULL,
 479         .check_phys_apicid_present      = default_check_phys_apicid_present,
 480         .phys_pkg_id                    = uv_phys_pkg_id,
 481
 482         .get_apic_id                    = x2apic_get_apic_id,
 483         .set_apic_id                    = set_apic_id,
 484         .apic_id_mask                   = 0xFFFFFFFFu,
 485
 486         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 487
 488         .send_IPI                       = uv_send_IPI_one,
 489         .send_IPI_mask                  = uv_send_IPI_mask,
 490         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 491         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 492         .send_IPI_all                   = uv_send_IPI_all,
 493         .send_IPI_self                  = uv_send_IPI_self,
 494
 495         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 496         .inquire_remote_apic            = NULL,
 497
 498         .read                           = native_apic_msr_read,
 499         .write                          = native_apic_msr_write,
 500         .eoi_write                      = native_apic_msr_eoi_write,
 501         .icr_read                       = native_x2apic_icr_read,
 502         .icr_write                      = native_x2apic_icr_write,
 503         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 504         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 505 };
 506
 507 static void set_x2apic_extra_bits(int pnode)
 508 {
 509         __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
 510 }
 511
 512 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH      3
 513 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 514
 515 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 516 {
 517         union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
 518         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 519         unsigned long m_redirect;
 520         unsigned long m_overlay;
 521         int i;
 522
 523         for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
 524                 switch (i) {
 525                 case 0:
 526                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
 527                         m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
 528                         break;
 529                 case 1:
 530                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
 531                         m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
 532                         break;
 533                 case 2:
 534                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
 535                         m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
 536                         break;
 537                 }
 538                 alias.v = uv_read_local_mmr(m_overlay);
 539                 if (alias.s.enable && alias.s.base == 0) {
 540                         *size = (1UL << alias.s.m_alias);
 541                         redirect.v = uv_read_local_mmr(m_redirect);
 542                         *base = (unsigned long)redirect.s.dest_base
 543                                                         << DEST_SHIFT;
 544                         return;
 545                 }
 546         }
 547         *base = *size = 0;
 548 }
 549
 550 enum map_type {map_wb, map_uc};
 551
 552 static __init void map_high(char *id, unsigned long base, int pshift,
 553                         int bshift, int max_pnode, enum map_type map_type)
 554 {
 555         unsigned long bytes, paddr;
 556
 557         paddr = base << pshift;
 558         bytes = (1UL << bshift) * (max_pnode + 1);
 559         if (!paddr) {
 560                 pr_info("UV: Map %s_HI base address NULL\n", id);
 561                 return;
 562         }
 563         pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
 564         if (map_type == map_uc)
 565                 init_extra_mapping_uc(paddr, bytes);
 566         else
 567                 init_extra_mapping_wb(paddr, bytes);
 568 }
 569
 570 static __init void map_gru_distributed(unsigned long c)
 571 {
 572         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 573         u64 paddr;
 574         unsigned long bytes;
 575         int nid;
 576
 577         gru.v = c;
 578         /* only base bits 42:28 relevant in dist mode */
 579         gru_dist_base = gru.v & 0x000007fff0000000UL;
 580         if (!gru_dist_base) {
 581                 pr_info("UV: Map GRU_DIST base address NULL\n");
 582                 return;
 583         }
 584         bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 585         gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
 586         gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
 587         gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
 588         for_each_online_node(nid) {
 589                 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
 590                                 gru_dist_base;
 591                 init_extra_mapping_wb(paddr, bytes);
 592                 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
 593                 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
 594         }
 595         /* Save upper (63:M) bits of address only for is_GRU_range */
 596         gru_first_node_paddr &= gru_dist_umask;
 597         gru_last_node_paddr &= gru_dist_umask;
 598         pr_debug("UV: Map GRU_DIST base 0x%016llx  0x%016llx - 0x%016llx\n",
 599                 gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
 600 }
 601
 602 static __init void map_gru_high(int max_pnode)
 603 {
 604         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 605         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 606         unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
 607         unsigned long base;
 608
 609         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 610         if (!gru.s.enable) {
 611                 pr_info("UV: GRU disabled\n");
 612                 return;
 613         }
 614
 615         if (is_uv3_hub() && gru.s3.mode) {
 616                 map_gru_distributed(gru.v);
 617                 return;
 618         }
 619         base = (gru.v & mask) >> shift;
 620         map_high("GRU", base, shift, shift, max_pnode, map_wb);
 621         gru_start_paddr = ((u64)base << shift);
 622         gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 623 }
 624
 625 static __init void map_mmr_high(int max_pnode)
 626 {
 627         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 628         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 629
 630         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 631         if (mmr.s.enable)
 632                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 633         else
 634                 pr_info("UV: MMR disabled\n");
 635 }
 636
 637 /*
 638  * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY
 639  * and REDIRECT MMR regs are exactly the same on UV3.
 640  */
 641 struct mmioh_config {
 642         unsigned long overlay;
 643         unsigned long redirect;
 644         char *id;
 645 };
 646
 647 static __initdata struct mmioh_config mmiohs[] = {
 648         {
 649                 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR,
 650                 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR,
 651                 "MMIOH0"
 652         },
 653         {
 654                 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR,
 655                 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR,
 656                 "MMIOH1"
 657         },
 658 };
 659
 660 /* UV3 & UV4 have identical MMIOH overlay configs */
 661 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
 662 {
 663         union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
 664         unsigned long mmr;
 665         unsigned long base;
 666         int i, n, shift, m_io, max_io;
 667         int nasid, lnasid, fi, li;
 668         char *id;
 669
 670         id = mmiohs[index].id;
 671         overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
 672         pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n",
 673                 id, overlay.v, overlay.s3.base, overlay.s3.m_io);
 674         if (!overlay.s3.enable) {
 675                 pr_info("UV: %s disabled\n", id);
 676                 return;
 677         }
 678
 679         shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT;
 680         base = (unsigned long)overlay.s3.base;
 681         m_io = overlay.s3.m_io;
 682         mmr = mmiohs[index].redirect;
 683         n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
 684         min_pnode *= 2;                         /* convert to NASID */
 685         max_pnode *= 2;
 686         max_io = lnasid = fi = li = -1;
 687
 688         for (i = 0; i < n; i++) {
 689                 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect;
 690
 691                 redirect.v = uv_read_local_mmr(mmr + i * 8);
 692                 nasid = redirect.s3.nasid;
 693                 if (nasid < min_pnode || max_pnode < nasid)
 694                         nasid = -1;             /* invalid NASID */
 695
 696                 if (nasid == lnasid) {
 697                         li = i;
 698                         if (i != n-1)           /* last entry check */
 699                                 continue;
 700                 }
 701
 702                 /* check if we have a cached (or last) redirect to print */
 703                 if (lnasid != -1 || (i == n-1 && nasid != -1))  {
 704                         unsigned long addr1, addr2;
 705                         int f, l;
 706
 707                         if (lnasid == -1) {
 708                                 f = l = i;
 709                                 lnasid = nasid;
 710                         } else {
 711                                 f = fi;
 712                                 l = li;
 713                         }
 714                         addr1 = (base << shift) +
 715                                 f * (unsigned long)(1 << m_io);
 716                         addr2 = (base << shift) +
 717                                 (l + 1) * (unsigned long)(1 << m_io);
 718                         pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
 719                                 id, fi, li, lnasid, addr1, addr2);
 720                         if (max_io < l)
 721                                 max_io = l;
 722                 }
 723                 fi = li = i;
 724                 lnasid = nasid;
 725         }
 726
 727         pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n",
 728                 id, base, shift, m_io, max_io);
 729
 730         if (max_io >= 0)
 731                 map_high(id, base, shift, m_io, max_io, map_uc);
 732 }
 733
 734 static __init void map_mmioh_high(int min_pnode, int max_pnode)
 735 {
 736         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 737         unsigned long mmr, base;
 738         int shift, enable, m_io, n_io;
 739
 740         if (is_uv3_hub() || is_uv4_hub()) {
 741                 /* Map both MMIOH Regions */
 742                 map_mmioh_high_uv3(0, min_pnode, max_pnode);
 743                 map_mmioh_high_uv3(1, min_pnode, max_pnode);
 744                 return;
 745         }
 746
 747         if (is_uv1_hub()) {
 748                 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 749                 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 750                 mmioh.v = uv_read_local_mmr(mmr);
 751                 enable = !!mmioh.s1.enable;
 752                 base = mmioh.s1.base;
 753                 m_io = mmioh.s1.m_io;
 754                 n_io = mmioh.s1.n_io;
 755         } else if (is_uv2_hub()) {
 756                 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 757                 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 758                 mmioh.v = uv_read_local_mmr(mmr);
 759                 enable = !!mmioh.s2.enable;
 760                 base = mmioh.s2.base;
 761                 m_io = mmioh.s2.m_io;
 762                 n_io = mmioh.s2.n_io;
 763         } else
 764                 return;
 765
 766         if (enable) {
 767                 max_pnode &= (1 << n_io) - 1;
 768                 pr_info(
 769                     "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
 770                         base, shift, m_io, n_io, max_pnode);
 771                 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
 772         } else {
 773                 pr_info("UV: MMIOH disabled\n");
 774         }
 775 }
 776
 777 static __init void map_low_mmrs(void)
 778 {
 779         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 780         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 781 }
 782
 783 static __init void uv_rtc_init(void)
 784 {
 785         long status;
 786         u64 ticks_per_sec;
 787
 788         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 789                                         &ticks_per_sec);
 790         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 791                 printk(KERN_WARNING
 792                         "unable to determine platform RTC clock frequency, "
 793                         "guessing.\n");
 794                 /* BIOS gives wrong value for clock freq. so guess */
 795                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 796         } else
 797                 sn_rtc_cycles_per_second = ticks_per_sec;
 798 }
 799
 800 /*
 801  * percpu heartbeat timer
 802  */
 803 static void uv_heartbeat(unsigned long ignored)
 804 {
 805         struct timer_list *timer = &uv_scir_info->timer;
 806         unsigned char bits = uv_scir_info->state;
 807
 808         /* flip heartbeat bit */
 809         bits ^= SCIR_CPU_HEARTBEAT;
 810
 811         /* is this cpu idle? */
 812         if (idle_cpu(raw_smp_processor_id()))
 813                 bits &= ~SCIR_CPU_ACTIVITY;
 814         else
 815                 bits |= SCIR_CPU_ACTIVITY;
 816
 817         /* update system controller interface reg */
 818         uv_set_scir_bits(bits);
 819
 820         /* enable next timer period */
 821         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 822 }
 823
 824 static void uv_heartbeat_enable(int cpu)
 825 {
 826         while (!uv_cpu_scir_info(cpu)->enabled) {
 827                 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
 828
 829                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 830                 setup_timer(timer, uv_heartbeat, cpu);
 831                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 832                 add_timer_on(timer, cpu);
 833                 uv_cpu_scir_info(cpu)->enabled = 1;
 834
 835                 /* also ensure that boot cpu is enabled */
 836                 cpu = 0;
 837         }
 838 }
 839
 840 #ifdef CONFIG_HOTPLUG_CPU
 841 static void uv_heartbeat_disable(int cpu)
 842 {
 843         if (uv_cpu_scir_info(cpu)->enabled) {
 844                 uv_cpu_scir_info(cpu)->enabled = 0;
 845                 del_timer(&uv_cpu_scir_info(cpu)->timer);
 846         }
 847         uv_set_cpu_scir_bits(cpu, 0xff);
 848 }
 849
 850 /*
 851  * cpu hotplug notifier
 852  */
 853 static int uv_scir_cpu_notify(struct notifier_block *self, unsigned long action,
 854                               void *hcpu)
 855 {
 856         long cpu = (long)hcpu;
 857
 858         switch (action & ~CPU_TASKS_FROZEN) {
 859         case CPU_DOWN_FAILED:
 860         case CPU_ONLINE:
 861                 uv_heartbeat_enable(cpu);
 862                 break;
 863         case CPU_DOWN_PREPARE:
 864                 uv_heartbeat_disable(cpu);
 865                 break;
 866         default:
 867                 break;
 868         }
 869         return NOTIFY_OK;
 870 }
 871
 872 static __init void uv_scir_register_cpu_notifier(void)
 873 {
 874         hotcpu_notifier(uv_scir_cpu_notify, 0);
 875 }
 876
 877 #else /* !CONFIG_HOTPLUG_CPU */
 878
 879 static __init void uv_scir_register_cpu_notifier(void)
 880 {
 881 }
 882
 883 static __init int uv_init_heartbeat(void)
 884 {
 885         int cpu;
 886
 887         if (is_uv_system())
 888                 for_each_online_cpu(cpu)
 889                         uv_heartbeat_enable(cpu);
 890         return 0;
 891 }
 892
 893 late_initcall(uv_init_heartbeat);
 894
 895 #endif /* !CONFIG_HOTPLUG_CPU */
 896
 897 /* Direct Legacy VGA I/O traffic to designated IOH */
 898 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
 899                       unsigned int command_bits, u32 flags)
 900 {
 901         int domain, bus, rc;
 902
 903         PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
 904                         pdev->devfn, decode, command_bits, flags);
 905
 906         if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
 907                 return 0;
 908
 909         if ((command_bits & PCI_COMMAND_IO) == 0)
 910                 return 0;
 911
 912         domain = pci_domain_nr(pdev->bus);
 913         bus = pdev->bus->number;
 914
 915         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
 916         PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
 917
 918         return rc;
 919 }
 920
 921 /*
 922  * Called on each cpu to initialize the per_cpu UV data area.
 923  * FIXME: hotplug not supported yet
 924  */
 925 void uv_cpu_init(void)
 926 {
 927         /* CPU 0 initialization will be done via uv_system_init. */
 928         if (smp_processor_id() == 0)
 929                 return;
 930
 931         uv_hub_info->nr_online_cpus++;
 932
 933         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 934                 set_x2apic_extra_bits(uv_hub_info->pnode);
 935 }
 936
 937 struct mn {
 938         unsigned char   m_val;
 939         unsigned char   n_val;
 940         unsigned char   m_shift;
 941         unsigned char   n_lshift;
 942 };
 943
 944 static void get_mn(struct mn *mnp)
 945 {
 946         union uvh_rh_gam_config_mmr_u m_n_config;
 947         union uv3h_gr0_gam_gr_config_u m_gr_config;
 948
 949         m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
 950         mnp->n_val = m_n_config.s.n_skt;
 951         if (is_uv4_hub()) {
 952                 mnp->m_val = 0;
 953                 mnp->n_lshift = 0;
 954         } else if (is_uv3_hub()) {
 955                 mnp->m_val = m_n_config.s3.m_skt;
 956                 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
 957                 mnp->n_lshift = m_gr_config.s3.m_skt;
 958         } else if (is_uv2_hub()) {
 959                 mnp->m_val = m_n_config.s2.m_skt;
 960                 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
 961         } else if (is_uv1_hub()) {
 962                 mnp->m_val = m_n_config.s1.m_skt;
 963                 mnp->n_lshift = mnp->m_val;
 964         }
 965         mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
 966 }
 967
 968 void __init uv_init_hub_info(struct uv_hub_info_s *hub_info)
 969 {
 970         struct mn mn = {0};     /* avoid unitialized warnings */
 971         union uvh_node_id_u node_id;
 972
 973         get_mn(&mn);
 974         hub_info->m_val = mn.m_val;
 975         hub_info->n_val = mn.n_val;
 976         hub_info->m_shift = mn.m_shift;
 977         hub_info->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
 978
 979         hub_info->hub_revision = uv_hub_info->hub_revision;
 980         hub_info->pnode_mask = uv_cpuid.pnode_mask;
 981         hub_info->gpa_mask = mn.m_val ?
 982                 (1UL << (mn.m_val + mn.n_val)) - 1 :
 983                 (1UL << uv_cpuid.gpa_shift) - 1;
 984
 985         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 986         hub_info->gnode_extra =
 987                 (node_id.s.node_id & ~((1 << mn.n_val) - 1)) >> 1;
 988
 989         hub_info->gnode_upper =
 990                 ((unsigned long)hub_info->gnode_extra << mn.m_val);
 991
 992         hub_info->global_mmr_base =
 993                 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 994                                 ~UV_MMR_ENABLE;
 995
 996         get_lowmem_redirect(
 997                 &hub_info->lowmem_remap_base, &hub_info->lowmem_remap_top);
 998
 999         hub_info->apic_pnode_shift = uv_cpuid.socketid_shift;
1000
1001         /* show system specific info */
1002         pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n",
1003                 hub_info->n_val, hub_info->m_val,
1004                 hub_info->m_shift, hub_info->n_lshift);
1005
1006         pr_info("UV: pnode_mask:0x%x gpa_mask:0x%lx apic_pns:%d\n",
1007                 hub_info->pnode_mask, hub_info->gpa_mask,
1008                 hub_info->apic_pnode_shift);
1009
1010         pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n",
1011                 hub_info->gnode_upper, hub_info->gnode_extra);
1012
1013         pr_info("UV: global MMR base 0x%lx\n", hub_info->global_mmr_base);
1014
1015 }
1016
1017 /*
1018  * Setup physical blade translations from UVH_NODE_PRESENT_TABLE
1019  * .. NB: UVH_NODE_PRESENT_TABLE is going away,
1020  * .. being replaced by GAM Range Table
1021  */
1022 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1023 {
1024         size_t bytes;
1025         int blade, i, j, uv_pb = 0, num_nodes = num_possible_nodes();
1026
1027         pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1028         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1029                 unsigned long np;
1030
1031                 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1032                 if (np)
1033                         pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1034
1035                 uv_pb += hweight64(np);
1036         }
1037         if (uv_possible_blades != uv_pb)
1038                 uv_possible_blades = uv_pb;
1039
1040         bytes = num_nodes * sizeof(_node_to_pnode[0]);
1041         _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1042         BUG_ON(!_node_to_pnode);
1043
1044         for (blade = 0, i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1045                 unsigned short pnode;
1046                 unsigned long present =
1047                         uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1048
1049                 for (j = 0; j < 64; j++) {
1050                         if (!test_bit(j, &present))
1051                                 continue;
1052                         pnode = (i * 64 + j) & hub_info->pnode_mask;
1053                         _node_to_pnode[blade++] = pnode;
1054                 }
1055                 if (blade > num_nodes) {
1056                         pr_err("UV: blade count(%d) exceeds node count(%d)!\n",
1057                                 blade, num_nodes);
1058                         BUG();
1059                 }
1060         }
1061 }
1062
1063 void __init uv_system_init(void)
1064 {
1065         struct uv_hub_info_s hub_info = {0};
1066         int bytes, cpu, nodeid;
1067         unsigned short min_pnode = 9999, max_pnode = 0;
1068         char *hub = is_uv4_hub() ? "UV400" :
1069                     is_uv3_hub() ? "UV300" :
1070                     is_uv2_hub() ? "UV2000/3000" :
1071                     is_uv1_hub() ? "UV100/1000" : NULL;
1072
1073         if (!hub) {
1074                 pr_err("UV: Unknown/unsupported UV hub\n");
1075                 return;
1076         }
1077         pr_info("UV: Found %s hub\n", hub);
1078
1079         /* We now only need to map the MMRs on UV1 */
1080         if (is_uv1_hub())
1081                 map_low_mmrs();
1082
1083         uv_init_hub_info(&hub_info);
1084         uv_possible_blades = num_possible_nodes();
1085         if (!_node_to_pnode)
1086                 boot_init_possible_blades(&hub_info);
1087
1088         /* uv_num_possible_blades() is really the hub count */
1089         pr_info("UV: Found %d hubs, %d nodes, %d cpus\n",
1090                         uv_num_possible_blades(),
1091                         num_possible_nodes(),
1092                         num_possible_cpus());
1093
1094         uv_bios_init();
1095         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
1096                             &sn_region_size, &system_serial_number);
1097         hub_info.coherency_domain_number = sn_coherency_id;
1098         uv_rtc_init();
1099
1100         bytes = sizeof(void *) * uv_num_possible_blades();
1101         __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1102         BUG_ON(!__uv_hub_info_list);
1103
1104         bytes = sizeof(struct uv_hub_info_s);
1105         for_each_node(nodeid) {
1106                 struct uv_hub_info_s *new_hub;
1107                 unsigned short pnode;
1108
1109                 if (__uv_hub_info_list[nodeid]) {
1110                         pr_err("UV: Node %d UV HUB already initialized!?\n",
1111                                 nodeid);
1112                         BUG();
1113                 }
1114
1115                 /* Allocate new per hub info list */
1116                 new_hub = (nodeid == 0) ?
1117                         &uv_hub_info_node0 :
1118                         kzalloc_node(bytes, GFP_KERNEL, nodeid);
1119                 BUG_ON(!new_hub);
1120                 __uv_hub_info_list[nodeid] = new_hub;
1121                 new_hub = uv_hub_info_list(nodeid);
1122                 BUG_ON(!new_hub);
1123                 *new_hub = hub_info;
1124
1125                 pnode = _node_to_pnode[nodeid];
1126                 min_pnode = min(pnode, min_pnode);
1127                 max_pnode = max(pnode, max_pnode);
1128                 new_hub->pnode = pnode;
1129                 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1130                 new_hub->memory_nid = -1;
1131                 new_hub->nr_possible_cpus = 0;
1132                 new_hub->nr_online_cpus = 0;
1133         }
1134
1135         /* Initialize per cpu info */
1136         for_each_possible_cpu(cpu) {
1137                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1138
1139                 nodeid = cpu_to_node(cpu);
1140                 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1141                 uv_cpu_info_per(cpu)->blade_cpu_id =
1142                         uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1143                 if (uv_cpu_hub_info(cpu)->memory_nid == -1)
1144                         uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1145                 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
1146         }
1147
1148         /* Display per node info */
1149         for_each_node(nodeid) {
1150                 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1151                         nodeid,
1152                         uv_hub_info_list(nodeid)->pnode,
1153                         uv_hub_info_list(nodeid)->nr_possible_cpus);
1154         }
1155
1156         pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1157         map_gru_high(max_pnode);
1158         map_mmr_high(max_pnode);
1159         map_mmioh_high(min_pnode, max_pnode);
1160
1161         uv_nmi_setup();
1162         uv_cpu_init();
1163         uv_scir_register_cpu_notifier();
1164         proc_mkdir("sgi_uv", NULL);
1165
1166         /* register Legacy VGA I/O redirection handler */
1167         pci_register_set_vga_state(uv_set_vga_state);
1168
1169         /*
1170          * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
1171          * EFI is not enabled in the kdump kernel.
1172          */
1173         if (is_kdump_kernel())
1174                 reboot_type = BOOT_ACPI;
1175 }
1176
1177 apic_driver(apic_x2apic_uv_x);