2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
8 * (C) Copyright 2020 Hewlett Packard Enterprise Development LP
9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
11 #include <linux/crash_dump.h>
12 #include <linux/cpuhotplug.h>
13 #include <linux/cpumask.h>
14 #include <linux/proc_fs.h>
15 #include <linux/memory.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/acpi.h>
19 #include <linux/efi.h>
21 #include <asm/e820/api.h>
22 #include <asm/uv/uv_mmrs.h>
23 #include <asm/uv/uv_hub.h>
24 #include <asm/uv/bios.h>
25 #include <asm/uv/uv.h>
30 static enum uv_system_type uv_system_type;
31 static int uv_hubbed_system;
32 static int uv_hubless_system;
33 static u64 gru_start_paddr, gru_end_paddr;
34 static union uvh_apicid uvh_apicid;
35 static int uv_node_id;
37 /* Unpack AT/OEM/TABLE ID's to be NULL terminated strings */
38 static u8 uv_archtype[UV_AT_SIZE + 1];
39 static u8 oem_id[ACPI_OEM_ID_SIZE + 1];
40 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
42 /* Information derived from CPUID and some UV MMRs */
44 unsigned int apicid_shift;
45 unsigned int apicid_mask;
46 unsigned int socketid_shift; /* aka pnode_shift for UV2/3 */
47 unsigned int pnode_mask;
48 unsigned int nasid_shift;
49 unsigned int gpa_shift;
50 unsigned int gnode_shift;
55 static int uv_min_hub_revision_id;
57 static struct apic apic_x2apic_uv_x;
58 static struct uv_hub_info_s uv_hub_info_node0;
60 /* Set this to use hardware error handler instead of kernel panic: */
61 static int disable_uv_undefined_panic = 1;
63 unsigned long uv_undefined(char *str)
65 if (likely(!disable_uv_undefined_panic))
66 panic("UV: error: undefined MMR: %s\n", str);
68 pr_crit("UV: error: undefined MMR: %s\n", str);
70 /* Cause a machine fault: */
73 EXPORT_SYMBOL(uv_undefined);
75 static unsigned long __init uv_early_read_mmr(unsigned long addr)
77 unsigned long val, *mmr;
79 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
81 early_iounmap(mmr, sizeof(*mmr));
86 static inline bool is_GRU_range(u64 start, u64 end)
91 return start >= gru_start_paddr && end <= gru_end_paddr;
94 static bool uv_is_untracked_pat_range(u64 start, u64 end)
96 return is_ISA_range(start, end) || is_GRU_range(start, end);
99 static void __init early_get_pnodeid(void)
104 if (UVH_RH10_GAM_ADDR_MAP_CONFIG) {
105 union uvh_rh10_gam_addr_map_config_u m_n_config;
107 m_n_config.v = uv_early_read_mmr(UVH_RH10_GAM_ADDR_MAP_CONFIG);
108 uv_cpuid.n_skt = m_n_config.s.n_skt;
109 uv_cpuid.nasid_shift = 0;
110 } else if (UVH_RH_GAM_ADDR_MAP_CONFIG) {
111 union uvh_rh_gam_addr_map_config_u m_n_config;
113 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG);
114 uv_cpuid.n_skt = m_n_config.s.n_skt;
116 uv_cpuid.m_skt = m_n_config.s3.m_skt;
118 uv_cpuid.m_skt = m_n_config.s2.m_skt;
119 uv_cpuid.nasid_shift = 1;
121 unsigned long GAM_ADDR_MAP_CONFIG = 0;
123 WARN(GAM_ADDR_MAP_CONFIG == 0,
124 "UV: WARN: GAM_ADDR_MAP_CONFIG is not available\n");
126 uv_cpuid.nasid_shift = 0;
130 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
132 uv_cpuid.pnode_mask = (1 << uv_cpuid.n_skt) - 1;
133 pnode = (uv_node_id >> uv_cpuid.nasid_shift) & uv_cpuid.pnode_mask;
134 uv_cpuid.gpa_shift = 46; /* Default unless changed */
136 pr_info("UV: n_skt:%d pnmsk:%x pn:%x\n",
137 uv_cpuid.n_skt, uv_cpuid.pnode_mask, pnode);
140 /* Running on a UV Hubbed system, determine which UV Hub Type it is */
141 static int __init early_set_hub_type(void)
143 union uvh_node_id_u node_id;
146 * The NODE_ID MMR is always at offset 0.
147 * Contains the chip part # + revision.
148 * Node_id field started with 15 bits,
149 * ... now 7 but upper 8 are masked to 0.
150 * All blades/nodes have the same part # and hub revision.
152 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
153 uv_node_id = node_id.sx.node_id;
155 switch (node_id.s.part_number) {
157 case UV5_HUB_PART_NUMBER:
158 uv_min_hub_revision_id = node_id.s.revision
159 + UV5_HUB_REVISION_BASE;
160 uv_hub_type_set(UV5);
163 /* UV4/4A only have a revision difference */
164 case UV4_HUB_PART_NUMBER:
165 uv_min_hub_revision_id = node_id.s.revision
166 + UV4_HUB_REVISION_BASE - 1;
167 uv_hub_type_set(UV4);
168 if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE)
169 uv_hub_type_set(UV4|UV4A);
172 case UV3_HUB_PART_NUMBER:
173 case UV3_HUB_PART_NUMBER_X:
174 uv_min_hub_revision_id = node_id.s.revision
175 + UV3_HUB_REVISION_BASE;
176 uv_hub_type_set(UV3);
179 case UV2_HUB_PART_NUMBER:
180 case UV2_HUB_PART_NUMBER_X:
181 uv_min_hub_revision_id = node_id.s.revision
182 + UV2_HUB_REVISION_BASE - 1;
183 uv_hub_type_set(UV2);
190 pr_info("UV: part#:%x rev:%d rev_id:%d UVtype:0x%x\n",
191 node_id.s.part_number, node_id.s.revision,
192 uv_min_hub_revision_id, is_uv(~0));
197 static void __init uv_tsc_check_sync(void)
204 /* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */
205 if (!is_uv(UV2|UV3|UV4)) {
206 mark_tsc_async_resets("UV5+");
210 /* UV2,3,4, UV BIOS TSC sync state available */
211 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
213 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
214 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
216 /* Check if TSC is valid for all sockets */
217 switch (sync_state) {
218 case UVH_TSC_SYNC_VALID:
220 mark_tsc_async_resets("UV BIOS");
223 /* If BIOS state unknown, don't do anything */
224 case UVH_TSC_SYNC_UNKNOWN:
228 /* Otherwise, BIOS indicates problem with TSC */
231 mark_tsc_unstable("UV BIOS");
234 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
237 /* Selector for (4|4A|5) structs */
238 #define uvxy_field(sname, field, undef) ( \
239 is_uv(UV4A) ? sname.s4a.field : \
240 is_uv(UV4) ? sname.s4.field : \
241 is_uv(UV3) ? sname.s3.field : \
244 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
246 #define SMT_LEVEL 0 /* Leaf 0xb SMT level */
247 #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */
250 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
251 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
253 static void set_x2apic_bits(void)
255 unsigned int eax, ebx, ecx, edx, sub_index;
256 unsigned int sid_shift;
258 cpuid(0, &eax, &ebx, &ecx, &edx);
260 pr_info("UV: CPU does not have CPUID.11\n");
264 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
265 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
266 pr_info("UV: CPUID.11 not implemented\n");
270 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
273 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
274 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
275 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
279 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
281 uv_cpuid.apicid_shift = 0;
282 uv_cpuid.apicid_mask = (~(-1 << sid_shift));
283 uv_cpuid.socketid_shift = sid_shift;
286 static void __init early_get_apic_socketid_shift(void)
288 if (is_uv2_hub() || is_uv3_hub())
289 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
293 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
294 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
297 static void __init uv_stringify(int len, char *to, char *from)
299 strscpy(to, from, len);
301 /* Trim trailing spaces */
305 /* Find UV arch type entry in UVsystab */
306 static unsigned long __init early_find_archtype(struct uv_systab *st)
310 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
311 unsigned long ptr = st->entry[i].offset;
315 ptr += (unsigned long)st;
316 if (st->entry[i].type == UV_SYSTAB_TYPE_ARCH_TYPE)
322 /* Validate UV arch type field in UVsystab */
323 static int __init decode_arch_type(unsigned long ptr)
325 struct uv_arch_type_entry *uv_ate = (struct uv_arch_type_entry *)ptr;
326 int n = strlen(uv_ate->archtype);
328 if (n > 0 && n < sizeof(uv_ate->archtype)) {
329 pr_info("UV: UVarchtype received from BIOS\n");
330 uv_stringify(sizeof(uv_archtype), uv_archtype, uv_ate->archtype);
336 /* Determine if UV arch type entry might exist in UVsystab */
337 static int __init early_get_arch_type(void)
339 unsigned long uvst_physaddr, uvst_size, ptr;
340 struct uv_systab *st;
344 uvst_physaddr = get_uv_systab_phys(0);
348 st = early_memremap_ro(uvst_physaddr, sizeof(struct uv_systab));
350 pr_err("UV: Cannot access UVsystab, remap failed\n");
355 if (rev < UV_SYSTAB_VERSION_UV5) {
356 early_memunmap(st, sizeof(struct uv_systab));
360 uvst_size = st->size;
361 early_memunmap(st, sizeof(struct uv_systab));
362 st = early_memremap_ro(uvst_physaddr, uvst_size);
364 pr_err("UV: Cannot access UVarchtype, remap failed\n");
368 ptr = early_find_archtype(st);
370 early_memunmap(st, uvst_size);
374 ret = decode_arch_type(ptr);
375 early_memunmap(st, uvst_size);
379 /* UV system found, check which APIC MODE BIOS already selected */
380 static void __init early_set_apic_mode(void)
382 if (x2apic_enabled())
383 uv_system_type = UV_X2APIC;
385 uv_system_type = UV_LEGACY_APIC;
388 static int __init uv_set_system_type(char *_oem_id, char *_oem_table_id)
390 /* Save OEM_ID passed from ACPI MADT */
391 uv_stringify(sizeof(oem_id), oem_id, _oem_id);
393 /* Check if BIOS sent us a UVarchtype */
394 if (!early_get_arch_type())
396 /* If not use OEM ID for UVarchtype */
397 uv_stringify(sizeof(uv_archtype), uv_archtype, oem_id);
399 /* Check if not hubbed */
400 if (strncmp(uv_archtype, "SGI", 3) != 0) {
402 /* (Not hubbed), check if not hubless */
403 if (strncmp(uv_archtype, "NSGI", 4) != 0)
405 /* (Not hubless), not a UV */
408 /* Is UV hubless system */
409 uv_hubless_system = 0x01;
412 if (strncmp(uv_archtype, "NSGI5", 5) == 0)
413 uv_hubless_system |= 0x20;
415 /* UV4 Hubless: CH */
416 else if (strncmp(uv_archtype, "NSGI4", 5) == 0)
417 uv_hubless_system |= 0x10;
419 /* UV3 Hubless: UV300/MC990X w/o hub */
421 uv_hubless_system |= 0x8;
423 /* Copy OEM Table ID */
424 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
426 pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n",
427 oem_id, oem_table_id, uv_system_type, uv_hubless_system);
433 pr_err("UV: NUMA is off, disabling UV support\n");
437 /* Set hubbed type if true */
438 uv_hub_info->hub_revision =
439 !strncmp(uv_archtype, "SGI5", 4) ? UV5_HUB_REVISION_BASE :
440 !strncmp(uv_archtype, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
441 !strncmp(uv_archtype, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
442 !strcmp(uv_archtype, "SGI2") ? UV2_HUB_REVISION_BASE : 0;
444 switch (uv_hub_info->hub_revision) {
445 case UV5_HUB_REVISION_BASE:
446 uv_hubbed_system = 0x21;
447 uv_hub_type_set(UV5);
450 case UV4_HUB_REVISION_BASE:
451 uv_hubbed_system = 0x11;
452 uv_hub_type_set(UV4);
455 case UV3_HUB_REVISION_BASE:
456 uv_hubbed_system = 0x9;
457 uv_hub_type_set(UV3);
460 case UV2_HUB_REVISION_BASE:
461 uv_hubbed_system = 0x5;
462 uv_hub_type_set(UV2);
469 /* Get UV hub chip part number & revision */
470 early_set_hub_type();
472 /* Other UV setup functions */
473 early_set_apic_mode();
475 early_get_apic_socketid_shift();
476 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
477 x86_platform.nmi_init = uv_nmi_init;
483 /* Called early to probe for the correct APIC driver */
484 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id)
486 /* Set up early hub info fields for Node 0 */
487 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
489 /* If not UV, return. */
490 if (uv_set_system_type(_oem_id, _oem_table_id) == 0)
493 /* Save for display of the OEM Table ID */
494 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
496 pr_info("UV: OEM IDs %s/%s, System/UVType %d/0x%x, HUB RevID %d\n",
497 oem_id, oem_table_id, uv_system_type, is_uv(UV_ANY),
498 uv_min_hub_revision_id);
503 enum uv_system_type get_uv_system_type(void)
505 return uv_system_type;
508 int uv_get_hubless_system(void)
510 return uv_hubless_system;
512 EXPORT_SYMBOL_GPL(uv_get_hubless_system);
514 ssize_t uv_get_archtype(char *buf, int len)
516 return scnprintf(buf, len, "%s/%s", uv_archtype, oem_table_id);
518 EXPORT_SYMBOL_GPL(uv_get_archtype);
520 int is_uv_system(void)
522 return uv_system_type != UV_NONE;
524 EXPORT_SYMBOL_GPL(is_uv_system);
526 int is_uv_hubbed(int uvtype)
528 return (uv_hubbed_system & uvtype);
530 EXPORT_SYMBOL_GPL(is_uv_hubbed);
532 static int is_uv_hubless(int uvtype)
534 return (uv_hubless_system & uvtype);
537 void **__uv_hub_info_list;
538 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
540 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
541 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
543 short uv_possible_blades;
544 EXPORT_SYMBOL_GPL(uv_possible_blades);
546 unsigned long sn_rtc_cycles_per_second;
547 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
549 /* The following values are used for the per node hub info struct */
550 static __initdata unsigned short _min_socket, _max_socket;
551 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
552 static __initdata struct uv_gam_range_entry *uv_gre_table;
553 static __initdata struct uv_gam_parameters *uv_gp_table;
554 static __initdata unsigned short *_socket_to_node;
555 static __initdata unsigned short *_socket_to_pnode;
556 static __initdata unsigned short *_pnode_to_socket;
557 static __initdata unsigned short *_node_to_socket;
559 static __initdata struct uv_gam_range_s *_gr_table;
561 #define SOCK_EMPTY ((unsigned short)~0)
563 /* Default UV memory block size is 2GB */
564 static unsigned long mem_block_size __initdata = (2UL << 30);
566 /* Kernel parameter to specify UV mem block size */
567 static int __init parse_mem_block_size(char *ptr)
569 unsigned long size = memparse(ptr, NULL);
571 /* Size will be rounded down by set_block_size() below */
572 mem_block_size = size;
575 early_param("uv_memblksize", parse_mem_block_size);
577 static __init int adj_blksize(u32 lgre)
579 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
582 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
583 if (IS_ALIGNED(base, size))
586 if (size >= mem_block_size)
589 mem_block_size = size;
593 static __init void set_block_size(void)
595 unsigned int order = ffs(mem_block_size);
598 /* adjust for ffs return of 1..64 */
599 set_memory_block_size_order(order - 1);
600 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
602 /* bad or zero value, default to 1UL << 31 (2GB) */
603 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
604 set_memory_block_size_order(31);
608 /* Build GAM range lookup table: */
609 static __init void build_uv_gr_table(void)
611 struct uv_gam_range_entry *gre = uv_gre_table;
612 struct uv_gam_range_s *grt;
613 unsigned long last_limit = 0, ram_limit = 0;
614 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
619 bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
620 grt = kzalloc(bytes, GFP_KERNEL);
621 if (WARN_ON_ONCE(!grt))
625 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
626 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
628 /* Mark hole between RAM/non-RAM: */
629 ram_limit = last_limit;
630 last_limit = gre->limit;
634 last_limit = gre->limit;
635 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
638 if (_max_socket < gre->sockid) {
639 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
642 sid = gre->sockid - _min_socket;
645 grt = &_gr_table[indx];
647 grt->nasid = gre->nasid;
648 grt->limit = last_limit = gre->limit;
654 if (lsid == sid && !ram_limit) {
655 /* .. if contiguous: */
656 if (grt->limit == last_limit) {
657 grt->limit = last_limit = gre->limit;
661 /* Non-contiguous RAM range: */
665 grt->nasid = gre->nasid;
666 grt->limit = last_limit = gre->limit;
669 /* Non-contiguous/non-RAM: */
671 /* base is this entry */
672 grt->base = grt - _gr_table;
673 grt->nasid = gre->nasid;
674 grt->limit = last_limit = gre->limit;
678 /* Shorten table if possible */
681 if (i < _gr_table_len) {
684 bytes = i * sizeof(struct uv_gam_range_s);
685 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
692 /* Display resultant GAM range table: */
693 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
694 unsigned long start, end;
697 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
698 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
700 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
704 static int uv_wakeup_secondary(u32 phys_apicid, unsigned long start_rip)
709 pnode = uv_apicid_to_pnode(phys_apicid);
711 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
712 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
713 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
716 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
718 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
719 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
720 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
723 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
728 static void uv_send_IPI_one(int cpu, int vector)
730 unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu);
731 int pnode = uv_apicid_to_pnode(apicid);
732 unsigned long dmode, val;
734 if (vector == NMI_VECTOR)
735 dmode = APIC_DELIVERY_MODE_NMI;
737 dmode = APIC_DELIVERY_MODE_FIXED;
739 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
740 (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
741 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
742 (vector << UVH_IPI_INT_VECTOR_SHFT);
744 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
747 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
751 for_each_cpu(cpu, mask)
752 uv_send_IPI_one(cpu, vector);
755 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
757 unsigned int this_cpu = smp_processor_id();
760 for_each_cpu(cpu, mask) {
762 uv_send_IPI_one(cpu, vector);
766 static void uv_send_IPI_allbutself(int vector)
768 unsigned int this_cpu = smp_processor_id();
771 for_each_online_cpu(cpu) {
773 uv_send_IPI_one(cpu, vector);
777 static void uv_send_IPI_all(int vector)
779 uv_send_IPI_mask(cpu_online_mask, vector);
782 static u32 set_apic_id(u32 id)
787 static unsigned int uv_read_apic_id(void)
789 return x2apic_get_apic_id(apic_read(APIC_ID));
792 static u32 uv_phys_pkg_id(u32 initial_apicid, int index_msb)
794 return uv_read_apic_id() >> index_msb;
797 static int uv_probe(void)
799 return apic == &apic_x2apic_uv_x;
802 static struct apic apic_x2apic_uv_x __ro_after_init = {
804 .name = "UV large system",
806 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
808 .dest_mode_logical = false,
812 .cpu_present_to_apicid = default_cpu_present_to_apicid,
813 .phys_pkg_id = uv_phys_pkg_id,
815 .max_apic_id = UINT_MAX,
816 .get_apic_id = x2apic_get_apic_id,
817 .set_apic_id = set_apic_id,
819 .calc_dest_apicid = apic_default_calc_apicid,
821 .send_IPI = uv_send_IPI_one,
822 .send_IPI_mask = uv_send_IPI_mask,
823 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
824 .send_IPI_allbutself = uv_send_IPI_allbutself,
825 .send_IPI_all = uv_send_IPI_all,
826 .send_IPI_self = x2apic_send_IPI_self,
828 .wakeup_secondary_cpu = uv_wakeup_secondary,
830 .read = native_apic_msr_read,
831 .write = native_apic_msr_write,
832 .eoi = native_apic_msr_eoi,
833 .icr_read = native_x2apic_icr_read,
834 .icr_write = native_x2apic_icr_write,
837 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
838 #define DEST_SHIFT UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT
840 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
842 union uvh_rh_gam_alias_2_overlay_config_u alias;
843 union uvh_rh_gam_alias_2_redirect_config_u redirect;
844 unsigned long m_redirect;
845 unsigned long m_overlay;
848 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
851 m_redirect = UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG;
852 m_overlay = UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG;
855 m_redirect = UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG;
856 m_overlay = UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG;
859 m_redirect = UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG;
860 m_overlay = UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG;
863 alias.v = uv_read_local_mmr(m_overlay);
864 if (alias.s.enable && alias.s.base == 0) {
865 *size = (1UL << alias.s.m_alias);
866 redirect.v = uv_read_local_mmr(m_redirect);
867 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
874 enum map_type {map_wb, map_uc};
875 static const char * const mt[] = { "WB", "UC" };
877 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
879 unsigned long bytes, paddr;
881 paddr = base << pshift;
882 bytes = (1UL << bshift) * (max_pnode + 1);
884 pr_info("UV: Map %s_HI base address NULL\n", id);
887 if (map_type == map_uc)
888 init_extra_mapping_uc(paddr, bytes);
890 init_extra_mapping_wb(paddr, bytes);
892 pr_info("UV: Map %s_HI 0x%lx - 0x%lx %s (%d segments)\n",
893 id, paddr, paddr + bytes, mt[map_type], max_pnode + 1);
896 static __init void map_gru_high(int max_pnode)
898 union uvh_rh_gam_gru_overlay_config_u gru;
899 unsigned long mask, base;
902 if (UVH_RH_GAM_GRU_OVERLAY_CONFIG) {
903 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG);
904 shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
905 mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
906 } else if (UVH_RH10_GAM_GRU_OVERLAY_CONFIG) {
907 gru.v = uv_read_local_mmr(UVH_RH10_GAM_GRU_OVERLAY_CONFIG);
908 shift = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
909 mask = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
911 pr_err("UV: GRU unavailable (no MMR)\n");
916 pr_info("UV: GRU disabled (by BIOS)\n");
920 base = (gru.v & mask) >> shift;
921 map_high("GRU", base, shift, shift, max_pnode, map_wb);
922 gru_start_paddr = ((u64)base << shift);
923 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
926 static __init void map_mmr_high(int max_pnode)
932 if (UVH_RH10_GAM_MMR_OVERLAY_CONFIG) {
933 union uvh_rh10_gam_mmr_overlay_config_u mmr;
935 mmr.v = uv_read_local_mmr(UVH_RH10_GAM_MMR_OVERLAY_CONFIG);
936 enable = mmr.s.enable;
938 shift = UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
939 } else if (UVH_RH_GAM_MMR_OVERLAY_CONFIG) {
940 union uvh_rh_gam_mmr_overlay_config_u mmr;
942 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG);
943 enable = mmr.s.enable;
945 shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
947 pr_err("UV:%s:RH_GAM_MMR_OVERLAY_CONFIG MMR undefined?\n",
953 map_high("MMR", base, shift, shift, max_pnode, map_uc);
955 pr_info("UV: MMR disabled\n");
958 /* Arch specific ENUM cases */
961 UVY_MMIOH0, UVY_MMIOH1,
962 UVX_MMIOH0, UVX_MMIOH1,
965 /* Calculate and Map MMIOH Regions */
966 static void __init calc_mmioh_map(enum mmioh_arch index,
967 int min_pnode, int max_pnode,
968 int shift, unsigned long base, int m_io, int n_io)
970 unsigned long mmr, nasid_mask;
971 int nasid, min_nasid, max_nasid, lnasid, mapped;
972 int i, fi, li, n, max_io;
975 /* One (UV2) mapping */
976 if (index == UV2_MMIOH) {
977 strscpy(id, "MMIOH", sizeof(id));
983 /* small and large MMIOH mappings */
986 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0;
987 nasid_mask = UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK;
988 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
989 min_nasid = min_pnode;
990 max_nasid = max_pnode;
994 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1;
995 nasid_mask = UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK;
996 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
997 min_nasid = min_pnode;
998 max_nasid = max_pnode;
1002 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0;
1003 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK;
1004 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
1005 min_nasid = min_pnode * 2;
1006 max_nasid = max_pnode * 2;
1010 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1;
1011 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK;
1012 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
1013 min_nasid = min_pnode * 2;
1014 max_nasid = max_pnode * 2;
1018 pr_err("UV:%s:Invalid mapping type:%d\n", __func__, index);
1022 /* enum values chosen so (index mod 2) is MMIOH 0/1 (low/high) */
1023 snprintf(id, sizeof(id), "MMIOH%d", index%2);
1025 max_io = lnasid = fi = li = -1;
1026 for (i = 0; i < n; i++) {
1027 unsigned long m_redirect = mmr + i * 8;
1028 unsigned long redirect = uv_read_local_mmr(m_redirect);
1030 nasid = redirect & nasid_mask;
1032 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
1033 id, redirect, m_redirect, nasid);
1035 /* Invalid NASID check */
1036 if (nasid < min_nasid || max_nasid < nasid) {
1037 /* Not an error: unused table entries get "poison" values */
1038 pr_debug("UV:%s:Invalid NASID(%x):%x (range:%x..%x)\n",
1039 __func__, index, nasid, min_nasid, max_nasid);
1043 if (nasid == lnasid) {
1045 /* Last entry check: */
1050 /* Check if we have a cached (or last) redirect to print: */
1051 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
1052 unsigned long addr1, addr2;
1062 addr1 = (base << shift) + f * (1ULL << m_io);
1063 addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
1064 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
1065 id, fi, li, lnasid, addr1, addr2);
1074 pr_info("UV: %s base:0x%lx shift:%d m_io:%d max_io:%d max_pnode:0x%x\n",
1075 id, base, shift, m_io, max_io, max_pnode);
1077 if (max_io >= 0 && !mapped)
1078 map_high(id, base, shift, m_io, max_io, map_uc);
1081 static __init void map_mmioh_high(int min_pnode, int max_pnode)
1084 if (UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0) {
1085 union uvh_rh10_gam_mmioh_overlay_config0_u mmioh0;
1086 union uvh_rh10_gam_mmioh_overlay_config1_u mmioh1;
1088 mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0);
1089 if (unlikely(mmioh0.s.enable == 0))
1090 pr_info("UV: MMIOH0 disabled\n");
1092 calc_mmioh_map(UVY_MMIOH0, min_pnode, max_pnode,
1093 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1094 mmioh0.s.base, mmioh0.s.m_io, mmioh0.s.n_io);
1096 mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1);
1097 if (unlikely(mmioh1.s.enable == 0))
1098 pr_info("UV: MMIOH1 disabled\n");
1100 calc_mmioh_map(UVY_MMIOH1, min_pnode, max_pnode,
1101 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1102 mmioh1.s.base, mmioh1.s.m_io, mmioh1.s.n_io);
1106 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0) {
1107 union uvh_rh_gam_mmioh_overlay_config0_u mmioh0;
1108 union uvh_rh_gam_mmioh_overlay_config1_u mmioh1;
1110 mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0);
1111 if (unlikely(mmioh0.s.enable == 0))
1112 pr_info("UV: MMIOH0 disabled\n");
1114 unsigned long base = uvxy_field(mmioh0, base, 0);
1115 int m_io = uvxy_field(mmioh0, m_io, 0);
1116 int n_io = uvxy_field(mmioh0, n_io, 0);
1118 calc_mmioh_map(UVX_MMIOH0, min_pnode, max_pnode,
1119 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1123 mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1);
1124 if (unlikely(mmioh1.s.enable == 0))
1125 pr_info("UV: MMIOH1 disabled\n");
1127 unsigned long base = uvxy_field(mmioh1, base, 0);
1128 int m_io = uvxy_field(mmioh1, m_io, 0);
1129 int n_io = uvxy_field(mmioh1, n_io, 0);
1131 calc_mmioh_map(UVX_MMIOH1, min_pnode, max_pnode,
1132 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1139 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG) {
1140 union uvh_rh_gam_mmioh_overlay_config_u mmioh;
1142 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG);
1143 if (unlikely(mmioh.s2.enable == 0))
1144 pr_info("UV: MMIOH disabled\n");
1146 calc_mmioh_map(UV2_MMIOH, min_pnode, max_pnode,
1147 UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT,
1148 mmioh.s2.base, mmioh.s2.m_io, mmioh.s2.n_io);
1153 static __init void map_low_mmrs(void)
1155 if (UV_GLOBAL_MMR32_BASE)
1156 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
1158 if (UV_LOCAL_MMR_BASE)
1159 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
1162 static __init void uv_rtc_init(void)
1167 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
1169 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
1170 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
1172 /* BIOS gives wrong value for clock frequency, so guess: */
1173 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
1175 sn_rtc_cycles_per_second = ticks_per_sec;
1179 /* Direct Legacy VGA I/O traffic to designated IOH */
1180 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
1182 int domain, bus, rc;
1184 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1187 if ((command_bits & PCI_COMMAND_IO) == 0)
1190 domain = pci_domain_nr(pdev->bus);
1191 bus = pdev->bus->number;
1193 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1199 * Called on each CPU to initialize the per_cpu UV data area.
1200 * FIXME: hotplug not supported yet
1202 void uv_cpu_init(void)
1204 /* CPU 0 initialization will be done via uv_system_init. */
1205 if (smp_processor_id() == 0)
1208 uv_hub_info->nr_online_cpus++;
1212 unsigned char m_val;
1213 unsigned char n_val;
1214 unsigned char m_shift;
1215 unsigned char n_lshift;
1218 /* Initialize caller's MN struct and fill in values */
1219 static void get_mn(struct mn *mnp)
1221 memset(mnp, 0, sizeof(*mnp));
1222 mnp->n_val = uv_cpuid.n_skt;
1223 if (is_uv(UV4|UVY)) {
1226 } else if (is_uv3_hub()) {
1227 union uvyh_gr0_gam_gr_config_u m_gr_config;
1229 mnp->m_val = uv_cpuid.m_skt;
1230 m_gr_config.v = uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG);
1231 mnp->n_lshift = m_gr_config.s3.m_skt;
1232 } else if (is_uv2_hub()) {
1233 mnp->m_val = uv_cpuid.m_skt;
1234 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1236 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1239 static void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1244 hi->gpa_mask = mn.m_val ?
1245 (1UL << (mn.m_val + mn.n_val)) - 1 :
1246 (1UL << uv_cpuid.gpa_shift) - 1;
1248 hi->m_val = mn.m_val;
1249 hi->n_val = mn.n_val;
1250 hi->m_shift = mn.m_shift;
1251 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
1252 hi->hub_revision = uv_hub_info->hub_revision;
1253 hi->hub_type = uv_hub_info->hub_type;
1254 hi->pnode_mask = uv_cpuid.pnode_mask;
1255 hi->nasid_shift = uv_cpuid.nasid_shift;
1256 hi->min_pnode = _min_pnode;
1257 hi->min_socket = _min_socket;
1258 hi->node_to_socket = _node_to_socket;
1259 hi->pnode_to_socket = _pnode_to_socket;
1260 hi->socket_to_node = _socket_to_node;
1261 hi->socket_to_pnode = _socket_to_pnode;
1262 hi->gr_table_len = _gr_table_len;
1263 hi->gr_table = _gr_table;
1265 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1266 hi->gnode_extra = (uv_node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1268 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1271 hi->global_mmr_base = uv_gp_table->mmr_base;
1272 hi->global_mmr_shift = uv_gp_table->mmr_shift;
1273 hi->global_gru_base = uv_gp_table->gru_base;
1274 hi->global_gru_shift = uv_gp_table->gru_shift;
1275 hi->gpa_shift = uv_gp_table->gpa_shift;
1276 hi->gpa_mask = (1UL << hi->gpa_shift) - 1;
1278 hi->global_mmr_base =
1279 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG) &
1281 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1284 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1286 hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1288 /* Show system specific info: */
1289 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1290 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1291 pr_info("UV: mmr_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift);
1292 if (hi->global_gru_base)
1293 pr_info("UV: gru_base/shift:0x%lx/%ld\n",
1294 hi->global_gru_base, hi->global_gru_shift);
1296 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1299 static void __init decode_gam_params(unsigned long ptr)
1301 uv_gp_table = (struct uv_gam_parameters *)ptr;
1303 pr_info("UV: GAM Params...\n");
1304 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1305 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1306 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1307 uv_gp_table->gpa_shift);
1310 static void __init decode_gam_rng_tbl(unsigned long ptr)
1312 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1313 unsigned long lgre = 0, gend = 0;
1315 int sock_min = INT_MAX, pnode_min = INT_MAX;
1316 int sock_max = -1, pnode_max = -1;
1319 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1320 unsigned long size = ((unsigned long)(gre->limit - lgre)
1321 << UV_GAM_RANGE_SHFT);
1323 char suffix[] = " KMGTPE";
1326 while (size > 9999 && order < sizeof(suffix)) {
1331 /* adjust max block size to current range start */
1332 if (gre->type == 1 || gre->type == 2)
1333 if (adj_blksize(lgre))
1337 pr_info("UV: GAM Range Table...\n");
1338 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1340 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n",
1342 (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1343 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1344 flag, size, suffix[order],
1345 gre->type, gre->nasid, gre->sockid, gre->pnode);
1347 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1348 gend = (unsigned long)gre->limit << UV_GAM_RANGE_SHFT;
1350 /* update to next range start */
1352 if (sock_min > gre->sockid)
1353 sock_min = gre->sockid;
1354 if (sock_max < gre->sockid)
1355 sock_max = gre->sockid;
1356 if (pnode_min > gre->pnode)
1357 pnode_min = gre->pnode;
1358 if (pnode_max < gre->pnode)
1359 pnode_max = gre->pnode;
1361 _min_socket = sock_min;
1362 _max_socket = sock_max;
1363 _min_pnode = pnode_min;
1364 _max_pnode = pnode_max;
1365 _gr_table_len = index;
1367 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x), pnodes(min:%x,max:%x), gap_end(%d)\n",
1368 index, _min_socket, _max_socket, _min_pnode, _max_pnode, fls64(gend));
1371 /* Walk through UVsystab decoding the fields */
1372 static int __init decode_uv_systab(void)
1374 struct uv_systab *st;
1377 /* Get mapped UVsystab pointer */
1380 /* If UVsystab is version 1, there is no extended UVsystab */
1381 if (st && st->revision == UV_SYSTAB_VERSION_1)
1384 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1385 int rev = st ? st->revision : 0;
1387 pr_err("UV: BIOS UVsystab mismatch, (%x < %x)\n",
1388 rev, UV_SYSTAB_VERSION_UV4_LATEST);
1389 pr_err("UV: Does not support UV, switch to non-UV x86_64\n");
1390 uv_system_type = UV_NONE;
1395 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1396 unsigned long ptr = st->entry[i].offset;
1401 /* point to payload */
1402 ptr += (unsigned long)st;
1404 switch (st->entry[i].type) {
1405 case UV_SYSTAB_TYPE_GAM_PARAMS:
1406 decode_gam_params(ptr);
1409 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1410 decode_gam_rng_tbl(ptr);
1413 case UV_SYSTAB_TYPE_ARCH_TYPE:
1414 /* already processed in early startup */
1418 pr_err("UV:%s:Unrecognized UV_SYSTAB_TYPE:%d, skipped\n",
1419 __func__, st->entry[i].type);
1427 * Given a bitmask 'bits' representing presnt blades, numbered
1428 * starting at 'base', masking off unused high bits of blade number
1429 * with 'mask', update the minimum and maximum blade numbers that we
1430 * have found. (Masking with 'mask' necessary because of BIOS
1431 * treatment of system partitioning when creating this table we are
1434 static inline void blade_update_min_max(unsigned long bits, int base, int mask, int *min, int *max)
1440 first = (base + __ffs(bits)) & mask;
1441 last = (base + __fls(bits)) & mask;
1449 /* Set up physical blade translations from UVH_NODE_PRESENT_TABLE */
1450 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1454 int sock_min = INT_MAX, sock_max = -1, s_mask;
1456 s_mask = (1 << uv_cpuid.n_skt) - 1;
1458 if (UVH_NODE_PRESENT_TABLE) {
1459 pr_info("UV: NODE_PRESENT_DEPTH = %d\n",
1460 UVH_NODE_PRESENT_TABLE_DEPTH);
1461 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1462 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1463 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1464 blade_update_min_max(np, i * 64, s_mask, &sock_min, &sock_max);
1467 if (UVH_NODE_PRESENT_0) {
1468 np = uv_read_local_mmr(UVH_NODE_PRESENT_0);
1469 pr_info("UV: NODE_PRESENT_0 = 0x%016lx\n", np);
1470 blade_update_min_max(np, 0, s_mask, &sock_min, &sock_max);
1472 if (UVH_NODE_PRESENT_1) {
1473 np = uv_read_local_mmr(UVH_NODE_PRESENT_1);
1474 pr_info("UV: NODE_PRESENT_1 = 0x%016lx\n", np);
1475 blade_update_min_max(np, 64, s_mask, &sock_min, &sock_max);
1478 /* Only update if we actually found some bits indicating blades present */
1479 if (sock_max >= sock_min) {
1480 _min_socket = sock_min;
1481 _max_socket = sock_max;
1482 uv_pb = sock_max - sock_min + 1;
1484 if (uv_possible_blades != uv_pb)
1485 uv_possible_blades = uv_pb;
1487 pr_info("UV: number nodes/possible blades %d (%d - %d)\n",
1488 uv_pb, sock_min, sock_max);
1491 static int __init alloc_conv_table(int num_elem, unsigned short **table)
1496 bytes = num_elem * sizeof(*table[0]);
1497 *table = kmalloc(bytes, GFP_KERNEL);
1498 if (WARN_ON_ONCE(!*table))
1500 for (i = 0; i < num_elem; i++)
1501 ((unsigned short *)*table)[i] = SOCK_EMPTY;
1505 /* Remove conversion table if it's 1:1 */
1506 #define FREE_1_TO_1_TABLE(tbl, min, max, max2) free_1_to_1_table(&tbl, #tbl, min, max, max2)
1508 static void __init free_1_to_1_table(unsigned short **tp, char *tname, int min, int max, int max2)
1511 unsigned short *table = *tp;
1517 for (i = 0; i < max; i++) {
1523 pr_info("UV: %s is 1:1, conversion table removed\n", tname);
1527 * Build Socket Tables
1528 * If the number of nodes is >1 per socket, socket to node table will
1529 * contain lowest node number on that socket.
1531 static void __init build_socket_tables(void)
1533 struct uv_gam_range_entry *gre = uv_gre_table;
1534 int nums, numn, nump;
1535 int i, lnid, apicid;
1536 int minsock = _min_socket;
1537 int maxsock = _max_socket;
1538 int minpnode = _min_pnode;
1539 int maxpnode = _max_pnode;
1542 if (is_uv2_hub() || is_uv3_hub()) {
1543 pr_info("UV: No UVsystab socket table, ignoring\n");
1546 pr_err("UV: Error: UVsystab address translations not available!\n");
1551 numn = num_possible_nodes();
1552 nump = maxpnode - minpnode + 1;
1553 nums = maxsock - minsock + 1;
1555 /* Allocate and clear tables */
1556 if ((alloc_conv_table(nump, &_pnode_to_socket) < 0)
1557 || (alloc_conv_table(nums, &_socket_to_pnode) < 0)
1558 || (alloc_conv_table(numn, &_node_to_socket) < 0)
1559 || (alloc_conv_table(nums, &_socket_to_node) < 0)) {
1560 kfree(_pnode_to_socket);
1561 kfree(_socket_to_pnode);
1562 kfree(_node_to_socket);
1566 /* Fill in pnode/node/addr conversion list values: */
1567 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1568 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1570 i = gre->sockid - minsock;
1571 if (_socket_to_pnode[i] == SOCK_EMPTY)
1572 _socket_to_pnode[i] = gre->pnode;
1574 i = gre->pnode - minpnode;
1575 if (_pnode_to_socket[i] == SOCK_EMPTY)
1576 _pnode_to_socket[i] = gre->sockid;
1578 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1579 gre->sockid, gre->type, gre->nasid,
1580 _socket_to_pnode[gre->sockid - minsock],
1581 _pnode_to_socket[gre->pnode - minpnode]);
1584 /* Set socket -> node values: */
1585 lnid = NUMA_NO_NODE;
1586 for (apicid = 0; apicid < ARRAY_SIZE(__apicid_to_node); apicid++) {
1587 int nid = __apicid_to_node[apicid];
1590 if ((nid == NUMA_NO_NODE) || (lnid == nid))
1594 sockid = apicid >> uv_cpuid.socketid_shift;
1596 if (_socket_to_node[sockid - minsock] == SOCK_EMPTY)
1597 _socket_to_node[sockid - minsock] = nid;
1599 if (_node_to_socket[nid] == SOCK_EMPTY)
1600 _node_to_socket[nid] = sockid;
1602 pr_info("UV: sid:%02x: apicid:%04x socket:%02d node:%03x s2n:%03x\n",
1605 _node_to_socket[nid],
1607 _socket_to_node[sockid - minsock]);
1611 * If e.g. socket id == pnode for all pnodes,
1612 * system runs faster by removing corresponding conversion table.
1614 FREE_1_TO_1_TABLE(_socket_to_node, _min_socket, nums, numn);
1615 FREE_1_TO_1_TABLE(_node_to_socket, _min_socket, nums, numn);
1616 FREE_1_TO_1_TABLE(_socket_to_pnode, _min_pnode, nums, nump);
1617 FREE_1_TO_1_TABLE(_pnode_to_socket, _min_pnode, nums, nump);
1620 /* Check which reboot to use */
1621 static void check_efi_reboot(void)
1623 /* If EFI reboot not available, use ACPI reboot */
1624 if (!efi_enabled(EFI_BOOT))
1625 reboot_type = BOOT_ACPI;
1629 * User proc fs file handling now deprecated.
1630 * Recommend using /sys/firmware/sgi_uv/... instead.
1632 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data)
1634 pr_notice_once("%s: using deprecated /proc/sgi_uv/hubbed, use /sys/firmware/sgi_uv/hub_type\n",
1636 seq_printf(file, "0x%x\n", uv_hubbed_system);
1640 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data)
1642 pr_notice_once("%s: using deprecated /proc/sgi_uv/hubless, use /sys/firmware/sgi_uv/hubless\n",
1644 seq_printf(file, "0x%x\n", uv_hubless_system);
1648 static int __maybe_unused proc_archtype_show(struct seq_file *file, void *data)
1650 pr_notice_once("%s: using deprecated /proc/sgi_uv/archtype, use /sys/firmware/sgi_uv/archtype\n",
1652 seq_printf(file, "%s/%s\n", uv_archtype, oem_table_id);
1656 static __init void uv_setup_proc_files(int hubless)
1658 struct proc_dir_entry *pde;
1660 pde = proc_mkdir(UV_PROC_NODE, NULL);
1661 proc_create_single("archtype", 0, pde, proc_archtype_show);
1663 proc_create_single("hubless", 0, pde, proc_hubless_show);
1665 proc_create_single("hubbed", 0, pde, proc_hubbed_show);
1668 /* Initialize UV hubless systems */
1669 static __init int uv_system_init_hubless(void)
1673 /* Setup PCH NMI handler */
1674 uv_nmi_setup_hubless();
1676 /* Init kernel/BIOS interface */
1677 rc = uv_bios_init();
1681 /* Process UVsystab */
1682 rc = decode_uv_systab();
1686 /* Set section block size for current node memory */
1689 /* Create user access node */
1691 uv_setup_proc_files(1);
1698 static void __init uv_system_init_hub(void)
1700 struct uv_hub_info_s hub_info = {0};
1701 int bytes, cpu, nodeid, bid;
1702 unsigned short min_pnode = USHRT_MAX, max_pnode = 0;
1703 char *hub = is_uv5_hub() ? "UV500" :
1704 is_uv4_hub() ? "UV400" :
1705 is_uv3_hub() ? "UV300" :
1706 is_uv2_hub() ? "UV2000/3000" : NULL;
1707 struct uv_hub_info_s **uv_hub_info_list_blade;
1710 pr_err("UV: Unknown/unsupported UV hub\n");
1713 pr_info("UV: Found %s hub\n", hub);
1717 /* Get uv_systab for decoding, setup UV BIOS calls */
1720 /* If there's an UVsystab problem then abort UV init: */
1721 if (decode_uv_systab() < 0) {
1722 pr_err("UV: Mangled UVsystab format\n");
1726 build_socket_tables();
1727 build_uv_gr_table();
1729 uv_init_hub_info(&hub_info);
1730 /* If UV2 or UV3 may need to get # blades from HW */
1731 if (is_uv(UV2|UV3) && !uv_gre_table)
1732 boot_init_possible_blades(&hub_info);
1734 /* min/max sockets set in decode_gam_rng_tbl */
1735 uv_possible_blades = (_max_socket - _min_socket) + 1;
1737 /* uv_num_possible_blades() is really the hub count: */
1738 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1740 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1741 hub_info.coherency_domain_number = sn_coherency_id;
1745 * __uv_hub_info_list[] is indexed by node, but there is only
1746 * one hub_info structure per blade. First, allocate one
1747 * structure per blade. Further down we create a per-node
1748 * table (__uv_hub_info_list[]) pointing to hub_info
1749 * structures for the correct blade.
1752 bytes = sizeof(void *) * uv_num_possible_blades();
1753 uv_hub_info_list_blade = kzalloc(bytes, GFP_KERNEL);
1754 if (WARN_ON_ONCE(!uv_hub_info_list_blade))
1757 bytes = sizeof(struct uv_hub_info_s);
1758 for_each_possible_blade(bid) {
1759 struct uv_hub_info_s *new_hub;
1761 /* Allocate & fill new per hub info list */
1762 new_hub = (bid == 0) ? &uv_hub_info_node0
1763 : kzalloc_node(bytes, GFP_KERNEL, uv_blade_to_node(bid));
1764 if (WARN_ON_ONCE(!new_hub)) {
1765 /* do not kfree() bid 0, which is statically allocated */
1767 kfree(uv_hub_info_list_blade[bid]);
1768 kfree(uv_hub_info_list_blade);
1772 uv_hub_info_list_blade[bid] = new_hub;
1773 *new_hub = hub_info;
1775 /* Use information from GAM table if available: */
1777 new_hub->pnode = uv_blade_to_pnode(bid);
1778 else /* Or fill in during CPU loop: */
1779 new_hub->pnode = 0xffff;
1781 new_hub->numa_blade_id = bid;
1782 new_hub->memory_nid = NUMA_NO_NODE;
1783 new_hub->nr_possible_cpus = 0;
1784 new_hub->nr_online_cpus = 0;
1788 * Now populate __uv_hub_info_list[] for each node with the
1789 * pointer to the struct for the blade it resides on.
1792 bytes = sizeof(void *) * num_possible_nodes();
1793 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1794 if (WARN_ON_ONCE(!__uv_hub_info_list)) {
1795 for_each_possible_blade(bid)
1796 /* bid 0 is statically allocated */
1798 kfree(uv_hub_info_list_blade[bid]);
1799 kfree(uv_hub_info_list_blade);
1803 for_each_node(nodeid)
1804 __uv_hub_info_list[nodeid] = uv_hub_info_list_blade[uv_node_to_blade_id(nodeid)];
1806 /* Initialize per CPU info: */
1807 for_each_possible_cpu(cpu) {
1808 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1810 unsigned short pnode;
1812 pnode = uv_apicid_to_pnode(apicid);
1813 bid = uv_pnode_to_socket(pnode) - _min_socket;
1815 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list_blade[bid];
1816 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1817 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE)
1818 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1820 if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1821 uv_cpu_hub_info(cpu)->pnode = pnode;
1824 for_each_possible_blade(bid) {
1825 unsigned short pnode = uv_hub_info_list_blade[bid]->pnode;
1827 if (pnode == 0xffff)
1830 min_pnode = min(pnode, min_pnode);
1831 max_pnode = max(pnode, max_pnode);
1832 pr_info("UV: HUB:%2d pn:%02x nrcpus:%d\n",
1834 uv_hub_info_list_blade[bid]->pnode,
1835 uv_hub_info_list_blade[bid]->nr_possible_cpus);
1838 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1839 map_gru_high(max_pnode);
1840 map_mmr_high(max_pnode);
1841 map_mmioh_high(min_pnode, max_pnode);
1843 kfree(uv_hub_info_list_blade);
1844 uv_hub_info_list_blade = NULL;
1848 uv_setup_proc_files(0);
1850 /* Register Legacy VGA I/O redirection handler: */
1851 pci_register_set_vga_state(uv_set_vga_state);
1857 * There is a different code path needed to initialize a UV system that does
1858 * not have a "UV HUB" (referred to as "hubless").
1860 void __init uv_system_init(void)
1862 if (likely(!is_uv_system() && !is_uv_hubless(1)))
1866 uv_system_init_hub();
1868 uv_system_init_hubless();
1871 apic_driver(apic_x2apic_uv_x);