2 * Local APIC related interfaces to support IOAPIC, MSI, etc.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Enable support of hierarchical irqdomains
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/interrupt.h>
14 #include <linux/seq_file.h>
15 #include <linux/init.h>
16 #include <linux/compiler.h>
17 #include <linux/slab.h>
18 #include <asm/irqdomain.h>
19 #include <asm/hw_irq.h>
21 #include <asm/i8259.h>
23 #include <asm/irq_remapping.h>
25 #include <asm/trace/irq_vectors.h>
27 struct apic_chip_data {
28 struct irq_cfg hw_irq_cfg;
30 unsigned int prev_vector;
32 unsigned int prev_cpu;
34 struct hlist_node clist;
35 unsigned int move_in_progress : 1,
41 struct irq_domain *x86_vector_domain;
42 EXPORT_SYMBOL_GPL(x86_vector_domain);
43 static DEFINE_RAW_SPINLOCK(vector_lock);
44 static cpumask_var_t vector_searchmask;
45 static struct irq_chip lapic_controller;
46 static struct irq_matrix *vector_matrix;
48 static DEFINE_PER_CPU(struct hlist_head, cleanup_list);
51 void lock_vector_lock(void)
53 /* Used to the online set of cpus does not change
54 * during assign_irq_vector.
56 raw_spin_lock(&vector_lock);
59 void unlock_vector_lock(void)
61 raw_spin_unlock(&vector_lock);
64 void init_irq_alloc_info(struct irq_alloc_info *info,
65 const struct cpumask *mask)
67 memset(info, 0, sizeof(*info));
71 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
76 memset(dst, 0, sizeof(*dst));
79 static struct apic_chip_data *apic_chip_data(struct irq_data *irqd)
84 while (irqd->parent_data)
85 irqd = irqd->parent_data;
87 return irqd->chip_data;
90 struct irq_cfg *irqd_cfg(struct irq_data *irqd)
92 struct apic_chip_data *apicd = apic_chip_data(irqd);
94 return apicd ? &apicd->hw_irq_cfg : NULL;
96 EXPORT_SYMBOL_GPL(irqd_cfg);
98 struct irq_cfg *irq_cfg(unsigned int irq)
100 return irqd_cfg(irq_get_irq_data(irq));
103 static struct apic_chip_data *alloc_apic_chip_data(int node)
105 struct apic_chip_data *apicd;
107 apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node);
109 INIT_HLIST_NODE(&apicd->clist);
113 static void free_apic_chip_data(struct apic_chip_data *apicd)
118 static void apic_update_irq_cfg(struct irq_data *irqd, unsigned int vector,
121 struct apic_chip_data *apicd = apic_chip_data(irqd);
123 lockdep_assert_held(&vector_lock);
125 apicd->hw_irq_cfg.vector = vector;
126 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu);
127 irq_data_update_effective_affinity(irqd, cpumask_of(cpu));
128 trace_vector_config(irqd->irq, vector, cpu,
129 apicd->hw_irq_cfg.dest_apicid);
132 static void apic_update_vector(struct irq_data *irqd, unsigned int newvec,
135 struct apic_chip_data *apicd = apic_chip_data(irqd);
136 struct irq_desc *desc = irq_data_to_desc(irqd);
138 lockdep_assert_held(&vector_lock);
140 trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector,
143 /* Setup the vector move, if required */
144 if (apicd->vector && cpu_online(apicd->cpu)) {
145 apicd->move_in_progress = true;
146 apicd->prev_vector = apicd->vector;
147 apicd->prev_cpu = apicd->cpu;
149 apicd->prev_vector = 0;
152 apicd->vector = newvec;
154 BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec]));
155 per_cpu(vector_irq, newcpu)[newvec] = desc;
158 static void vector_assign_managed_shutdown(struct irq_data *irqd)
160 unsigned int cpu = cpumask_first(cpu_online_mask);
162 apic_update_irq_cfg(irqd, MANAGED_IRQ_SHUTDOWN_VECTOR, cpu);
165 static int reserve_managed_vector(struct irq_data *irqd)
167 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
168 struct apic_chip_data *apicd = apic_chip_data(irqd);
172 raw_spin_lock_irqsave(&vector_lock, flags);
173 apicd->is_managed = true;
174 ret = irq_matrix_reserve_managed(vector_matrix, affmsk);
175 raw_spin_unlock_irqrestore(&vector_lock, flags);
176 trace_vector_reserve_managed(irqd->irq, ret);
180 static void reserve_irq_vector_locked(struct irq_data *irqd)
182 struct apic_chip_data *apicd = apic_chip_data(irqd);
184 irq_matrix_reserve(vector_matrix);
185 apicd->can_reserve = true;
186 apicd->has_reserved = true;
187 irqd_set_can_reserve(irqd);
188 trace_vector_reserve(irqd->irq, 0);
189 vector_assign_managed_shutdown(irqd);
192 static int reserve_irq_vector(struct irq_data *irqd)
196 raw_spin_lock_irqsave(&vector_lock, flags);
197 reserve_irq_vector_locked(irqd);
198 raw_spin_unlock_irqrestore(&vector_lock, flags);
202 static int allocate_vector(struct irq_data *irqd, const struct cpumask *dest)
204 struct apic_chip_data *apicd = apic_chip_data(irqd);
205 bool resvd = apicd->has_reserved;
206 unsigned int cpu = apicd->cpu;
207 int vector = apicd->vector;
209 lockdep_assert_held(&vector_lock);
212 * If the current target CPU is online and in the new requested
213 * affinity mask, there is no point in moving the interrupt from
214 * one CPU to another.
216 if (vector && cpu_online(cpu) && cpumask_test_cpu(cpu, dest))
219 vector = irq_matrix_alloc(vector_matrix, dest, resvd, &cpu);
221 apic_update_vector(irqd, vector, cpu);
222 trace_vector_alloc(irqd->irq, vector, resvd, vector);
226 static int assign_vector_locked(struct irq_data *irqd,
227 const struct cpumask *dest)
229 struct apic_chip_data *apicd = apic_chip_data(irqd);
230 int vector = allocate_vector(irqd, dest);
235 apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu);
239 static int assign_irq_vector(struct irq_data *irqd, const struct cpumask *dest)
244 raw_spin_lock_irqsave(&vector_lock, flags);
245 cpumask_and(vector_searchmask, dest, cpu_online_mask);
246 ret = assign_vector_locked(irqd, vector_searchmask);
247 raw_spin_unlock_irqrestore(&vector_lock, flags);
251 static int assign_irq_vector_any_locked(struct irq_data *irqd)
253 /* Get the affinity mask - either irq_default_affinity or (user) set */
254 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
255 int node = irq_data_get_node(irqd);
257 if (node == NUMA_NO_NODE)
259 /* Try the intersection of @affmsk and node mask */
260 cpumask_and(vector_searchmask, cpumask_of_node(node), affmsk);
261 if (!assign_vector_locked(irqd, vector_searchmask))
263 /* Try the node mask */
264 if (!assign_vector_locked(irqd, cpumask_of_node(node)))
267 /* Try the full affinity mask */
268 cpumask_and(vector_searchmask, affmsk, cpu_online_mask);
269 if (!assign_vector_locked(irqd, vector_searchmask))
271 /* Try the full online mask */
272 return assign_vector_locked(irqd, cpu_online_mask);
276 assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info)
278 if (irqd_affinity_is_managed(irqd))
279 return reserve_managed_vector(irqd);
281 return assign_irq_vector(irqd, info->mask);
283 * Make only a global reservation with no guarantee. A real vector
284 * is associated at activation time.
286 return reserve_irq_vector(irqd);
290 assign_managed_vector(struct irq_data *irqd, const struct cpumask *dest)
292 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
293 struct apic_chip_data *apicd = apic_chip_data(irqd);
296 cpumask_and(vector_searchmask, vector_searchmask, affmsk);
297 cpu = cpumask_first(vector_searchmask);
298 if (cpu >= nr_cpu_ids)
300 /* set_affinity might call here for nothing */
301 if (apicd->vector && cpumask_test_cpu(apicd->cpu, vector_searchmask))
303 vector = irq_matrix_alloc_managed(vector_matrix, cpu);
304 trace_vector_alloc_managed(irqd->irq, vector, vector);
307 apic_update_vector(irqd, vector, cpu);
308 apic_update_irq_cfg(irqd, vector, cpu);
312 static void clear_irq_vector(struct irq_data *irqd)
314 struct apic_chip_data *apicd = apic_chip_data(irqd);
315 bool managed = irqd_affinity_is_managed(irqd);
316 unsigned int vector = apicd->vector;
318 lockdep_assert_held(&vector_lock);
323 trace_vector_clear(irqd->irq, vector, apicd->cpu, apicd->prev_vector,
326 per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_UNUSED;
327 irq_matrix_free(vector_matrix, apicd->cpu, vector, managed);
330 /* Clean up move in progress */
331 vector = apicd->prev_vector;
335 per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED;
336 irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed);
337 apicd->prev_vector = 0;
338 apicd->move_in_progress = 0;
339 hlist_del_init(&apicd->clist);
342 static void x86_vector_deactivate(struct irq_domain *dom, struct irq_data *irqd)
344 struct apic_chip_data *apicd = apic_chip_data(irqd);
347 trace_vector_deactivate(irqd->irq, apicd->is_managed,
348 apicd->can_reserve, false);
350 /* Regular fixed assigned interrupt */
351 if (!apicd->is_managed && !apicd->can_reserve)
353 /* If the interrupt has a global reservation, nothing to do */
354 if (apicd->has_reserved)
357 raw_spin_lock_irqsave(&vector_lock, flags);
358 clear_irq_vector(irqd);
359 if (apicd->can_reserve)
360 reserve_irq_vector_locked(irqd);
362 vector_assign_managed_shutdown(irqd);
363 raw_spin_unlock_irqrestore(&vector_lock, flags);
366 static int activate_reserved(struct irq_data *irqd)
368 struct apic_chip_data *apicd = apic_chip_data(irqd);
371 ret = assign_irq_vector_any_locked(irqd);
373 apicd->has_reserved = false;
375 * Core might have disabled reservation mode after
376 * allocating the irq descriptor. Ideally this should
377 * happen before allocation time, but that would require
378 * completely convoluted ways of transporting that
381 if (!irqd_can_reserve(irqd))
382 apicd->can_reserve = false;
387 static int activate_managed(struct irq_data *irqd)
389 const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
392 cpumask_and(vector_searchmask, dest, cpu_online_mask);
393 if (WARN_ON_ONCE(cpumask_empty(vector_searchmask))) {
394 /* Something in the core code broke! Survive gracefully */
395 pr_err("Managed startup for irq %u, but no CPU\n", irqd->irq);
399 ret = assign_managed_vector(irqd, vector_searchmask);
401 * This should not happen. The vector reservation got buggered. Handle
404 if (WARN_ON_ONCE(ret < 0)) {
405 pr_err("Managed startup irq %u, no vector available\n",
411 static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd,
414 struct apic_chip_data *apicd = apic_chip_data(irqd);
418 trace_vector_activate(irqd->irq, apicd->is_managed,
419 apicd->can_reserve, reserve);
421 /* Nothing to do for fixed assigned vectors */
422 if (!apicd->can_reserve && !apicd->is_managed)
425 raw_spin_lock_irqsave(&vector_lock, flags);
426 if (reserve || irqd_is_managed_and_shutdown(irqd))
427 vector_assign_managed_shutdown(irqd);
428 else if (apicd->is_managed)
429 ret = activate_managed(irqd);
430 else if (apicd->has_reserved)
431 ret = activate_reserved(irqd);
432 raw_spin_unlock_irqrestore(&vector_lock, flags);
436 static void vector_free_reserved_and_managed(struct irq_data *irqd)
438 const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
439 struct apic_chip_data *apicd = apic_chip_data(irqd);
441 trace_vector_teardown(irqd->irq, apicd->is_managed,
442 apicd->has_reserved);
444 if (apicd->has_reserved)
445 irq_matrix_remove_reserved(vector_matrix);
446 if (apicd->is_managed)
447 irq_matrix_remove_managed(vector_matrix, dest);
450 static void x86_vector_free_irqs(struct irq_domain *domain,
451 unsigned int virq, unsigned int nr_irqs)
453 struct apic_chip_data *apicd;
454 struct irq_data *irqd;
458 for (i = 0; i < nr_irqs; i++) {
459 irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i);
460 if (irqd && irqd->chip_data) {
461 raw_spin_lock_irqsave(&vector_lock, flags);
462 clear_irq_vector(irqd);
463 vector_free_reserved_and_managed(irqd);
464 apicd = irqd->chip_data;
465 irq_domain_reset_irq_data(irqd);
466 raw_spin_unlock_irqrestore(&vector_lock, flags);
467 free_apic_chip_data(apicd);
472 static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd,
473 struct apic_chip_data *apicd)
476 bool realloc = false;
478 apicd->vector = ISA_IRQ_VECTOR(virq);
481 raw_spin_lock_irqsave(&vector_lock, flags);
483 * If the interrupt is activated, then it must stay at this vector
484 * position. That's usually the timer interrupt (0).
486 if (irqd_is_activated(irqd)) {
487 trace_vector_setup(virq, true, 0);
488 apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu);
490 /* Release the vector */
491 apicd->can_reserve = true;
492 irqd_set_can_reserve(irqd);
493 clear_irq_vector(irqd);
496 raw_spin_unlock_irqrestore(&vector_lock, flags);
500 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
501 unsigned int nr_irqs, void *arg)
503 struct irq_alloc_info *info = arg;
504 struct apic_chip_data *apicd;
505 struct irq_data *irqd;
511 /* Currently vector allocator can't guarantee contiguous allocations */
512 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
515 for (i = 0; i < nr_irqs; i++) {
516 irqd = irq_domain_get_irq_data(domain, virq + i);
518 node = irq_data_get_node(irqd);
519 WARN_ON_ONCE(irqd->chip_data);
520 apicd = alloc_apic_chip_data(node);
526 apicd->irq = virq + i;
527 irqd->chip = &lapic_controller;
528 irqd->chip_data = apicd;
529 irqd->hwirq = virq + i;
530 irqd_set_single_target(irqd);
532 * Legacy vectors are already assigned when the IOAPIC
533 * takes them over. They stay on the same vector. This is
534 * required for check_timer() to work correctly as it might
535 * switch back to legacy mode. Only update the hardware
538 if (info->flags & X86_IRQ_ALLOC_LEGACY) {
539 if (!vector_configure_legacy(virq + i, irqd, apicd))
543 err = assign_irq_vector_policy(irqd, info);
544 trace_vector_setup(virq + i, false, err);
552 x86_vector_free_irqs(domain, virq, i + 1);
556 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
557 static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d,
558 struct irq_data *irqd, int ind)
560 unsigned int cpu, vector, prev_cpu, prev_vector;
561 struct apic_chip_data *apicd;
566 irq_matrix_debug_show(m, vector_matrix, ind);
571 if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) {
572 seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq));
573 seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, "");
577 apicd = irqd->chip_data;
579 seq_printf(m, "%*sVector: Not assigned\n", ind, "");
583 raw_spin_lock_irqsave(&vector_lock, flags);
585 vector = apicd->vector;
586 prev_cpu = apicd->prev_cpu;
587 prev_vector = apicd->prev_vector;
588 raw_spin_unlock_irqrestore(&vector_lock, flags);
589 seq_printf(m, "%*sVector: %5u\n", ind, "", vector);
590 seq_printf(m, "%*sTarget: %5u\n", ind, "", cpu);
592 seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", prev_vector);
593 seq_printf(m, "%*sPrevious target: %5u\n", ind, "", prev_cpu);
598 static const struct irq_domain_ops x86_vector_domain_ops = {
599 .alloc = x86_vector_alloc_irqs,
600 .free = x86_vector_free_irqs,
601 .activate = x86_vector_activate,
602 .deactivate = x86_vector_deactivate,
603 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
604 .debug_show = x86_vector_debug_show,
608 int __init arch_probe_nr_irqs(void)
612 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
613 nr_irqs = NR_VECTORS * nr_cpu_ids;
615 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
616 #if defined(CONFIG_PCI_MSI)
618 * for MSI and HT dyn irq
620 if (gsi_top <= NR_IRQS_LEGACY)
621 nr += 8 * nr_cpu_ids;
629 * We don't know if PIC is present at this point so we need to do
630 * probe() to get the right number of legacy IRQs.
632 return legacy_pic->probe();
635 void lapic_assign_legacy_vector(unsigned int irq, bool replace)
638 * Use assign system here so it wont get accounted as allocated
639 * and moveable in the cpu hotplug check and it prevents managed
640 * irq reservation from touching it.
642 irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace);
645 void __init lapic_assign_system_vectors(void)
647 unsigned int i, vector = 0;
649 for_each_set_bit_from(vector, system_vectors, NR_VECTORS)
650 irq_matrix_assign_system(vector_matrix, vector, false);
652 if (nr_legacy_irqs() > 1)
653 lapic_assign_legacy_vector(PIC_CASCADE_IR, false);
655 /* System vectors are reserved, online it */
656 irq_matrix_online(vector_matrix);
658 /* Mark the preallocated legacy interrupts */
659 for (i = 0; i < nr_legacy_irqs(); i++) {
660 if (i != PIC_CASCADE_IR)
661 irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i));
665 int __init arch_early_irq_init(void)
667 struct fwnode_handle *fn;
669 fn = irq_domain_alloc_named_fwnode("VECTOR");
671 x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops,
673 BUG_ON(x86_vector_domain == NULL);
674 irq_domain_free_fwnode(fn);
675 irq_set_default_host(x86_vector_domain);
677 arch_init_msi_domain(x86_vector_domain);
679 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
682 * Allocate the vector matrix allocator data structure and limit the
685 vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR,
686 FIRST_SYSTEM_VECTOR);
687 BUG_ON(!vector_matrix);
689 return arch_early_ioapic_init();
694 static struct irq_desc *__setup_vector_irq(int vector)
696 int isairq = vector - ISA_IRQ_VECTOR(0);
698 /* Check whether the irq is in the legacy space */
699 if (isairq < 0 || isairq >= nr_legacy_irqs())
700 return VECTOR_UNUSED;
701 /* Check whether the irq is handled by the IOAPIC */
702 if (test_bit(isairq, &io_apic_irqs))
703 return VECTOR_UNUSED;
704 return irq_to_desc(isairq);
707 /* Online the local APIC infrastructure and initialize the vectors */
708 void lapic_online(void)
712 lockdep_assert_held(&vector_lock);
714 /* Online the vector matrix array for this CPU */
715 irq_matrix_online(vector_matrix);
718 * The interrupt affinity logic never targets interrupts to offline
719 * CPUs. The exception are the legacy PIC interrupts. In general
720 * they are only targeted to CPU0, but depending on the platform
721 * they can be distributed to any online CPU in hardware. The
722 * kernel has no influence on that. So all active legacy vectors
723 * must be installed on all CPUs. All non legacy interrupts can be
726 for (vector = 0; vector < NR_VECTORS; vector++)
727 this_cpu_write(vector_irq[vector], __setup_vector_irq(vector));
730 void lapic_offline(void)
733 irq_matrix_offline(vector_matrix);
734 unlock_vector_lock();
737 static int apic_set_affinity(struct irq_data *irqd,
738 const struct cpumask *dest, bool force)
740 struct apic_chip_data *apicd = apic_chip_data(irqd);
744 * Core code can call here for inactive interrupts. For inactive
745 * interrupts which use managed or reservation mode there is no
746 * point in going through the vector assignment right now as the
747 * activation will assign a vector which fits the destination
748 * cpumask. Let the core code store the destination mask and be
751 if (!irqd_is_activated(irqd) &&
752 (apicd->is_managed || apicd->can_reserve))
753 return IRQ_SET_MASK_OK;
755 raw_spin_lock(&vector_lock);
756 cpumask_and(vector_searchmask, dest, cpu_online_mask);
757 if (irqd_affinity_is_managed(irqd))
758 err = assign_managed_vector(irqd, vector_searchmask);
760 err = assign_vector_locked(irqd, vector_searchmask);
761 raw_spin_unlock(&vector_lock);
762 return err ? err : IRQ_SET_MASK_OK;
766 # define apic_set_affinity NULL
769 static int apic_retrigger_irq(struct irq_data *irqd)
771 struct apic_chip_data *apicd = apic_chip_data(irqd);
774 raw_spin_lock_irqsave(&vector_lock, flags);
775 apic->send_IPI(apicd->cpu, apicd->vector);
776 raw_spin_unlock_irqrestore(&vector_lock, flags);
781 void apic_ack_edge(struct irq_data *irqd)
783 irq_complete_move(irqd_cfg(irqd));
788 static struct irq_chip lapic_controller = {
790 .irq_ack = apic_ack_edge,
791 .irq_set_affinity = apic_set_affinity,
792 .irq_retrigger = apic_retrigger_irq,
797 static void free_moved_vector(struct apic_chip_data *apicd)
799 unsigned int vector = apicd->prev_vector;
800 unsigned int cpu = apicd->prev_cpu;
801 bool managed = apicd->is_managed;
804 * This should never happen. Managed interrupts are not
805 * migrated except on CPU down, which does not involve the
806 * cleanup vector. But try to keep the accounting correct
809 WARN_ON_ONCE(managed);
811 trace_vector_free_moved(apicd->irq, cpu, vector, managed);
812 irq_matrix_free(vector_matrix, cpu, vector, managed);
813 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
814 hlist_del_init(&apicd->clist);
815 apicd->prev_vector = 0;
816 apicd->move_in_progress = 0;
819 asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void)
821 struct hlist_head *clhead = this_cpu_ptr(&cleanup_list);
822 struct apic_chip_data *apicd;
823 struct hlist_node *tmp;
826 /* Prevent vectors vanishing under us */
827 raw_spin_lock(&vector_lock);
829 hlist_for_each_entry_safe(apicd, tmp, clhead, clist) {
830 unsigned int irr, vector = apicd->prev_vector;
833 * Paranoia: Check if the vector that needs to be cleaned
834 * up is registered at the APICs IRR. If so, then this is
835 * not the best time to clean it up. Clean it up in the
836 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
837 * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest
838 * priority external vector, so on return from this
839 * interrupt the device interrupt will happen first.
841 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
842 if (irr & (1U << (vector % 32))) {
843 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
846 free_moved_vector(apicd);
849 raw_spin_unlock(&vector_lock);
853 static void __send_cleanup_vector(struct apic_chip_data *apicd)
857 raw_spin_lock(&vector_lock);
858 apicd->move_in_progress = 0;
859 cpu = apicd->prev_cpu;
860 if (cpu_online(cpu)) {
861 hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu));
862 apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR);
864 apicd->prev_vector = 0;
866 raw_spin_unlock(&vector_lock);
869 void send_cleanup_vector(struct irq_cfg *cfg)
871 struct apic_chip_data *apicd;
873 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
874 if (apicd->move_in_progress)
875 __send_cleanup_vector(apicd);
878 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
880 struct apic_chip_data *apicd;
882 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
883 if (likely(!apicd->move_in_progress))
886 if (vector == apicd->vector && apicd->cpu == smp_processor_id())
887 __send_cleanup_vector(apicd);
890 void irq_complete_move(struct irq_cfg *cfg)
892 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
896 * Called from fixup_irqs() with @desc->lock held and interrupts disabled.
898 void irq_force_complete_move(struct irq_desc *desc)
900 struct apic_chip_data *apicd;
901 struct irq_data *irqd;
905 * The function is called for all descriptors regardless of which
906 * irqdomain they belong to. For example if an IRQ is provided by
907 * an irq_chip as part of a GPIO driver, the chip data for that
908 * descriptor is specific to the irq_chip in question.
910 * Check first that the chip_data is what we expect
911 * (apic_chip_data) before touching it any further.
913 irqd = irq_domain_get_irq_data(x86_vector_domain,
914 irq_desc_get_irq(desc));
918 raw_spin_lock(&vector_lock);
919 apicd = apic_chip_data(irqd);
924 * If prev_vector is empty, no action required.
926 vector = apicd->prev_vector;
931 * This is tricky. If the cleanup of the old vector has not been
932 * done yet, then the following setaffinity call will fail with
933 * -EBUSY. This can leave the interrupt in a stale state.
935 * All CPUs are stuck in stop machine with interrupts disabled so
936 * calling __irq_complete_move() would be completely pointless.
938 * 1) The interrupt is in move_in_progress state. That means that we
939 * have not seen an interrupt since the io_apic was reprogrammed to
942 * 2) The interrupt has fired on the new vector, but the cleanup IPIs
943 * have not been processed yet.
945 if (apicd->move_in_progress) {
947 * In theory there is a race:
949 * set_ioapic(new_vector) <-- Interrupt is raised before update
950 * is effective, i.e. it's raised on
953 * So if the target cpu cannot handle that interrupt before
954 * the old vector is cleaned up, we get a spurious interrupt
955 * and in the worst case the ioapic irq line becomes stale.
957 * But in case of cpu hotplug this should be a non issue
958 * because if the affinity update happens right before all
959 * cpus rendevouz in stop machine, there is no way that the
960 * interrupt can be blocked on the target cpu because all cpus
961 * loops first with interrupts enabled in stop machine, so the
962 * old vector is not yet cleaned up when the interrupt fires.
964 * So the only way to run into this issue is if the delivery
965 * of the interrupt on the apic/system bus would be delayed
966 * beyond the point where the target cpu disables interrupts
967 * in stop machine. I doubt that it can happen, but at least
968 * there is a theroretical chance. Virtualization might be
969 * able to expose this, but AFAICT the IOAPIC emulation is not
970 * as stupid as the real hardware.
972 * Anyway, there is nothing we can do about that at this point
973 * w/o refactoring the whole fixup_irq() business completely.
974 * We print at least the irq number and the old vector number,
975 * so we have the necessary information when a problem in that
978 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n",
981 free_moved_vector(apicd);
983 raw_spin_unlock(&vector_lock);
986 #ifdef CONFIG_HOTPLUG_CPU
988 * Note, this is not accurate accounting, but at least good enough to
989 * prevent that the actual interrupt move will run out of vectors.
991 int lapic_can_unplug_cpu(void)
993 unsigned int rsvd, avl, tomove, cpu = smp_processor_id();
996 raw_spin_lock(&vector_lock);
997 tomove = irq_matrix_allocated(vector_matrix);
998 avl = irq_matrix_available(vector_matrix, true);
1000 pr_warn("CPU %u has %u vectors, %u available. Cannot disable CPU\n",
1005 rsvd = irq_matrix_reserved(vector_matrix);
1007 pr_warn("Reserved vectors %u > available %u. IRQ request may fail\n",
1011 raw_spin_unlock(&vector_lock);
1014 #endif /* HOTPLUG_CPU */
1017 static void __init print_APIC_field(int base)
1023 for (i = 0; i < 8; i++)
1024 pr_cont("%08x", apic_read(base + i*0x10));
1029 static void __init print_local_APIC(void *dummy)
1031 unsigned int i, v, ver, maxlvt;
1034 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
1035 smp_processor_id(), hard_smp_processor_id());
1036 v = apic_read(APIC_ID);
1037 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
1038 v = apic_read(APIC_LVR);
1039 pr_info("... APIC VERSION: %08x\n", v);
1040 ver = GET_APIC_VERSION(v);
1041 maxlvt = lapic_get_maxlvt();
1043 v = apic_read(APIC_TASKPRI);
1044 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1047 if (APIC_INTEGRATED(ver)) {
1048 if (!APIC_XAPIC(ver)) {
1049 v = apic_read(APIC_ARBPRI);
1050 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
1051 v, v & APIC_ARBPRI_MASK);
1053 v = apic_read(APIC_PROCPRI);
1054 pr_debug("... APIC PROCPRI: %08x\n", v);
1058 * Remote read supported only in the 82489DX and local APIC for
1059 * Pentium processors.
1061 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1062 v = apic_read(APIC_RRR);
1063 pr_debug("... APIC RRR: %08x\n", v);
1066 v = apic_read(APIC_LDR);
1067 pr_debug("... APIC LDR: %08x\n", v);
1068 if (!x2apic_enabled()) {
1069 v = apic_read(APIC_DFR);
1070 pr_debug("... APIC DFR: %08x\n", v);
1072 v = apic_read(APIC_SPIV);
1073 pr_debug("... APIC SPIV: %08x\n", v);
1075 pr_debug("... APIC ISR field:\n");
1076 print_APIC_field(APIC_ISR);
1077 pr_debug("... APIC TMR field:\n");
1078 print_APIC_field(APIC_TMR);
1079 pr_debug("... APIC IRR field:\n");
1080 print_APIC_field(APIC_IRR);
1083 if (APIC_INTEGRATED(ver)) {
1084 /* Due to the Pentium erratum 3AP. */
1086 apic_write(APIC_ESR, 0);
1088 v = apic_read(APIC_ESR);
1089 pr_debug("... APIC ESR: %08x\n", v);
1092 icr = apic_icr_read();
1093 pr_debug("... APIC ICR: %08x\n", (u32)icr);
1094 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
1096 v = apic_read(APIC_LVTT);
1097 pr_debug("... APIC LVTT: %08x\n", v);
1101 v = apic_read(APIC_LVTPC);
1102 pr_debug("... APIC LVTPC: %08x\n", v);
1104 v = apic_read(APIC_LVT0);
1105 pr_debug("... APIC LVT0: %08x\n", v);
1106 v = apic_read(APIC_LVT1);
1107 pr_debug("... APIC LVT1: %08x\n", v);
1111 v = apic_read(APIC_LVTERR);
1112 pr_debug("... APIC LVTERR: %08x\n", v);
1115 v = apic_read(APIC_TMICT);
1116 pr_debug("... APIC TMICT: %08x\n", v);
1117 v = apic_read(APIC_TMCCT);
1118 pr_debug("... APIC TMCCT: %08x\n", v);
1119 v = apic_read(APIC_TDCR);
1120 pr_debug("... APIC TDCR: %08x\n", v);
1122 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1123 v = apic_read(APIC_EFEAT);
1124 maxlvt = (v >> 16) & 0xff;
1125 pr_debug("... APIC EFEAT: %08x\n", v);
1126 v = apic_read(APIC_ECTRL);
1127 pr_debug("... APIC ECTRL: %08x\n", v);
1128 for (i = 0; i < maxlvt; i++) {
1129 v = apic_read(APIC_EILVTn(i));
1130 pr_debug("... APIC EILVT%d: %08x\n", i, v);
1136 static void __init print_local_APICs(int maxcpu)
1144 for_each_online_cpu(cpu) {
1147 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1152 static void __init print_PIC(void)
1155 unsigned long flags;
1157 if (!nr_legacy_irqs())
1160 pr_debug("\nprinting PIC contents\n");
1162 raw_spin_lock_irqsave(&i8259A_lock, flags);
1164 v = inb(0xa1) << 8 | inb(0x21);
1165 pr_debug("... PIC IMR: %04x\n", v);
1167 v = inb(0xa0) << 8 | inb(0x20);
1168 pr_debug("... PIC IRR: %04x\n", v);
1172 v = inb(0xa0) << 8 | inb(0x20);
1176 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1178 pr_debug("... PIC ISR: %04x\n", v);
1180 v = inb(0x4d1) << 8 | inb(0x4d0);
1181 pr_debug("... PIC ELCR: %04x\n", v);
1184 static int show_lapic __initdata = 1;
1185 static __init int setup_show_lapic(char *arg)
1189 if (strcmp(arg, "all") == 0) {
1190 show_lapic = CONFIG_NR_CPUS;
1192 get_option(&arg, &num);
1199 __setup("show_lapic=", setup_show_lapic);
1201 static int __init print_ICs(void)
1203 if (apic_verbosity == APIC_QUIET)
1208 /* don't print out if apic is not there */
1209 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1212 print_local_APICs(show_lapic);
1218 late_initcall(print_ICs);