1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
7 * Many thanks to Stig Venaas for trying out countless experimental
8 * patches and reporting/debugging problems patiently!
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13 * further tested and cleaned up by Zach Brown <zab@redhat.com>
14 * and Ingo Molnar <mingo@redhat.com>
17 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
18 * thanks to Eric Gilmore
20 * for testing these extensively
21 * Paul Diefenbaugh : Added full ACPI support
23 * Historical information which is worth to be preserved:
27 * We used to have a workaround for a bug in SiS chips which
28 * required to rewrite the index register for a read-modify-write
29 * operation as the chip lost the index information which was
30 * setup for the read already. We cache the data now, so that
31 * workaround has been removed.
35 #include <linux/interrupt.h>
36 #include <linux/irq.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/pci.h>
41 #include <linux/mc146818rtc.h>
42 #include <linux/compiler.h>
43 #include <linux/acpi.h>
44 #include <linux/export.h>
45 #include <linux/syscore_ops.h>
46 #include <linux/freezer.h>
47 #include <linux/kthread.h>
48 #include <linux/jiffies.h> /* time_after() */
49 #include <linux/slab.h>
50 #include <linux/memblock.h>
52 #include <asm/irqdomain.h>
57 #include <asm/proto.h>
60 #include <asm/timer.h>
62 #include <asm/i8259.h>
63 #include <asm/setup.h>
64 #include <asm/irq_remapping.h>
65 #include <asm/hw_irq.h>
69 #define for_each_ioapic(idx) \
70 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
71 #define for_each_ioapic_reverse(idx) \
72 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
73 #define for_each_pin(idx, pin) \
74 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
75 #define for_each_ioapic_pin(idx, pin) \
76 for_each_ioapic((idx)) \
77 for_each_pin((idx), (pin))
78 #define for_each_irq_pin(entry, head) \
79 list_for_each_entry(entry, &head, list)
81 static DEFINE_RAW_SPINLOCK(ioapic_lock);
82 static DEFINE_MUTEX(ioapic_mutex);
83 static unsigned int ioapic_dynirq_base;
84 static int ioapic_initialized;
87 struct list_head list;
92 struct list_head irq_2_pin;
93 struct IO_APIC_route_entry entry;
100 struct mp_ioapic_gsi {
105 static struct ioapic {
107 * # of IRQ routing registers
111 * Saved state during suspend/resume, or while enabling intr-remap.
113 struct IO_APIC_route_entry *saved_registers;
114 /* I/O APIC config */
115 struct mpc_ioapic mp_config;
116 /* IO APIC gsi routing info */
117 struct mp_ioapic_gsi gsi_config;
118 struct ioapic_domain_cfg irqdomain_cfg;
119 struct irq_domain *irqdomain;
120 struct resource *iomem_res;
121 } ioapics[MAX_IO_APICS];
123 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
125 int mpc_ioapic_id(int ioapic_idx)
127 return ioapics[ioapic_idx].mp_config.apicid;
130 unsigned int mpc_ioapic_addr(int ioapic_idx)
132 return ioapics[ioapic_idx].mp_config.apicaddr;
135 static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
137 return &ioapics[ioapic_idx].gsi_config;
140 static inline int mp_ioapic_pin_count(int ioapic)
142 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
144 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
147 static inline u32 mp_pin_to_gsi(int ioapic, int pin)
149 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
152 static inline bool mp_is_legacy_irq(int irq)
154 return irq >= 0 && irq < nr_legacy_irqs();
157 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
159 return ioapics[ioapic].irqdomain;
164 /* The one past the highest gsi number used */
167 /* MP IRQ source entries */
168 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
170 /* # of MP IRQ source entries */
174 int mp_bus_id_to_type[MAX_MP_BUSSES];
177 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
179 int skip_ioapic_setup;
182 * disable_ioapic_support() - disables ioapic support at runtime
184 void disable_ioapic_support(void)
188 noioapicreroute = -1;
190 skip_ioapic_setup = 1;
193 static int __init parse_noapic(char *str)
195 /* disable IO-APIC */
196 disable_ioapic_support();
199 early_param("noapic", parse_noapic);
201 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
202 void mp_save_irq(struct mpc_intsrc *m)
206 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
207 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
208 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
209 m->srcbusirq, m->dstapic, m->dstirq);
211 for (i = 0; i < mp_irq_entries; i++) {
212 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
216 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
217 if (++mp_irq_entries == MAX_IRQ_SOURCES)
218 panic("Max # of irq sources exceeded!!\n");
221 static void alloc_ioapic_saved_registers(int idx)
225 if (ioapics[idx].saved_registers)
228 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
229 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
230 if (!ioapics[idx].saved_registers)
231 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
234 static void free_ioapic_saved_registers(int idx)
236 kfree(ioapics[idx].saved_registers);
237 ioapics[idx].saved_registers = NULL;
240 int __init arch_early_ioapic_init(void)
244 if (!nr_legacy_irqs())
248 alloc_ioapic_saved_registers(i);
255 unsigned int unused[3];
257 unsigned int unused2[11];
261 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
263 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
264 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
267 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
269 struct io_apic __iomem *io_apic = io_apic_base(apic);
270 writel(vector, &io_apic->eoi);
273 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
275 struct io_apic __iomem *io_apic = io_apic_base(apic);
276 writel(reg, &io_apic->index);
277 return readl(&io_apic->data);
280 static void io_apic_write(unsigned int apic, unsigned int reg,
283 struct io_apic __iomem *io_apic = io_apic_base(apic);
285 writel(reg, &io_apic->index);
286 writel(value, &io_apic->data);
290 struct { u32 w1, w2; };
291 struct IO_APIC_route_entry entry;
294 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
296 union entry_union eu;
298 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
299 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
304 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
306 union entry_union eu;
309 raw_spin_lock_irqsave(&ioapic_lock, flags);
310 eu.entry = __ioapic_read_entry(apic, pin);
311 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
317 * When we write a new IO APIC routing entry, we need to write the high
318 * word first! If the mask bit in the low word is clear, we will enable
319 * the interrupt, and we need to make sure the entry is fully populated
320 * before that happens.
322 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
324 union entry_union eu = {{0, 0}};
327 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
328 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
331 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
335 raw_spin_lock_irqsave(&ioapic_lock, flags);
336 __ioapic_write_entry(apic, pin, e);
337 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
341 * When we mask an IO APIC routing entry, we need to write the low
342 * word first, in order to set the mask bit before we change the
345 static void ioapic_mask_entry(int apic, int pin)
348 union entry_union eu = { .entry.mask = IOAPIC_MASKED };
350 raw_spin_lock_irqsave(&ioapic_lock, flags);
351 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
352 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
353 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
357 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
358 * shared ISA-space IRQs, so we have to support them. We are super
359 * fast in the common case, and fast for shared ISA-space IRQs.
361 static int __add_pin_to_irq_node(struct mp_chip_data *data,
362 int node, int apic, int pin)
364 struct irq_pin_list *entry;
366 /* don't allow duplicates */
367 for_each_irq_pin(entry, data->irq_2_pin)
368 if (entry->apic == apic && entry->pin == pin)
371 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
373 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
379 list_add_tail(&entry->list, &data->irq_2_pin);
384 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
386 struct irq_pin_list *tmp, *entry;
388 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
389 if (entry->apic == apic && entry->pin == pin) {
390 list_del(&entry->list);
396 static void add_pin_to_irq_node(struct mp_chip_data *data,
397 int node, int apic, int pin)
399 if (__add_pin_to_irq_node(data, node, apic, pin))
400 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
404 * Reroute an IRQ to a different pin.
406 static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
407 int oldapic, int oldpin,
408 int newapic, int newpin)
410 struct irq_pin_list *entry;
412 for_each_irq_pin(entry, data->irq_2_pin) {
413 if (entry->apic == oldapic && entry->pin == oldpin) {
414 entry->apic = newapic;
416 /* every one is different, right? */
421 /* old apic/pin didn't exist, so just add new ones */
422 add_pin_to_irq_node(data, node, newapic, newpin);
425 static void io_apic_modify_irq(struct mp_chip_data *data,
426 int mask_and, int mask_or,
427 void (*final)(struct irq_pin_list *entry))
429 union entry_union eu;
430 struct irq_pin_list *entry;
432 eu.entry = data->entry;
435 data->entry = eu.entry;
437 for_each_irq_pin(entry, data->irq_2_pin) {
438 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1);
444 static void io_apic_sync(struct irq_pin_list *entry)
447 * Synchronize the IO-APIC and the CPU by doing
448 * a dummy read from the IO-APIC
450 struct io_apic __iomem *io_apic;
452 io_apic = io_apic_base(entry->apic);
453 readl(&io_apic->data);
456 static void mask_ioapic_irq(struct irq_data *irq_data)
458 struct mp_chip_data *data = irq_data->chip_data;
461 raw_spin_lock_irqsave(&ioapic_lock, flags);
462 io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
463 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
466 static void __unmask_ioapic(struct mp_chip_data *data)
468 io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
471 static void unmask_ioapic_irq(struct irq_data *irq_data)
473 struct mp_chip_data *data = irq_data->chip_data;
476 raw_spin_lock_irqsave(&ioapic_lock, flags);
477 __unmask_ioapic(data);
478 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
482 * IO-APIC versions below 0x20 don't support EOI register.
483 * For the record, here is the information about various versions:
485 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
486 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
489 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
490 * version as 0x2. This is an error with documentation and these ICH chips
491 * use io-apic's of version 0x20.
493 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
494 * Otherwise, we simulate the EOI message manually by changing the trigger
495 * mode to edge and then back to level, with RTE being masked during this.
497 static void __eoi_ioapic_pin(int apic, int pin, int vector)
499 if (mpc_ioapic_ver(apic) >= 0x20) {
500 io_apic_eoi(apic, vector);
502 struct IO_APIC_route_entry entry, entry1;
504 entry = entry1 = __ioapic_read_entry(apic, pin);
507 * Mask the entry and change the trigger mode to edge.
509 entry1.mask = IOAPIC_MASKED;
510 entry1.trigger = IOAPIC_EDGE;
512 __ioapic_write_entry(apic, pin, entry1);
515 * Restore the previous level triggered entry.
517 __ioapic_write_entry(apic, pin, entry);
521 static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
524 struct irq_pin_list *entry;
526 raw_spin_lock_irqsave(&ioapic_lock, flags);
527 for_each_irq_pin(entry, data->irq_2_pin)
528 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
529 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
532 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
534 struct IO_APIC_route_entry entry;
536 /* Check delivery_mode to be sure we're not clearing an SMI pin */
537 entry = ioapic_read_entry(apic, pin);
538 if (entry.delivery_mode == dest_SMI)
542 * Make sure the entry is masked and re-read the contents to check
543 * if it is a level triggered pin and if the remote-IRR is set.
545 if (entry.mask == IOAPIC_UNMASKED) {
546 entry.mask = IOAPIC_MASKED;
547 ioapic_write_entry(apic, pin, entry);
548 entry = ioapic_read_entry(apic, pin);
555 * Make sure the trigger mode is set to level. Explicit EOI
556 * doesn't clear the remote-IRR if the trigger mode is not
559 if (entry.trigger == IOAPIC_EDGE) {
560 entry.trigger = IOAPIC_LEVEL;
561 ioapic_write_entry(apic, pin, entry);
563 raw_spin_lock_irqsave(&ioapic_lock, flags);
564 __eoi_ioapic_pin(apic, pin, entry.vector);
565 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
569 * Clear the rest of the bits in the IO-APIC RTE except for the mask
572 ioapic_mask_entry(apic, pin);
573 entry = ioapic_read_entry(apic, pin);
575 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
576 mpc_ioapic_id(apic), pin);
579 void clear_IO_APIC (void)
583 for_each_ioapic_pin(apic, pin)
584 clear_IO_APIC_pin(apic, pin);
589 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
590 * specific CPU-side IRQs.
594 static int pirq_entries[MAX_PIRQS] = {
595 [0 ... MAX_PIRQS - 1] = -1
598 static int __init ioapic_pirq_setup(char *str)
601 int ints[MAX_PIRQS+1];
603 get_options(str, ARRAY_SIZE(ints), ints);
605 apic_printk(APIC_VERBOSE, KERN_INFO
606 "PIRQ redirection, working around broken MP-BIOS.\n");
608 if (ints[0] < MAX_PIRQS)
611 for (i = 0; i < max; i++) {
612 apic_printk(APIC_VERBOSE, KERN_DEBUG
613 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
615 * PIRQs are mapped upside down, usually.
617 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
622 __setup("pirq=", ioapic_pirq_setup);
623 #endif /* CONFIG_X86_32 */
626 * Saves all the IO-APIC RTE's
628 int save_ioapic_entries(void)
633 for_each_ioapic(apic) {
634 if (!ioapics[apic].saved_registers) {
639 for_each_pin(apic, pin)
640 ioapics[apic].saved_registers[pin] =
641 ioapic_read_entry(apic, pin);
648 * Mask all IO APIC entries.
650 void mask_ioapic_entries(void)
654 for_each_ioapic(apic) {
655 if (!ioapics[apic].saved_registers)
658 for_each_pin(apic, pin) {
659 struct IO_APIC_route_entry entry;
661 entry = ioapics[apic].saved_registers[pin];
662 if (entry.mask == IOAPIC_UNMASKED) {
663 entry.mask = IOAPIC_MASKED;
664 ioapic_write_entry(apic, pin, entry);
671 * Restore IO APIC entries which was saved in the ioapic structure.
673 int restore_ioapic_entries(void)
677 for_each_ioapic(apic) {
678 if (!ioapics[apic].saved_registers)
681 for_each_pin(apic, pin)
682 ioapic_write_entry(apic, pin,
683 ioapics[apic].saved_registers[pin]);
689 * Find the IRQ entry number of a certain pin.
691 static int find_irq_entry(int ioapic_idx, int pin, int type)
695 for (i = 0; i < mp_irq_entries; i++)
696 if (mp_irqs[i].irqtype == type &&
697 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
698 mp_irqs[i].dstapic == MP_APIC_ALL) &&
699 mp_irqs[i].dstirq == pin)
706 * Find the pin to which IRQ[irq] (ISA) is connected
708 static int __init find_isa_irq_pin(int irq, int type)
712 for (i = 0; i < mp_irq_entries; i++) {
713 int lbus = mp_irqs[i].srcbus;
715 if (test_bit(lbus, mp_bus_not_pci) &&
716 (mp_irqs[i].irqtype == type) &&
717 (mp_irqs[i].srcbusirq == irq))
719 return mp_irqs[i].dstirq;
724 static int __init find_isa_irq_apic(int irq, int type)
728 for (i = 0; i < mp_irq_entries; i++) {
729 int lbus = mp_irqs[i].srcbus;
731 if (test_bit(lbus, mp_bus_not_pci) &&
732 (mp_irqs[i].irqtype == type) &&
733 (mp_irqs[i].srcbusirq == irq))
737 if (i < mp_irq_entries) {
740 for_each_ioapic(ioapic_idx)
741 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
750 * EISA Edge/Level control register, ELCR
752 static int EISA_ELCR(unsigned int irq)
754 if (irq < nr_legacy_irqs()) {
755 unsigned int port = 0x4d0 + (irq >> 3);
756 return (inb(port) >> (irq & 7)) & 1;
758 apic_printk(APIC_VERBOSE, KERN_INFO
759 "Broken MPtable reports ISA irq %d\n", irq);
765 /* ISA interrupts are always active high edge triggered,
766 * when listed as conforming in the MP table. */
768 #define default_ISA_trigger(idx) (IOAPIC_EDGE)
769 #define default_ISA_polarity(idx) (IOAPIC_POL_HIGH)
771 /* EISA interrupts are always polarity zero and can be edge or level
772 * trigger depending on the ELCR value. If an interrupt is listed as
773 * EISA conforming in the MP table, that means its trigger type must
774 * be read in from the ELCR */
776 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
777 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
779 /* PCI interrupts are always active low level triggered,
780 * when listed as conforming in the MP table. */
782 #define default_PCI_trigger(idx) (IOAPIC_LEVEL)
783 #define default_PCI_polarity(idx) (IOAPIC_POL_LOW)
785 static int irq_polarity(int idx)
787 int bus = mp_irqs[idx].srcbus;
790 * Determine IRQ line polarity (high active or low active):
792 switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
793 case MP_IRQPOL_DEFAULT:
794 /* conforms to spec, ie. bus-type dependent polarity */
795 if (test_bit(bus, mp_bus_not_pci))
796 return default_ISA_polarity(idx);
798 return default_PCI_polarity(idx);
799 case MP_IRQPOL_ACTIVE_HIGH:
800 return IOAPIC_POL_HIGH;
801 case MP_IRQPOL_RESERVED:
802 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
804 case MP_IRQPOL_ACTIVE_LOW:
805 default: /* Pointless default required due to do gcc stupidity */
806 return IOAPIC_POL_LOW;
811 static int eisa_irq_trigger(int idx, int bus, int trigger)
813 switch (mp_bus_id_to_type[bus]) {
818 return default_EISA_trigger(idx);
820 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
824 static inline int eisa_irq_trigger(int idx, int bus, int trigger)
830 static int irq_trigger(int idx)
832 int bus = mp_irqs[idx].srcbus;
836 * Determine IRQ trigger mode (edge or level sensitive):
838 switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
839 case MP_IRQTRIG_DEFAULT:
840 /* conforms to spec, ie. bus-type dependent trigger mode */
841 if (test_bit(bus, mp_bus_not_pci))
842 trigger = default_ISA_trigger(idx);
844 trigger = default_PCI_trigger(idx);
845 /* Take EISA into account */
846 return eisa_irq_trigger(idx, bus, trigger);
847 case MP_IRQTRIG_EDGE:
849 case MP_IRQTRIG_RESERVED:
850 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
852 case MP_IRQTRIG_LEVEL:
853 default: /* Pointless default required due to do gcc stupidity */
858 void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
859 int trigger, int polarity)
861 init_irq_alloc_info(info, NULL);
862 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
863 info->ioapic.node = node;
864 info->ioapic.trigger = trigger;
865 info->ioapic.polarity = polarity;
866 info->ioapic.valid = 1;
870 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
873 static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
874 struct irq_alloc_info *src,
875 u32 gsi, int ioapic_idx, int pin)
877 int trigger, polarity;
879 copy_irq_alloc_info(dst, src);
880 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
881 dst->devid = mpc_ioapic_id(ioapic_idx);
882 dst->ioapic.pin = pin;
883 dst->ioapic.valid = 1;
884 if (src && src->ioapic.valid) {
885 dst->ioapic.node = src->ioapic.node;
886 dst->ioapic.trigger = src->ioapic.trigger;
887 dst->ioapic.polarity = src->ioapic.polarity;
889 dst->ioapic.node = NUMA_NO_NODE;
890 if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
891 dst->ioapic.trigger = trigger;
892 dst->ioapic.polarity = polarity;
895 * PCI interrupts are always active low level
898 dst->ioapic.trigger = IOAPIC_LEVEL;
899 dst->ioapic.polarity = IOAPIC_POL_LOW;
904 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
906 return (info && info->ioapic.valid) ? info->ioapic.node : NUMA_NO_NODE;
909 static void mp_register_handler(unsigned int irq, unsigned long trigger)
911 irq_flow_handler_t hdl;
915 irq_set_status_flags(irq, IRQ_LEVEL);
918 irq_clear_status_flags(irq, IRQ_LEVEL);
922 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
923 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
926 static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
928 struct mp_chip_data *data = irq_get_chip_data(irq);
931 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
932 * and polarity attirbutes. So allow the first user to reprogram the
933 * pin with real trigger and polarity attributes.
935 if (irq < nr_legacy_irqs() && data->count == 1) {
936 if (info->ioapic.trigger != data->trigger)
937 mp_register_handler(irq, info->ioapic.trigger);
938 data->entry.trigger = data->trigger = info->ioapic.trigger;
939 data->entry.polarity = data->polarity = info->ioapic.polarity;
942 return data->trigger == info->ioapic.trigger &&
943 data->polarity == info->ioapic.polarity;
946 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
947 struct irq_alloc_info *info)
951 int type = ioapics[ioapic].irqdomain_cfg.type;
954 case IOAPIC_DOMAIN_LEGACY:
956 * Dynamically allocate IRQ number for non-ISA IRQs in the first
957 * 16 GSIs on some weird platforms.
959 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
961 legacy = mp_is_legacy_irq(irq);
963 case IOAPIC_DOMAIN_STRICT:
966 case IOAPIC_DOMAIN_DYNAMIC:
969 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
973 return __irq_domain_alloc_irqs(domain, irq, 1,
974 ioapic_alloc_attr_node(info),
979 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
980 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
981 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
982 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
983 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
984 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
985 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
986 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
988 static int alloc_isa_irq_from_domain(struct irq_domain *domain,
989 int irq, int ioapic, int pin,
990 struct irq_alloc_info *info)
992 struct mp_chip_data *data;
993 struct irq_data *irq_data = irq_get_irq_data(irq);
994 int node = ioapic_alloc_attr_node(info);
997 * Legacy ISA IRQ has already been allocated, just add pin to
998 * the pin list assoicated with this IRQ and program the IOAPIC
999 * entry. The IOAPIC entry
1001 if (irq_data && irq_data->parent_data) {
1002 if (!mp_check_pin_attr(irq, info))
1004 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1008 info->flags |= X86_IRQ_ALLOC_LEGACY;
1009 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1012 irq_data = irq_domain_get_irq_data(domain, irq);
1013 data = irq_data->chip_data;
1014 data->isa_irq = true;
1021 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1022 unsigned int flags, struct irq_alloc_info *info)
1025 bool legacy = false;
1026 struct irq_alloc_info tmp;
1027 struct mp_chip_data *data;
1028 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1033 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1034 irq = mp_irqs[idx].srcbusirq;
1035 legacy = mp_is_legacy_irq(irq);
1038 mutex_lock(&ioapic_mutex);
1039 if (!(flags & IOAPIC_MAP_ALLOC)) {
1041 irq = irq_find_mapping(domain, pin);
1046 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1048 irq = alloc_isa_irq_from_domain(domain, irq,
1050 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1051 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1052 else if (!mp_check_pin_attr(irq, &tmp))
1055 data = irq_get_chip_data(irq);
1059 mutex_unlock(&ioapic_mutex);
1064 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1066 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1069 * Debugging check, we are in big trouble if this message pops up!
1071 if (mp_irqs[idx].dstirq != pin)
1072 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1074 #ifdef CONFIG_X86_32
1076 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1078 if ((pin >= 16) && (pin <= 23)) {
1079 if (pirq_entries[pin-16] != -1) {
1080 if (!pirq_entries[pin-16]) {
1081 apic_printk(APIC_VERBOSE, KERN_DEBUG
1082 "disabling PIRQ%d\n", pin-16);
1084 int irq = pirq_entries[pin-16];
1085 apic_printk(APIC_VERBOSE, KERN_DEBUG
1086 "using PIRQ%d -> IRQ %d\n",
1094 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1097 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1099 int ioapic, pin, idx;
1101 ioapic = mp_find_ioapic(gsi);
1105 pin = mp_find_ioapic_pin(ioapic, gsi);
1106 idx = find_irq_entry(ioapic, pin, mp_INT);
1107 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1110 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1113 void mp_unmap_irq(int irq)
1115 struct irq_data *irq_data = irq_get_irq_data(irq);
1116 struct mp_chip_data *data;
1118 if (!irq_data || !irq_data->domain)
1121 data = irq_data->chip_data;
1122 if (!data || data->isa_irq)
1125 mutex_lock(&ioapic_mutex);
1126 if (--data->count == 0)
1127 irq_domain_free_irqs(irq, 1);
1128 mutex_unlock(&ioapic_mutex);
1132 * Find a specific PCI IRQ entry.
1133 * Not an __init, possibly needed by modules
1135 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1137 int irq, i, best_ioapic = -1, best_idx = -1;
1139 apic_printk(APIC_DEBUG,
1140 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1142 if (test_bit(bus, mp_bus_not_pci)) {
1143 apic_printk(APIC_VERBOSE,
1144 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1148 for (i = 0; i < mp_irq_entries; i++) {
1149 int lbus = mp_irqs[i].srcbus;
1150 int ioapic_idx, found = 0;
1152 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1153 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1156 for_each_ioapic(ioapic_idx)
1157 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1158 mp_irqs[i].dstapic == MP_APIC_ALL) {
1166 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1167 if (irq > 0 && !IO_APIC_IRQ(irq))
1170 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1172 best_ioapic = ioapic_idx;
1177 * Use the first all-but-pin matching entry as a
1178 * best-guess fuzzy result for broken mptables.
1182 best_ioapic = ioapic_idx;
1189 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1192 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1194 static struct irq_chip ioapic_chip, ioapic_ir_chip;
1196 static void __init setup_IO_APIC_irqs(void)
1198 unsigned int ioapic, pin;
1201 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1203 for_each_ioapic_pin(ioapic, pin) {
1204 idx = find_irq_entry(ioapic, pin, mp_INT);
1206 apic_printk(APIC_VERBOSE,
1207 KERN_DEBUG " apic %d pin %d not connected\n",
1208 mpc_ioapic_id(ioapic), pin);
1210 pin_2_irq(idx, ioapic, pin,
1211 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1215 void ioapic_zap_locks(void)
1217 raw_spin_lock_init(&ioapic_lock);
1220 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1224 struct IO_APIC_route_entry entry;
1225 struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
1227 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1228 for (i = 0; i <= nr_entries; i++) {
1229 entry = ioapic_read_entry(apic, i);
1230 snprintf(buf, sizeof(buf),
1231 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1233 entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ",
1234 entry.trigger == IOAPIC_LEVEL ? "level" : "edge ",
1235 entry.polarity == IOAPIC_POL_LOW ? "low " : "high",
1236 entry.vector, entry.irr, entry.delivery_status);
1237 if (ir_entry->format)
1238 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1239 buf, (ir_entry->index2 << 15) | ir_entry->index,
1242 printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
1244 entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ?
1245 "logical " : "physical",
1246 entry.dest, entry.delivery_mode);
1250 static void __init print_IO_APIC(int ioapic_idx)
1252 union IO_APIC_reg_00 reg_00;
1253 union IO_APIC_reg_01 reg_01;
1254 union IO_APIC_reg_02 reg_02;
1255 union IO_APIC_reg_03 reg_03;
1256 unsigned long flags;
1258 raw_spin_lock_irqsave(&ioapic_lock, flags);
1259 reg_00.raw = io_apic_read(ioapic_idx, 0);
1260 reg_01.raw = io_apic_read(ioapic_idx, 1);
1261 if (reg_01.bits.version >= 0x10)
1262 reg_02.raw = io_apic_read(ioapic_idx, 2);
1263 if (reg_01.bits.version >= 0x20)
1264 reg_03.raw = io_apic_read(ioapic_idx, 3);
1265 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1267 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1268 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1269 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1270 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1271 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1273 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1274 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1275 reg_01.bits.entries);
1277 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1278 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1279 reg_01.bits.version);
1282 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1283 * but the value of reg_02 is read as the previous read register
1284 * value, so ignore it if reg_02 == reg_01.
1286 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1287 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1288 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1292 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1293 * or reg_03, but the value of reg_0[23] is read as the previous read
1294 * register value, so ignore it if reg_03 == reg_0[12].
1296 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1297 reg_03.raw != reg_01.raw) {
1298 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1299 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1302 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1303 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1306 void __init print_IO_APICs(void)
1311 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1312 for_each_ioapic(ioapic_idx)
1313 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1314 mpc_ioapic_id(ioapic_idx),
1315 ioapics[ioapic_idx].nr_registers);
1318 * We are a bit conservative about what we expect. We have to
1319 * know about every hardware change ASAP.
1321 printk(KERN_INFO "testing the IO APIC.......................\n");
1323 for_each_ioapic(ioapic_idx)
1324 print_IO_APIC(ioapic_idx);
1326 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1327 for_each_active_irq(irq) {
1328 struct irq_pin_list *entry;
1329 struct irq_chip *chip;
1330 struct mp_chip_data *data;
1332 chip = irq_get_chip(irq);
1333 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1335 data = irq_get_chip_data(irq);
1338 if (list_empty(&data->irq_2_pin))
1341 printk(KERN_DEBUG "IRQ%d ", irq);
1342 for_each_irq_pin(entry, data->irq_2_pin)
1343 pr_cont("-> %d:%d", entry->apic, entry->pin);
1347 printk(KERN_INFO ".................................... done.\n");
1350 /* Where if anywhere is the i8259 connect in external int mode */
1351 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1353 void __init enable_IO_APIC(void)
1355 int i8259_apic, i8259_pin;
1358 if (skip_ioapic_setup)
1361 if (!nr_legacy_irqs() || !nr_ioapics)
1364 for_each_ioapic_pin(apic, pin) {
1365 /* See if any of the pins is in ExtINT mode */
1366 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1368 /* If the interrupt line is enabled and in ExtInt mode
1369 * I have found the pin where the i8259 is connected.
1371 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1372 ioapic_i8259.apic = apic;
1373 ioapic_i8259.pin = pin;
1378 /* Look to see what if the MP table has reported the ExtINT */
1379 /* If we could not find the appropriate pin by looking at the ioapic
1380 * the i8259 probably is not connected the ioapic but give the
1381 * mptable a chance anyway.
1383 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1384 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1385 /* Trust the MP table if nothing is setup in the hardware */
1386 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1387 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1388 ioapic_i8259.pin = i8259_pin;
1389 ioapic_i8259.apic = i8259_apic;
1391 /* Complain if the MP table and the hardware disagree */
1392 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1393 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1395 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1399 * Do not trust the IO-APIC being empty at bootup
1404 void native_restore_boot_irq_mode(void)
1407 * If the i8259 is routed through an IOAPIC
1408 * Put that IOAPIC in virtual wire mode
1409 * so legacy interrupts can be delivered.
1411 if (ioapic_i8259.pin != -1) {
1412 struct IO_APIC_route_entry entry;
1414 memset(&entry, 0, sizeof(entry));
1415 entry.mask = IOAPIC_UNMASKED;
1416 entry.trigger = IOAPIC_EDGE;
1417 entry.polarity = IOAPIC_POL_HIGH;
1418 entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
1419 entry.delivery_mode = dest_ExtINT;
1420 entry.dest = read_apic_id();
1423 * Add it to the IO-APIC irq-routing table:
1425 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1428 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1429 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1432 void restore_boot_irq_mode(void)
1434 if (!nr_legacy_irqs())
1437 x86_apic_ops.restore();
1440 #ifdef CONFIG_X86_32
1442 * function to set the IO-APIC physical IDs based on the
1443 * values stored in the MPC table.
1445 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1447 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1449 union IO_APIC_reg_00 reg_00;
1450 physid_mask_t phys_id_present_map;
1453 unsigned char old_id;
1454 unsigned long flags;
1457 * This is broken; anything with a real cpu count has to
1458 * circumvent this idiocy regardless.
1460 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1463 * Set the IOAPIC ID to the value stored in the MPC table.
1465 for_each_ioapic(ioapic_idx) {
1466 /* Read the register 0 value */
1467 raw_spin_lock_irqsave(&ioapic_lock, flags);
1468 reg_00.raw = io_apic_read(ioapic_idx, 0);
1469 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1471 old_id = mpc_ioapic_id(ioapic_idx);
1473 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1474 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1475 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1476 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1478 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1482 * Sanity check, is the ID really free? Every APIC in a
1483 * system must have a unique ID or we get lots of nice
1484 * 'stuck on smp_invalidate_needed IPI wait' messages.
1486 if (apic->check_apicid_used(&phys_id_present_map,
1487 mpc_ioapic_id(ioapic_idx))) {
1488 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1489 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1490 for (i = 0; i < get_physical_broadcast(); i++)
1491 if (!physid_isset(i, phys_id_present_map))
1493 if (i >= get_physical_broadcast())
1494 panic("Max APIC ID exceeded!\n");
1495 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1497 physid_set(i, phys_id_present_map);
1498 ioapics[ioapic_idx].mp_config.apicid = i;
1501 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1503 apic_printk(APIC_VERBOSE, "Setting %d in the "
1504 "phys_id_present_map\n",
1505 mpc_ioapic_id(ioapic_idx));
1506 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1510 * We need to adjust the IRQ routing table
1511 * if the ID changed.
1513 if (old_id != mpc_ioapic_id(ioapic_idx))
1514 for (i = 0; i < mp_irq_entries; i++)
1515 if (mp_irqs[i].dstapic == old_id)
1517 = mpc_ioapic_id(ioapic_idx);
1520 * Update the ID register according to the right value
1521 * from the MPC table if they are different.
1523 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1526 apic_printk(APIC_VERBOSE, KERN_INFO
1527 "...changing IO-APIC physical APIC ID to %d ...",
1528 mpc_ioapic_id(ioapic_idx));
1530 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1531 raw_spin_lock_irqsave(&ioapic_lock, flags);
1532 io_apic_write(ioapic_idx, 0, reg_00.raw);
1533 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1538 raw_spin_lock_irqsave(&ioapic_lock, flags);
1539 reg_00.raw = io_apic_read(ioapic_idx, 0);
1540 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1541 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1542 pr_cont("could not set ID!\n");
1544 apic_printk(APIC_VERBOSE, " ok.\n");
1548 void __init setup_ioapic_ids_from_mpc(void)
1554 * Don't check I/O APIC IDs for xAPIC systems. They have
1555 * no meaning without the serial APIC bus.
1557 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1558 || APIC_XAPIC(boot_cpu_apic_version))
1560 setup_ioapic_ids_from_mpc_nocheck();
1564 int no_timer_check __initdata;
1566 static int __init notimercheck(char *s)
1571 __setup("no_timer_check", notimercheck);
1573 static void __init delay_with_tsc(void)
1575 unsigned long long start, now;
1576 unsigned long end = jiffies + 4;
1581 * We don't know the TSC frequency yet, but waiting for
1582 * 40000000000/HZ TSC cycles is safe:
1583 * 4 GHz == 10 jiffies
1584 * 1 GHz == 40 jiffies
1589 } while ((now - start) < 40000000000ULL / HZ &&
1590 time_before_eq(jiffies, end));
1593 static void __init delay_without_tsc(void)
1595 unsigned long end = jiffies + 4;
1599 * We don't know any frequency yet, but waiting for
1600 * 40940000000/HZ cycles is safe:
1601 * 4 GHz == 10 jiffies
1602 * 1 GHz == 40 jiffies
1603 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1606 __delay(((1U << band++) * 10000000UL) / HZ);
1607 } while (band < 12 && time_before_eq(jiffies, end));
1611 * There is a nasty bug in some older SMP boards, their mptable lies
1612 * about the timer IRQ. We do the following to work around the situation:
1614 * - timer IRQ defaults to IO-APIC IRQ
1615 * - if this function detects that timer IRQs are defunct, then we fall
1616 * back to ISA timer IRQs
1618 static int __init timer_irq_works(void)
1620 unsigned long t1 = jiffies;
1621 unsigned long flags;
1626 local_save_flags(flags);
1629 if (boot_cpu_has(X86_FEATURE_TSC))
1632 delay_without_tsc();
1634 local_irq_restore(flags);
1637 * Expect a few ticks at least, to be sure some possible
1638 * glue logic does not lock up after one or two first
1639 * ticks in a non-ExtINT mode. Also the local APIC
1640 * might have cached one ExtINT interrupt. Finally, at
1641 * least one tick may be lost due to delays.
1645 if (time_after(jiffies, t1 + 4))
1651 * In the SMP+IOAPIC case it might happen that there are an unspecified
1652 * number of pending IRQ events unhandled. These cases are very rare,
1653 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1654 * better to do it this way as thus we do not have to be aware of
1655 * 'pending' interrupts in the IRQ path, except at this point.
1658 * Edge triggered needs to resend any interrupt
1659 * that was delayed but this is now handled in the device
1664 * Starting up a edge-triggered IO-APIC interrupt is
1665 * nasty - we need to make sure that we get the edge.
1666 * If it is already asserted for some reason, we need
1667 * return 1 to indicate that is was pending.
1669 * This is not complete - we should be able to fake
1670 * an edge even if it isn't on the 8259A...
1672 static unsigned int startup_ioapic_irq(struct irq_data *data)
1674 int was_pending = 0, irq = data->irq;
1675 unsigned long flags;
1677 raw_spin_lock_irqsave(&ioapic_lock, flags);
1678 if (irq < nr_legacy_irqs()) {
1679 legacy_pic->mask(irq);
1680 if (legacy_pic->irq_pending(irq))
1683 __unmask_ioapic(data->chip_data);
1684 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1689 atomic_t irq_mis_count;
1691 #ifdef CONFIG_GENERIC_PENDING_IRQ
1692 static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1694 struct irq_pin_list *entry;
1695 unsigned long flags;
1697 raw_spin_lock_irqsave(&ioapic_lock, flags);
1698 for_each_irq_pin(entry, data->irq_2_pin) {
1703 reg = io_apic_read(entry->apic, 0x10 + pin*2);
1704 /* Is the remote IRR bit set? */
1705 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1706 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1710 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1715 static inline bool ioapic_prepare_move(struct irq_data *data)
1717 /* If we are moving the IRQ we need to mask it */
1718 if (unlikely(irqd_is_setaffinity_pending(data))) {
1719 if (!irqd_irq_masked(data))
1720 mask_ioapic_irq(data);
1726 static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1728 if (unlikely(moveit)) {
1729 /* Only migrate the irq if the ack has been received.
1731 * On rare occasions the broadcast level triggered ack gets
1732 * delayed going to ioapics, and if we reprogram the
1733 * vector while Remote IRR is still set the irq will never
1736 * To prevent this scenario we read the Remote IRR bit
1737 * of the ioapic. This has two effects.
1738 * - On any sane system the read of the ioapic will
1739 * flush writes (and acks) going to the ioapic from
1741 * - We get to see if the ACK has actually been delivered.
1743 * Based on failed experiments of reprogramming the
1744 * ioapic entry from outside of irq context starting
1745 * with masking the ioapic entry and then polling until
1746 * Remote IRR was clear before reprogramming the
1747 * ioapic I don't trust the Remote IRR bit to be
1748 * completey accurate.
1750 * However there appears to be no other way to plug
1751 * this race, so if the Remote IRR bit is not
1752 * accurate and is causing problems then it is a hardware bug
1753 * and you can go talk to the chipset vendor about it.
1755 if (!io_apic_level_ack_pending(data->chip_data))
1756 irq_move_masked_irq(data);
1757 /* If the IRQ is masked in the core, leave it: */
1758 if (!irqd_irq_masked(data))
1759 unmask_ioapic_irq(data);
1763 static inline bool ioapic_prepare_move(struct irq_data *data)
1767 static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1772 static void ioapic_ack_level(struct irq_data *irq_data)
1774 struct irq_cfg *cfg = irqd_cfg(irq_data);
1779 irq_complete_move(cfg);
1780 moveit = ioapic_prepare_move(irq_data);
1783 * It appears there is an erratum which affects at least version 0x11
1784 * of I/O APIC (that's the 82093AA and cores integrated into various
1785 * chipsets). Under certain conditions a level-triggered interrupt is
1786 * erroneously delivered as edge-triggered one but the respective IRR
1787 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1788 * message but it will never arrive and further interrupts are blocked
1789 * from the source. The exact reason is so far unknown, but the
1790 * phenomenon was observed when two consecutive interrupt requests
1791 * from a given source get delivered to the same CPU and the source is
1792 * temporarily disabled in between.
1794 * A workaround is to simulate an EOI message manually. We achieve it
1795 * by setting the trigger mode to edge and then to level when the edge
1796 * trigger mode gets detected in the TMR of a local APIC for a
1797 * level-triggered interrupt. We mask the source for the time of the
1798 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1799 * The idea is from Manfred Spraul. --macro
1801 * Also in the case when cpu goes offline, fixup_irqs() will forward
1802 * any unhandled interrupt on the offlined cpu to the new cpu
1803 * destination that is handling the corresponding interrupt. This
1804 * interrupt forwarding is done via IPI's. Hence, in this case also
1805 * level-triggered io-apic interrupt will be seen as an edge
1806 * interrupt in the IRR. And we can't rely on the cpu's EOI
1807 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1808 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1809 * supporting EOI register, we do an explicit EOI to clear the
1810 * remote IRR and on IO-APIC's which don't have an EOI register,
1811 * we use the above logic (mask+edge followed by unmask+level) from
1812 * Manfred Spraul to clear the remote IRR.
1815 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1818 * We must acknowledge the irq before we move it or the acknowledge will
1819 * not propagate properly.
1824 * Tail end of clearing remote IRR bit (either by delivering the EOI
1825 * message via io-apic EOI register write or simulating it using
1826 * mask+edge followed by unnask+level logic) manually when the
1827 * level triggered interrupt is seen as the edge triggered interrupt
1830 if (!(v & (1 << (i & 0x1f)))) {
1831 atomic_inc(&irq_mis_count);
1832 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1835 ioapic_finish_move(irq_data, moveit);
1838 static void ioapic_ir_ack_level(struct irq_data *irq_data)
1840 struct mp_chip_data *data = irq_data->chip_data;
1843 * Intr-remapping uses pin number as the virtual vector
1844 * in the RTE. Actual vector is programmed in
1845 * intr-remapping table entry. Hence for the io-apic
1846 * EOI we use the pin number.
1848 apic_ack_irq(irq_data);
1849 eoi_ioapic_pin(data->entry.vector, data);
1852 static void ioapic_configure_entry(struct irq_data *irqd)
1854 struct mp_chip_data *mpd = irqd->chip_data;
1855 struct irq_cfg *cfg = irqd_cfg(irqd);
1856 struct irq_pin_list *entry;
1859 * Only update when the parent is the vector domain, don't touch it
1860 * if the parent is the remapping domain. Check the installed
1861 * ioapic chip to verify that.
1863 if (irqd->chip == &ioapic_chip) {
1864 mpd->entry.dest = cfg->dest_apicid;
1865 mpd->entry.vector = cfg->vector;
1867 for_each_irq_pin(entry, mpd->irq_2_pin)
1868 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1871 static int ioapic_set_affinity(struct irq_data *irq_data,
1872 const struct cpumask *mask, bool force)
1874 struct irq_data *parent = irq_data->parent_data;
1875 unsigned long flags;
1878 ret = parent->chip->irq_set_affinity(parent, mask, force);
1879 raw_spin_lock_irqsave(&ioapic_lock, flags);
1880 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1881 ioapic_configure_entry(irq_data);
1882 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1888 * Interrupt shutdown masks the ioapic pin, but the interrupt might already
1889 * be in flight, but not yet serviced by the target CPU. That means
1890 * __synchronize_hardirq() would return and claim that everything is calmed
1891 * down. So free_irq() would proceed and deactivate the interrupt and free
1894 * Once the target CPU comes around to service it it will find a cleared
1895 * vector and complain. While the spurious interrupt is harmless, the full
1896 * release of resources might prevent the interrupt from being acknowledged
1897 * which keeps the hardware in a weird state.
1899 * Verify that the corresponding Remote-IRR bits are clear.
1901 static int ioapic_irq_get_chip_state(struct irq_data *irqd,
1902 enum irqchip_irq_state which,
1905 struct mp_chip_data *mcd = irqd->chip_data;
1906 struct IO_APIC_route_entry rentry;
1907 struct irq_pin_list *p;
1909 if (which != IRQCHIP_STATE_ACTIVE)
1913 raw_spin_lock(&ioapic_lock);
1914 for_each_irq_pin(p, mcd->irq_2_pin) {
1915 rentry = __ioapic_read_entry(p->apic, p->pin);
1917 * The remote IRR is only valid in level trigger mode. It's
1918 * meaning is undefined for edge triggered interrupts and
1919 * irrelevant because the IO-APIC treats them as fire and
1922 if (rentry.irr && rentry.trigger) {
1927 raw_spin_unlock(&ioapic_lock);
1931 static struct irq_chip ioapic_chip __read_mostly = {
1933 .irq_startup = startup_ioapic_irq,
1934 .irq_mask = mask_ioapic_irq,
1935 .irq_unmask = unmask_ioapic_irq,
1936 .irq_ack = irq_chip_ack_parent,
1937 .irq_eoi = ioapic_ack_level,
1938 .irq_set_affinity = ioapic_set_affinity,
1939 .irq_retrigger = irq_chip_retrigger_hierarchy,
1940 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1941 .flags = IRQCHIP_SKIP_SET_WAKE,
1944 static struct irq_chip ioapic_ir_chip __read_mostly = {
1945 .name = "IR-IO-APIC",
1946 .irq_startup = startup_ioapic_irq,
1947 .irq_mask = mask_ioapic_irq,
1948 .irq_unmask = unmask_ioapic_irq,
1949 .irq_ack = irq_chip_ack_parent,
1950 .irq_eoi = ioapic_ir_ack_level,
1951 .irq_set_affinity = ioapic_set_affinity,
1952 .irq_retrigger = irq_chip_retrigger_hierarchy,
1953 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1954 .flags = IRQCHIP_SKIP_SET_WAKE,
1957 static inline void init_IO_APIC_traps(void)
1959 struct irq_cfg *cfg;
1962 for_each_active_irq(irq) {
1964 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1966 * Hmm.. We don't have an entry for this,
1967 * so default to an old-fashioned 8259
1968 * interrupt if we can..
1970 if (irq < nr_legacy_irqs())
1971 legacy_pic->make_irq(irq);
1973 /* Strange. Oh, well.. */
1974 irq_set_chip(irq, &no_irq_chip);
1980 * The local APIC irq-chip implementation:
1983 static void mask_lapic_irq(struct irq_data *data)
1987 v = apic_read(APIC_LVT0);
1988 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1991 static void unmask_lapic_irq(struct irq_data *data)
1995 v = apic_read(APIC_LVT0);
1996 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1999 static void ack_lapic_irq(struct irq_data *data)
2004 static struct irq_chip lapic_chip __read_mostly = {
2005 .name = "local-APIC",
2006 .irq_mask = mask_lapic_irq,
2007 .irq_unmask = unmask_lapic_irq,
2008 .irq_ack = ack_lapic_irq,
2011 static void lapic_register_intr(int irq)
2013 irq_clear_status_flags(irq, IRQ_LEVEL);
2014 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2019 * This looks a bit hackish but it's about the only one way of sending
2020 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2021 * not support the ExtINT mode, unfortunately. We need to send these
2022 * cycles as some i82489DX-based boards have glue logic that keeps the
2023 * 8259A interrupt line asserted until INTA. --macro
2025 static inline void __init unlock_ExtINT_logic(void)
2028 struct IO_APIC_route_entry entry0, entry1;
2029 unsigned char save_control, save_freq_select;
2031 pin = find_isa_irq_pin(8, mp_INT);
2036 apic = find_isa_irq_apic(8, mp_INT);
2042 entry0 = ioapic_read_entry(apic, pin);
2043 clear_IO_APIC_pin(apic, pin);
2045 memset(&entry1, 0, sizeof(entry1));
2047 entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
2048 entry1.mask = IOAPIC_UNMASKED;
2049 entry1.dest = hard_smp_processor_id();
2050 entry1.delivery_mode = dest_ExtINT;
2051 entry1.polarity = entry0.polarity;
2052 entry1.trigger = IOAPIC_EDGE;
2055 ioapic_write_entry(apic, pin, entry1);
2057 save_control = CMOS_READ(RTC_CONTROL);
2058 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2059 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2061 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2066 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2070 CMOS_WRITE(save_control, RTC_CONTROL);
2071 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2072 clear_IO_APIC_pin(apic, pin);
2074 ioapic_write_entry(apic, pin, entry0);
2077 static int disable_timer_pin_1 __initdata;
2078 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2079 static int __init disable_timer_pin_setup(char *arg)
2081 disable_timer_pin_1 = 1;
2084 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2086 static int mp_alloc_timer_irq(int ioapic, int pin)
2089 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2092 struct irq_alloc_info info;
2094 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2095 info.devid = mpc_ioapic_id(ioapic);
2096 info.ioapic.pin = pin;
2097 mutex_lock(&ioapic_mutex);
2098 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2099 mutex_unlock(&ioapic_mutex);
2106 * This code may look a bit paranoid, but it's supposed to cooperate with
2107 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2108 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2109 * fanatically on his truly buggy board.
2111 * FIXME: really need to revamp this for all platforms.
2113 static inline void __init check_timer(void)
2115 struct irq_data *irq_data = irq_get_irq_data(0);
2116 struct mp_chip_data *data = irq_data->chip_data;
2117 struct irq_cfg *cfg = irqd_cfg(irq_data);
2118 int node = cpu_to_node(0);
2119 int apic1, pin1, apic2, pin2;
2120 unsigned long flags;
2123 if (!global_clock_event)
2126 local_irq_save(flags);
2129 * get/set the timer IRQ vector:
2131 legacy_pic->mask(0);
2134 * As IRQ0 is to be enabled in the 8259A, the virtual
2135 * wire has to be disabled in the local APIC. Also
2136 * timer interrupts need to be acknowledged manually in
2137 * the 8259A for the i82489DX when using the NMI
2138 * watchdog as that APIC treats NMIs as level-triggered.
2139 * The AEOI mode will finish them in the 8259A
2142 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2143 legacy_pic->init(1);
2145 pin1 = find_isa_irq_pin(0, mp_INT);
2146 apic1 = find_isa_irq_apic(0, mp_INT);
2147 pin2 = ioapic_i8259.pin;
2148 apic2 = ioapic_i8259.apic;
2150 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2151 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2152 cfg->vector, apic1, pin1, apic2, pin2);
2155 * Some BIOS writers are clueless and report the ExtINTA
2156 * I/O APIC input from the cascaded 8259A as the timer
2157 * interrupt input. So just in case, if only one pin
2158 * was found above, try it both directly and through the
2162 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2166 } else if (pin2 == -1) {
2172 /* Ok, does IRQ0 through the IOAPIC work? */
2174 mp_alloc_timer_irq(apic1, pin1);
2177 * for edge trigger, it's already unmasked,
2178 * so only need to unmask if it is level-trigger
2179 * do we really have level trigger timer?
2182 idx = find_irq_entry(apic1, pin1, mp_INT);
2183 if (idx != -1 && irq_trigger(idx))
2184 unmask_ioapic_irq(irq_get_irq_data(0));
2186 irq_domain_deactivate_irq(irq_data);
2187 irq_domain_activate_irq(irq_data, false);
2188 if (timer_irq_works()) {
2189 if (disable_timer_pin_1 > 0)
2190 clear_IO_APIC_pin(0, pin1);
2193 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2194 local_irq_disable();
2195 clear_IO_APIC_pin(apic1, pin1);
2197 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2198 "8254 timer not connected to IO-APIC\n");
2200 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2201 "(IRQ0) through the 8259A ...\n");
2202 apic_printk(APIC_QUIET, KERN_INFO
2203 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2205 * legacy devices should be connected to IO APIC #0
2207 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2208 irq_domain_deactivate_irq(irq_data);
2209 irq_domain_activate_irq(irq_data, false);
2210 legacy_pic->unmask(0);
2211 if (timer_irq_works()) {
2212 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2216 * Cleanup, just in case ...
2218 local_irq_disable();
2219 legacy_pic->mask(0);
2220 clear_IO_APIC_pin(apic2, pin2);
2221 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2224 apic_printk(APIC_QUIET, KERN_INFO
2225 "...trying to set up timer as Virtual Wire IRQ...\n");
2227 lapic_register_intr(0);
2228 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2229 legacy_pic->unmask(0);
2231 if (timer_irq_works()) {
2232 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2235 local_irq_disable();
2236 legacy_pic->mask(0);
2237 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2238 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2240 apic_printk(APIC_QUIET, KERN_INFO
2241 "...trying to set up timer as ExtINT IRQ...\n");
2243 legacy_pic->init(0);
2244 legacy_pic->make_irq(0);
2245 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2246 legacy_pic->unmask(0);
2248 unlock_ExtINT_logic();
2250 if (timer_irq_works()) {
2251 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2254 local_irq_disable();
2255 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2256 if (apic_is_x2apic_enabled())
2257 apic_printk(APIC_QUIET, KERN_INFO
2258 "Perhaps problem with the pre-enabled x2apic mode\n"
2259 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2260 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2261 "report. Then try booting with the 'noapic' option.\n");
2263 local_irq_restore(flags);
2267 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2268 * to devices. However there may be an I/O APIC pin available for
2269 * this interrupt regardless. The pin may be left unconnected, but
2270 * typically it will be reused as an ExtINT cascade interrupt for
2271 * the master 8259A. In the MPS case such a pin will normally be
2272 * reported as an ExtINT interrupt in the MP table. With ACPI
2273 * there is no provision for ExtINT interrupts, and in the absence
2274 * of an override it would be treated as an ordinary ISA I/O APIC
2275 * interrupt, that is edge-triggered and unmasked by default. We
2276 * used to do this, but it caused problems on some systems because
2277 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2278 * the same ExtINT cascade interrupt to drive the local APIC of the
2279 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2280 * the I/O APIC in all cases now. No actual device should request
2281 * it anyway. --macro
2283 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2285 static int mp_irqdomain_create(int ioapic)
2287 struct irq_alloc_info info;
2288 struct irq_domain *parent;
2289 int hwirqs = mp_ioapic_pin_count(ioapic);
2290 struct ioapic *ip = &ioapics[ioapic];
2291 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2292 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2293 struct fwnode_handle *fn;
2294 char *name = "IO-APIC";
2296 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2299 init_irq_alloc_info(&info, NULL);
2300 info.type = X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT;
2301 info.devid = mpc_ioapic_id(ioapic);
2302 parent = irq_remapping_get_irq_domain(&info);
2304 parent = x86_vector_domain;
2306 name = "IO-APIC-IR";
2308 /* Handle device tree enumerated APICs proper */
2310 fn = of_node_to_fwnode(cfg->dev);
2312 fn = irq_domain_alloc_named_id_fwnode(name, ioapic);
2317 ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops,
2318 (void *)(long)ioapic);
2320 if (!ip->irqdomain) {
2321 /* Release fw handle if it was allocated above */
2323 irq_domain_free_fwnode(fn);
2327 ip->irqdomain->parent = parent;
2329 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2330 cfg->type == IOAPIC_DOMAIN_STRICT)
2331 ioapic_dynirq_base = max(ioapic_dynirq_base,
2332 gsi_cfg->gsi_end + 1);
2337 static void ioapic_destroy_irqdomain(int idx)
2339 struct ioapic_domain_cfg *cfg = &ioapics[idx].irqdomain_cfg;
2340 struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode;
2342 if (ioapics[idx].irqdomain) {
2343 irq_domain_remove(ioapics[idx].irqdomain);
2345 irq_domain_free_fwnode(fn);
2346 ioapics[idx].irqdomain = NULL;
2350 void __init setup_IO_APIC(void)
2354 if (skip_ioapic_setup || !nr_ioapics)
2357 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2359 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2360 for_each_ioapic(ioapic)
2361 BUG_ON(mp_irqdomain_create(ioapic));
2364 * Set up IO-APIC IRQ routing.
2366 x86_init.mpparse.setup_ioapic_ids();
2369 setup_IO_APIC_irqs();
2370 init_IO_APIC_traps();
2371 if (nr_legacy_irqs())
2374 ioapic_initialized = 1;
2377 static void resume_ioapic_id(int ioapic_idx)
2379 unsigned long flags;
2380 union IO_APIC_reg_00 reg_00;
2382 raw_spin_lock_irqsave(&ioapic_lock, flags);
2383 reg_00.raw = io_apic_read(ioapic_idx, 0);
2384 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2385 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2386 io_apic_write(ioapic_idx, 0, reg_00.raw);
2388 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2391 static void ioapic_resume(void)
2395 for_each_ioapic_reverse(ioapic_idx)
2396 resume_ioapic_id(ioapic_idx);
2398 restore_ioapic_entries();
2401 static struct syscore_ops ioapic_syscore_ops = {
2402 .suspend = save_ioapic_entries,
2403 .resume = ioapic_resume,
2406 static int __init ioapic_init_ops(void)
2408 register_syscore_ops(&ioapic_syscore_ops);
2413 device_initcall(ioapic_init_ops);
2415 static int io_apic_get_redir_entries(int ioapic)
2417 union IO_APIC_reg_01 reg_01;
2418 unsigned long flags;
2420 raw_spin_lock_irqsave(&ioapic_lock, flags);
2421 reg_01.raw = io_apic_read(ioapic, 1);
2422 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2424 /* The register returns the maximum index redir index
2425 * supported, which is one less than the total number of redir
2428 return reg_01.bits.entries + 1;
2431 unsigned int arch_dynirq_lower_bound(unsigned int from)
2434 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2435 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2437 if (!ioapic_initialized)
2440 * For DT enabled machines ioapic_dynirq_base is irrelevant and not
2441 * updated. So simply return @from if ioapic_dynirq_base == 0.
2443 return ioapic_dynirq_base ? : from;
2446 #ifdef CONFIG_X86_32
2447 static int io_apic_get_unique_id(int ioapic, int apic_id)
2449 union IO_APIC_reg_00 reg_00;
2450 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2452 unsigned long flags;
2456 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2457 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2458 * supports up to 16 on one shared APIC bus.
2460 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2461 * advantage of new APIC bus architecture.
2464 if (physids_empty(apic_id_map))
2465 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2467 raw_spin_lock_irqsave(&ioapic_lock, flags);
2468 reg_00.raw = io_apic_read(ioapic, 0);
2469 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2471 if (apic_id >= get_physical_broadcast()) {
2472 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2473 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2474 apic_id = reg_00.bits.ID;
2478 * Every APIC in a system must have a unique ID or we get lots of nice
2479 * 'stuck on smp_invalidate_needed IPI wait' messages.
2481 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2483 for (i = 0; i < get_physical_broadcast(); i++) {
2484 if (!apic->check_apicid_used(&apic_id_map, i))
2488 if (i == get_physical_broadcast())
2489 panic("Max apic_id exceeded!\n");
2491 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2492 "trying %d\n", ioapic, apic_id, i);
2497 apic->apicid_to_cpu_present(apic_id, &tmp);
2498 physids_or(apic_id_map, apic_id_map, tmp);
2500 if (reg_00.bits.ID != apic_id) {
2501 reg_00.bits.ID = apic_id;
2503 raw_spin_lock_irqsave(&ioapic_lock, flags);
2504 io_apic_write(ioapic, 0, reg_00.raw);
2505 reg_00.raw = io_apic_read(ioapic, 0);
2506 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2509 if (reg_00.bits.ID != apic_id) {
2510 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2516 apic_printk(APIC_VERBOSE, KERN_INFO
2517 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2522 static u8 io_apic_unique_id(int idx, u8 id)
2524 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2525 !APIC_XAPIC(boot_cpu_apic_version))
2526 return io_apic_get_unique_id(idx, id);
2531 static u8 io_apic_unique_id(int idx, u8 id)
2533 union IO_APIC_reg_00 reg_00;
2534 DECLARE_BITMAP(used, 256);
2535 unsigned long flags;
2539 bitmap_zero(used, 256);
2541 __set_bit(mpc_ioapic_id(i), used);
2543 /* Hand out the requested id if available */
2544 if (!test_bit(id, used))
2548 * Read the current id from the ioapic and keep it if
2551 raw_spin_lock_irqsave(&ioapic_lock, flags);
2552 reg_00.raw = io_apic_read(idx, 0);
2553 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2554 new_id = reg_00.bits.ID;
2555 if (!test_bit(new_id, used)) {
2556 apic_printk(APIC_VERBOSE, KERN_INFO
2557 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2563 * Get the next free id and write it to the ioapic.
2565 new_id = find_first_zero_bit(used, 256);
2566 reg_00.bits.ID = new_id;
2567 raw_spin_lock_irqsave(&ioapic_lock, flags);
2568 io_apic_write(idx, 0, reg_00.raw);
2569 reg_00.raw = io_apic_read(idx, 0);
2570 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2572 BUG_ON(reg_00.bits.ID != new_id);
2578 static int io_apic_get_version(int ioapic)
2580 union IO_APIC_reg_01 reg_01;
2581 unsigned long flags;
2583 raw_spin_lock_irqsave(&ioapic_lock, flags);
2584 reg_01.raw = io_apic_read(ioapic, 1);
2585 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2587 return reg_01.bits.version;
2590 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2592 int ioapic, pin, idx;
2594 if (skip_ioapic_setup)
2597 ioapic = mp_find_ioapic(gsi);
2601 pin = mp_find_ioapic_pin(ioapic, gsi);
2605 idx = find_irq_entry(ioapic, pin, mp_INT);
2609 *trigger = irq_trigger(idx);
2610 *polarity = irq_polarity(idx);
2615 * This function updates target affinity of IOAPIC interrupts to include
2616 * the CPUs which came online during SMP bringup.
2618 #define IOAPIC_RESOURCE_NAME_SIZE 11
2620 static struct resource *ioapic_resources;
2622 static struct resource * __init ioapic_setup_resources(void)
2625 struct resource *res;
2629 if (nr_ioapics == 0)
2632 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2635 mem = memblock_alloc(n, SMP_CACHE_BYTES);
2637 panic("%s: Failed to allocate %lu bytes\n", __func__, n);
2640 mem += sizeof(struct resource) * nr_ioapics;
2642 for_each_ioapic(i) {
2644 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2645 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2646 mem += IOAPIC_RESOURCE_NAME_SIZE;
2647 ioapics[i].iomem_res = &res[i];
2650 ioapic_resources = res;
2655 void __init io_apic_init_mappings(void)
2657 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2658 struct resource *ioapic_res;
2661 ioapic_res = ioapic_setup_resources();
2662 for_each_ioapic(i) {
2663 if (smp_found_config) {
2664 ioapic_phys = mpc_ioapic_addr(i);
2665 #ifdef CONFIG_X86_32
2668 "WARNING: bogus zero IO-APIC "
2669 "address found in MPTABLE, "
2670 "disabling IO/APIC support!\n");
2671 smp_found_config = 0;
2672 skip_ioapic_setup = 1;
2673 goto fake_ioapic_page;
2677 #ifdef CONFIG_X86_32
2680 ioapic_phys = (unsigned long)memblock_alloc(PAGE_SIZE,
2683 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
2684 __func__, PAGE_SIZE, PAGE_SIZE);
2685 ioapic_phys = __pa(ioapic_phys);
2687 set_fixmap_nocache(idx, ioapic_phys);
2688 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2689 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2693 ioapic_res->start = ioapic_phys;
2694 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2699 void __init ioapic_insert_resources(void)
2702 struct resource *r = ioapic_resources;
2707 "IO APIC resources couldn't be allocated.\n");
2711 for_each_ioapic(i) {
2712 insert_resource(&iomem_resource, r);
2717 int mp_find_ioapic(u32 gsi)
2721 if (nr_ioapics == 0)
2724 /* Find the IOAPIC that manages this GSI. */
2725 for_each_ioapic(i) {
2726 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2727 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2731 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2735 int mp_find_ioapic_pin(int ioapic, u32 gsi)
2737 struct mp_ioapic_gsi *gsi_cfg;
2739 if (WARN_ON(ioapic < 0))
2742 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2743 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2746 return gsi - gsi_cfg->gsi_base;
2749 static int bad_ioapic_register(int idx)
2751 union IO_APIC_reg_00 reg_00;
2752 union IO_APIC_reg_01 reg_01;
2753 union IO_APIC_reg_02 reg_02;
2755 reg_00.raw = io_apic_read(idx, 0);
2756 reg_01.raw = io_apic_read(idx, 1);
2757 reg_02.raw = io_apic_read(idx, 2);
2759 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2760 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2761 mpc_ioapic_addr(idx));
2768 static int find_free_ioapic_entry(void)
2772 for (idx = 0; idx < MAX_IO_APICS; idx++)
2773 if (ioapics[idx].nr_registers == 0)
2776 return MAX_IO_APICS;
2780 * mp_register_ioapic - Register an IOAPIC device
2781 * @id: hardware IOAPIC ID
2782 * @address: physical address of IOAPIC register area
2783 * @gsi_base: base of GSI associated with the IOAPIC
2784 * @cfg: configuration information for the IOAPIC
2786 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2787 struct ioapic_domain_cfg *cfg)
2789 bool hotplug = !!ioapic_initialized;
2790 struct mp_ioapic_gsi *gsi_cfg;
2791 int idx, ioapic, entries;
2795 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2798 for_each_ioapic(ioapic)
2799 if (ioapics[ioapic].mp_config.apicaddr == address) {
2800 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2805 idx = find_free_ioapic_entry();
2806 if (idx >= MAX_IO_APICS) {
2807 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2812 ioapics[idx].mp_config.type = MP_IOAPIC;
2813 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2814 ioapics[idx].mp_config.apicaddr = address;
2816 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2817 if (bad_ioapic_register(idx)) {
2818 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2822 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2823 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2826 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2827 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2829 entries = io_apic_get_redir_entries(idx);
2830 gsi_end = gsi_base + entries - 1;
2831 for_each_ioapic(ioapic) {
2832 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2833 if ((gsi_base >= gsi_cfg->gsi_base &&
2834 gsi_base <= gsi_cfg->gsi_end) ||
2835 (gsi_end >= gsi_cfg->gsi_base &&
2836 gsi_end <= gsi_cfg->gsi_end)) {
2837 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2839 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2840 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2844 gsi_cfg = mp_ioapic_gsi_routing(idx);
2845 gsi_cfg->gsi_base = gsi_base;
2846 gsi_cfg->gsi_end = gsi_end;
2848 ioapics[idx].irqdomain = NULL;
2849 ioapics[idx].irqdomain_cfg = *cfg;
2852 * If mp_register_ioapic() is called during early boot stage when
2853 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2854 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2857 if (mp_irqdomain_create(idx)) {
2858 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2861 alloc_ioapic_saved_registers(idx);
2864 if (gsi_cfg->gsi_end >= gsi_top)
2865 gsi_top = gsi_cfg->gsi_end + 1;
2866 if (nr_ioapics <= idx)
2867 nr_ioapics = idx + 1;
2869 /* Set nr_registers to mark entry present */
2870 ioapics[idx].nr_registers = entries;
2872 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2873 idx, mpc_ioapic_id(idx),
2874 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2875 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2880 int mp_unregister_ioapic(u32 gsi_base)
2885 for_each_ioapic(ioapic)
2886 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2891 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2895 for_each_pin(ioapic, pin) {
2896 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2897 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2898 struct mp_chip_data *data;
2901 data = irq_get_chip_data(irq);
2902 if (data && data->count) {
2903 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2910 /* Mark entry not present */
2911 ioapics[ioapic].nr_registers = 0;
2912 ioapic_destroy_irqdomain(ioapic);
2913 free_ioapic_saved_registers(ioapic);
2914 if (ioapics[ioapic].iomem_res)
2915 release_resource(ioapics[ioapic].iomem_res);
2916 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2917 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2922 int mp_ioapic_registered(u32 gsi_base)
2926 for_each_ioapic(ioapic)
2927 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2933 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2934 struct irq_alloc_info *info)
2936 if (info && info->ioapic.valid) {
2937 data->trigger = info->ioapic.trigger;
2938 data->polarity = info->ioapic.polarity;
2939 } else if (acpi_get_override_irq(gsi, &data->trigger,
2940 &data->polarity) < 0) {
2941 /* PCI interrupts are always active low level triggered. */
2942 data->trigger = IOAPIC_LEVEL;
2943 data->polarity = IOAPIC_POL_LOW;
2947 static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
2948 struct IO_APIC_route_entry *entry)
2950 memset(entry, 0, sizeof(*entry));
2951 entry->delivery_mode = apic->irq_delivery_mode;
2952 entry->dest_mode = apic->irq_dest_mode;
2953 entry->dest = cfg->dest_apicid;
2954 entry->vector = cfg->vector;
2955 entry->trigger = data->trigger;
2956 entry->polarity = data->polarity;
2958 * Mask level triggered irqs. Edge triggered irqs are masked
2959 * by the irq core code in case they fire.
2961 if (data->trigger == IOAPIC_LEVEL)
2962 entry->mask = IOAPIC_MASKED;
2964 entry->mask = IOAPIC_UNMASKED;
2967 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2968 unsigned int nr_irqs, void *arg)
2970 int ret, ioapic, pin;
2971 struct irq_cfg *cfg;
2972 struct irq_data *irq_data;
2973 struct mp_chip_data *data;
2974 struct irq_alloc_info *info = arg;
2975 unsigned long flags;
2977 if (!info || nr_irqs > 1)
2979 irq_data = irq_domain_get_irq_data(domain, virq);
2983 ioapic = mp_irqdomain_ioapic_idx(domain);
2984 pin = info->ioapic.pin;
2985 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
2988 data = kzalloc(sizeof(*data), GFP_KERNEL);
2992 info->ioapic.entry = &data->entry;
2993 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
2999 INIT_LIST_HEAD(&data->irq_2_pin);
3000 irq_data->hwirq = info->ioapic.pin;
3001 irq_data->chip = (domain->parent == x86_vector_domain) ?
3002 &ioapic_chip : &ioapic_ir_chip;
3003 irq_data->chip_data = data;
3004 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
3006 cfg = irqd_cfg(irq_data);
3007 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
3009 local_irq_save(flags);
3010 if (info->ioapic.entry)
3011 mp_setup_entry(cfg, data, info->ioapic.entry);
3012 mp_register_handler(virq, data->trigger);
3013 if (virq < nr_legacy_irqs())
3014 legacy_pic->mask(virq);
3015 local_irq_restore(flags);
3017 apic_printk(APIC_VERBOSE, KERN_DEBUG
3018 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
3019 ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
3020 virq, data->trigger, data->polarity, cfg->dest_apicid);
3025 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
3026 unsigned int nr_irqs)
3028 struct irq_data *irq_data;
3029 struct mp_chip_data *data;
3031 BUG_ON(nr_irqs != 1);
3032 irq_data = irq_domain_get_irq_data(domain, virq);
3033 if (irq_data && irq_data->chip_data) {
3034 data = irq_data->chip_data;
3035 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
3036 (int)irq_data->hwirq);
3037 WARN_ON(!list_empty(&data->irq_2_pin));
3038 kfree(irq_data->chip_data);
3040 irq_domain_free_irqs_top(domain, virq, nr_irqs);
3043 int mp_irqdomain_activate(struct irq_domain *domain,
3044 struct irq_data *irq_data, bool reserve)
3046 unsigned long flags;
3048 raw_spin_lock_irqsave(&ioapic_lock, flags);
3049 ioapic_configure_entry(irq_data);
3050 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3054 void mp_irqdomain_deactivate(struct irq_domain *domain,
3055 struct irq_data *irq_data)
3057 /* It won't be called for IRQ with multiple IOAPIC pins associated */
3058 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3059 (int)irq_data->hwirq);
3062 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3064 return (int)(long)domain->host_data;
3067 const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3068 .alloc = mp_irqdomain_alloc,
3069 .free = mp_irqdomain_free,
3070 .activate = mp_irqdomain_activate,
3071 .deactivate = mp_irqdomain_deactivate,