1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
7 * Many thanks to Stig Venaas for trying out countless experimental
8 * patches and reporting/debugging problems patiently!
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13 * further tested and cleaned up by Zach Brown <zab@redhat.com>
14 * and Ingo Molnar <mingo@redhat.com>
17 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
18 * thanks to Eric Gilmore
20 * for testing these extensively
21 * Paul Diefenbaugh : Added full ACPI support
23 * Historical information which is worth to be preserved:
27 * We used to have a workaround for a bug in SiS chips which
28 * required to rewrite the index register for a read-modify-write
29 * operation as the chip lost the index information which was
30 * setup for the read already. We cache the data now, so that
31 * workaround has been removed.
35 #include <linux/interrupt.h>
36 #include <linux/irq.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/pci.h>
41 #include <linux/mc146818rtc.h>
42 #include <linux/compiler.h>
43 #include <linux/acpi.h>
44 #include <linux/export.h>
45 #include <linux/syscore_ops.h>
46 #include <linux/freezer.h>
47 #include <linux/kthread.h>
48 #include <linux/jiffies.h> /* time_after() */
49 #include <linux/slab.h>
50 #include <linux/memblock.h>
51 #include <linux/msi.h>
53 #include <asm/irqdomain.h>
58 #include <asm/proto.h>
61 #include <asm/timer.h>
63 #include <asm/i8259.h>
64 #include <asm/setup.h>
65 #include <asm/irq_remapping.h>
66 #include <asm/hw_irq.h>
68 #include <asm/pgtable.h>
69 #include <asm/x86_init.h>
71 #define for_each_ioapic(idx) \
72 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
73 #define for_each_ioapic_reverse(idx) \
74 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
75 #define for_each_pin(idx, pin) \
76 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
77 #define for_each_ioapic_pin(idx, pin) \
78 for_each_ioapic((idx)) \
79 for_each_pin((idx), (pin))
80 #define for_each_irq_pin(entry, head) \
81 list_for_each_entry(entry, &head, list)
83 static DEFINE_RAW_SPINLOCK(ioapic_lock);
84 static DEFINE_MUTEX(ioapic_mutex);
85 static unsigned int ioapic_dynirq_base;
86 static int ioapic_initialized;
89 struct list_head list;
94 struct list_head irq_2_pin;
95 struct IO_APIC_route_entry entry;
102 struct mp_ioapic_gsi {
107 static struct ioapic {
109 * # of IRQ routing registers
113 * Saved state during suspend/resume, or while enabling intr-remap.
115 struct IO_APIC_route_entry *saved_registers;
116 /* I/O APIC config */
117 struct mpc_ioapic mp_config;
118 /* IO APIC gsi routing info */
119 struct mp_ioapic_gsi gsi_config;
120 struct ioapic_domain_cfg irqdomain_cfg;
121 struct irq_domain *irqdomain;
122 struct resource *iomem_res;
123 } ioapics[MAX_IO_APICS];
125 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
127 int mpc_ioapic_id(int ioapic_idx)
129 return ioapics[ioapic_idx].mp_config.apicid;
132 unsigned int mpc_ioapic_addr(int ioapic_idx)
134 return ioapics[ioapic_idx].mp_config.apicaddr;
137 static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
139 return &ioapics[ioapic_idx].gsi_config;
142 static inline int mp_ioapic_pin_count(int ioapic)
144 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
146 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
149 static inline u32 mp_pin_to_gsi(int ioapic, int pin)
151 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
154 static inline bool mp_is_legacy_irq(int irq)
156 return irq >= 0 && irq < nr_legacy_irqs();
159 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
161 return ioapics[ioapic].irqdomain;
166 /* The one past the highest gsi number used */
169 /* MP IRQ source entries */
170 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
172 /* # of MP IRQ source entries */
176 int mp_bus_id_to_type[MAX_MP_BUSSES];
179 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
181 int skip_ioapic_setup;
184 * disable_ioapic_support() - disables ioapic support at runtime
186 void disable_ioapic_support(void)
190 noioapicreroute = -1;
192 skip_ioapic_setup = 1;
195 static int __init parse_noapic(char *str)
197 /* disable IO-APIC */
198 disable_ioapic_support();
201 early_param("noapic", parse_noapic);
203 /* Will be called in mpparse/ACPI codes for saving IRQ info */
204 void mp_save_irq(struct mpc_intsrc *m)
208 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
209 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
210 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
211 m->srcbusirq, m->dstapic, m->dstirq);
213 for (i = 0; i < mp_irq_entries; i++) {
214 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
218 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
219 if (++mp_irq_entries == MAX_IRQ_SOURCES)
220 panic("Max # of irq sources exceeded!!\n");
223 static void alloc_ioapic_saved_registers(int idx)
227 if (ioapics[idx].saved_registers)
230 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
231 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
232 if (!ioapics[idx].saved_registers)
233 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
236 static void free_ioapic_saved_registers(int idx)
238 kfree(ioapics[idx].saved_registers);
239 ioapics[idx].saved_registers = NULL;
242 int __init arch_early_ioapic_init(void)
246 if (!nr_legacy_irqs())
250 alloc_ioapic_saved_registers(i);
257 unsigned int unused[3];
259 unsigned int unused2[11];
263 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
265 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
266 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
269 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
271 struct io_apic __iomem *io_apic = io_apic_base(apic);
272 writel(vector, &io_apic->eoi);
275 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
277 struct io_apic __iomem *io_apic = io_apic_base(apic);
278 writel(reg, &io_apic->index);
279 return readl(&io_apic->data);
282 static void io_apic_write(unsigned int apic, unsigned int reg,
285 struct io_apic __iomem *io_apic = io_apic_base(apic);
287 writel(reg, &io_apic->index);
288 writel(value, &io_apic->data);
291 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
293 struct IO_APIC_route_entry entry;
295 entry.w1 = io_apic_read(apic, 0x10 + 2 * pin);
296 entry.w2 = io_apic_read(apic, 0x11 + 2 * pin);
301 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
303 struct IO_APIC_route_entry entry;
306 raw_spin_lock_irqsave(&ioapic_lock, flags);
307 entry = __ioapic_read_entry(apic, pin);
308 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
314 * When we write a new IO APIC routing entry, we need to write the high
315 * word first! If the mask bit in the low word is clear, we will enable
316 * the interrupt, and we need to make sure the entry is fully populated
317 * before that happens.
319 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
321 io_apic_write(apic, 0x11 + 2*pin, e.w2);
322 io_apic_write(apic, 0x10 + 2*pin, e.w1);
325 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
329 raw_spin_lock_irqsave(&ioapic_lock, flags);
330 __ioapic_write_entry(apic, pin, e);
331 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
335 * When we mask an IO APIC routing entry, we need to write the low
336 * word first, in order to set the mask bit before we change the
339 static void ioapic_mask_entry(int apic, int pin)
341 struct IO_APIC_route_entry e = { .masked = true };
344 raw_spin_lock_irqsave(&ioapic_lock, flags);
345 io_apic_write(apic, 0x10 + 2*pin, e.w1);
346 io_apic_write(apic, 0x11 + 2*pin, e.w2);
347 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
351 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
352 * shared ISA-space IRQs, so we have to support them. We are super
353 * fast in the common case, and fast for shared ISA-space IRQs.
355 static int __add_pin_to_irq_node(struct mp_chip_data *data,
356 int node, int apic, int pin)
358 struct irq_pin_list *entry;
360 /* don't allow duplicates */
361 for_each_irq_pin(entry, data->irq_2_pin)
362 if (entry->apic == apic && entry->pin == pin)
365 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
367 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
373 list_add_tail(&entry->list, &data->irq_2_pin);
378 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
380 struct irq_pin_list *tmp, *entry;
382 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
383 if (entry->apic == apic && entry->pin == pin) {
384 list_del(&entry->list);
390 static void add_pin_to_irq_node(struct mp_chip_data *data,
391 int node, int apic, int pin)
393 if (__add_pin_to_irq_node(data, node, apic, pin))
394 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
398 * Reroute an IRQ to a different pin.
400 static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
401 int oldapic, int oldpin,
402 int newapic, int newpin)
404 struct irq_pin_list *entry;
406 for_each_irq_pin(entry, data->irq_2_pin) {
407 if (entry->apic == oldapic && entry->pin == oldpin) {
408 entry->apic = newapic;
410 /* every one is different, right? */
415 /* old apic/pin didn't exist, so just add new ones */
416 add_pin_to_irq_node(data, node, newapic, newpin);
419 static void io_apic_modify_irq(struct mp_chip_data *data, bool masked,
420 void (*final)(struct irq_pin_list *entry))
422 struct irq_pin_list *entry;
424 data->entry.masked = masked;
426 for_each_irq_pin(entry, data->irq_2_pin) {
427 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1);
433 static void io_apic_sync(struct irq_pin_list *entry)
436 * Synchronize the IO-APIC and the CPU by doing
437 * a dummy read from the IO-APIC
439 struct io_apic __iomem *io_apic;
441 io_apic = io_apic_base(entry->apic);
442 readl(&io_apic->data);
445 static void mask_ioapic_irq(struct irq_data *irq_data)
447 struct mp_chip_data *data = irq_data->chip_data;
450 raw_spin_lock_irqsave(&ioapic_lock, flags);
451 io_apic_modify_irq(data, true, &io_apic_sync);
452 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
455 static void __unmask_ioapic(struct mp_chip_data *data)
457 io_apic_modify_irq(data, false, NULL);
460 static void unmask_ioapic_irq(struct irq_data *irq_data)
462 struct mp_chip_data *data = irq_data->chip_data;
465 raw_spin_lock_irqsave(&ioapic_lock, flags);
466 __unmask_ioapic(data);
467 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
471 * IO-APIC versions below 0x20 don't support EOI register.
472 * For the record, here is the information about various versions:
474 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
475 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
478 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
479 * version as 0x2. This is an error with documentation and these ICH chips
480 * use io-apic's of version 0x20.
482 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
483 * Otherwise, we simulate the EOI message manually by changing the trigger
484 * mode to edge and then back to level, with RTE being masked during this.
486 static void __eoi_ioapic_pin(int apic, int pin, int vector)
488 if (mpc_ioapic_ver(apic) >= 0x20) {
489 io_apic_eoi(apic, vector);
491 struct IO_APIC_route_entry entry, entry1;
493 entry = entry1 = __ioapic_read_entry(apic, pin);
496 * Mask the entry and change the trigger mode to edge.
498 entry1.masked = true;
499 entry1.is_level = false;
501 __ioapic_write_entry(apic, pin, entry1);
504 * Restore the previous level triggered entry.
506 __ioapic_write_entry(apic, pin, entry);
510 static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
513 struct irq_pin_list *entry;
515 raw_spin_lock_irqsave(&ioapic_lock, flags);
516 for_each_irq_pin(entry, data->irq_2_pin)
517 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
518 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
521 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
523 struct IO_APIC_route_entry entry;
525 /* Check delivery_mode to be sure we're not clearing an SMI pin */
526 entry = ioapic_read_entry(apic, pin);
527 if (entry.delivery_mode == APIC_DELIVERY_MODE_SMI)
531 * Make sure the entry is masked and re-read the contents to check
532 * if it is a level triggered pin and if the remote-IRR is set.
536 ioapic_write_entry(apic, pin, entry);
537 entry = ioapic_read_entry(apic, pin);
544 * Make sure the trigger mode is set to level. Explicit EOI
545 * doesn't clear the remote-IRR if the trigger mode is not
548 if (!entry.is_level) {
549 entry.is_level = true;
550 ioapic_write_entry(apic, pin, entry);
552 raw_spin_lock_irqsave(&ioapic_lock, flags);
553 __eoi_ioapic_pin(apic, pin, entry.vector);
554 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
558 * Clear the rest of the bits in the IO-APIC RTE except for the mask
561 ioapic_mask_entry(apic, pin);
562 entry = ioapic_read_entry(apic, pin);
564 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
565 mpc_ioapic_id(apic), pin);
568 void clear_IO_APIC (void)
572 for_each_ioapic_pin(apic, pin)
573 clear_IO_APIC_pin(apic, pin);
578 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
579 * specific CPU-side IRQs.
583 static int pirq_entries[MAX_PIRQS] = {
584 [0 ... MAX_PIRQS - 1] = -1
587 static int __init ioapic_pirq_setup(char *str)
590 int ints[MAX_PIRQS+1];
592 get_options(str, ARRAY_SIZE(ints), ints);
594 apic_printk(APIC_VERBOSE, KERN_INFO
595 "PIRQ redirection, working around broken MP-BIOS.\n");
597 if (ints[0] < MAX_PIRQS)
600 for (i = 0; i < max; i++) {
601 apic_printk(APIC_VERBOSE, KERN_DEBUG
602 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
604 * PIRQs are mapped upside down, usually.
606 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
611 __setup("pirq=", ioapic_pirq_setup);
612 #endif /* CONFIG_X86_32 */
615 * Saves all the IO-APIC RTE's
617 int save_ioapic_entries(void)
622 for_each_ioapic(apic) {
623 if (!ioapics[apic].saved_registers) {
628 for_each_pin(apic, pin)
629 ioapics[apic].saved_registers[pin] =
630 ioapic_read_entry(apic, pin);
637 * Mask all IO APIC entries.
639 void mask_ioapic_entries(void)
643 for_each_ioapic(apic) {
644 if (!ioapics[apic].saved_registers)
647 for_each_pin(apic, pin) {
648 struct IO_APIC_route_entry entry;
650 entry = ioapics[apic].saved_registers[pin];
653 ioapic_write_entry(apic, pin, entry);
660 * Restore IO APIC entries which was saved in the ioapic structure.
662 int restore_ioapic_entries(void)
666 for_each_ioapic(apic) {
667 if (!ioapics[apic].saved_registers)
670 for_each_pin(apic, pin)
671 ioapic_write_entry(apic, pin,
672 ioapics[apic].saved_registers[pin]);
678 * Find the IRQ entry number of a certain pin.
680 static int find_irq_entry(int ioapic_idx, int pin, int type)
684 for (i = 0; i < mp_irq_entries; i++)
685 if (mp_irqs[i].irqtype == type &&
686 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
687 mp_irqs[i].dstapic == MP_APIC_ALL) &&
688 mp_irqs[i].dstirq == pin)
695 * Find the pin to which IRQ[irq] (ISA) is connected
697 static int __init find_isa_irq_pin(int irq, int type)
701 for (i = 0; i < mp_irq_entries; i++) {
702 int lbus = mp_irqs[i].srcbus;
704 if (test_bit(lbus, mp_bus_not_pci) &&
705 (mp_irqs[i].irqtype == type) &&
706 (mp_irqs[i].srcbusirq == irq))
708 return mp_irqs[i].dstirq;
713 static int __init find_isa_irq_apic(int irq, int type)
717 for (i = 0; i < mp_irq_entries; i++) {
718 int lbus = mp_irqs[i].srcbus;
720 if (test_bit(lbus, mp_bus_not_pci) &&
721 (mp_irqs[i].irqtype == type) &&
722 (mp_irqs[i].srcbusirq == irq))
726 if (i < mp_irq_entries) {
729 for_each_ioapic(ioapic_idx)
730 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
737 static bool irq_active_low(int idx)
739 int bus = mp_irqs[idx].srcbus;
742 * Determine IRQ line polarity (high active or low active):
744 switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
745 case MP_IRQPOL_DEFAULT:
747 * Conforms to spec, ie. bus-type dependent polarity. PCI
748 * defaults to low active. [E]ISA defaults to high active.
750 return !test_bit(bus, mp_bus_not_pci);
751 case MP_IRQPOL_ACTIVE_HIGH:
753 case MP_IRQPOL_RESERVED:
754 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
756 case MP_IRQPOL_ACTIVE_LOW:
757 default: /* Pointless default required due to do gcc stupidity */
764 * EISA Edge/Level control register, ELCR
766 static bool EISA_ELCR(unsigned int irq)
768 if (irq < nr_legacy_irqs()) {
769 unsigned int port = PIC_ELCR1 + (irq >> 3);
770 return (inb(port) >> (irq & 7)) & 1;
772 apic_printk(APIC_VERBOSE, KERN_INFO
773 "Broken MPtable reports ISA irq %d\n", irq);
778 * EISA interrupts are always active high and can be edge or level
779 * triggered depending on the ELCR value. If an interrupt is listed as
780 * EISA conforming in the MP table, that means its trigger type must be
781 * read in from the ELCR.
783 static bool eisa_irq_is_level(int idx, int bus, bool level)
785 switch (mp_bus_id_to_type[bus]) {
790 return EISA_ELCR(mp_irqs[idx].srcbusirq);
792 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
796 static inline int eisa_irq_is_level(int idx, int bus, bool level)
802 static bool irq_is_level(int idx)
804 int bus = mp_irqs[idx].srcbus;
808 * Determine IRQ trigger mode (edge or level sensitive):
810 switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
811 case MP_IRQTRIG_DEFAULT:
813 * Conforms to spec, ie. bus-type dependent trigger
814 * mode. PCI defaults to level, ISA to edge.
816 level = !test_bit(bus, mp_bus_not_pci);
817 /* Take EISA into account */
818 return eisa_irq_is_level(idx, bus, level);
819 case MP_IRQTRIG_EDGE:
821 case MP_IRQTRIG_RESERVED:
822 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
824 case MP_IRQTRIG_LEVEL:
825 default: /* Pointless default required due to do gcc stupidity */
830 static int __acpi_get_override_irq(u32 gsi, bool *trigger, bool *polarity)
832 int ioapic, pin, idx;
834 if (skip_ioapic_setup)
837 ioapic = mp_find_ioapic(gsi);
841 pin = mp_find_ioapic_pin(ioapic, gsi);
845 idx = find_irq_entry(ioapic, pin, mp_INT);
849 *trigger = irq_is_level(idx);
850 *polarity = irq_active_low(idx);
855 int acpi_get_override_irq(u32 gsi, int *is_level, int *active_low)
857 *is_level = *active_low = 0;
858 return __acpi_get_override_irq(gsi, (bool *)is_level,
863 void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
864 int trigger, int polarity)
866 init_irq_alloc_info(info, NULL);
867 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
868 info->ioapic.node = node;
869 info->ioapic.is_level = trigger;
870 info->ioapic.active_low = polarity;
871 info->ioapic.valid = 1;
874 static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
875 struct irq_alloc_info *src,
876 u32 gsi, int ioapic_idx, int pin)
880 copy_irq_alloc_info(dst, src);
881 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
882 dst->devid = mpc_ioapic_id(ioapic_idx);
883 dst->ioapic.pin = pin;
884 dst->ioapic.valid = 1;
885 if (src && src->ioapic.valid) {
886 dst->ioapic.node = src->ioapic.node;
887 dst->ioapic.is_level = src->ioapic.is_level;
888 dst->ioapic.active_low = src->ioapic.active_low;
890 dst->ioapic.node = NUMA_NO_NODE;
891 if (__acpi_get_override_irq(gsi, &level, &pol_low) >= 0) {
892 dst->ioapic.is_level = level;
893 dst->ioapic.active_low = pol_low;
896 * PCI interrupts are always active low level
899 dst->ioapic.is_level = true;
900 dst->ioapic.active_low = true;
905 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
907 return (info && info->ioapic.valid) ? info->ioapic.node : NUMA_NO_NODE;
910 static void mp_register_handler(unsigned int irq, bool level)
912 irq_flow_handler_t hdl;
916 irq_set_status_flags(irq, IRQ_LEVEL);
919 irq_clear_status_flags(irq, IRQ_LEVEL);
923 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
924 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
927 static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
929 struct mp_chip_data *data = irq_get_chip_data(irq);
932 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
933 * and polarity attributes. So allow the first user to reprogram the
934 * pin with real trigger and polarity attributes.
936 if (irq < nr_legacy_irqs() && data->count == 1) {
937 if (info->ioapic.is_level != data->is_level)
938 mp_register_handler(irq, info->ioapic.is_level);
939 data->entry.is_level = data->is_level = info->ioapic.is_level;
940 data->entry.active_low = data->active_low = info->ioapic.active_low;
943 return data->is_level == info->ioapic.is_level &&
944 data->active_low == info->ioapic.active_low;
947 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
948 struct irq_alloc_info *info)
952 int type = ioapics[ioapic].irqdomain_cfg.type;
955 case IOAPIC_DOMAIN_LEGACY:
957 * Dynamically allocate IRQ number for non-ISA IRQs in the first
958 * 16 GSIs on some weird platforms.
960 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
962 legacy = mp_is_legacy_irq(irq);
964 case IOAPIC_DOMAIN_STRICT:
967 case IOAPIC_DOMAIN_DYNAMIC:
970 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
974 return __irq_domain_alloc_irqs(domain, irq, 1,
975 ioapic_alloc_attr_node(info),
980 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
981 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
982 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
983 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
984 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
985 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
986 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
987 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
989 static int alloc_isa_irq_from_domain(struct irq_domain *domain,
990 int irq, int ioapic, int pin,
991 struct irq_alloc_info *info)
993 struct mp_chip_data *data;
994 struct irq_data *irq_data = irq_get_irq_data(irq);
995 int node = ioapic_alloc_attr_node(info);
998 * Legacy ISA IRQ has already been allocated, just add pin to
999 * the pin list associated with this IRQ and program the IOAPIC
1000 * entry. The IOAPIC entry
1002 if (irq_data && irq_data->parent_data) {
1003 if (!mp_check_pin_attr(irq, info))
1005 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1009 info->flags |= X86_IRQ_ALLOC_LEGACY;
1010 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1013 irq_data = irq_domain_get_irq_data(domain, irq);
1014 data = irq_data->chip_data;
1015 data->isa_irq = true;
1022 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1023 unsigned int flags, struct irq_alloc_info *info)
1026 bool legacy = false;
1027 struct irq_alloc_info tmp;
1028 struct mp_chip_data *data;
1029 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1034 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1035 irq = mp_irqs[idx].srcbusirq;
1036 legacy = mp_is_legacy_irq(irq);
1038 * IRQ2 is unusable for historical reasons on systems which
1039 * have a legacy PIC. See the comment vs. IRQ2 further down.
1041 * If this gets removed at some point then the related code
1042 * in lapic_assign_system_vectors() needs to be adjusted as
1045 if (legacy && irq == PIC_CASCADE_IR)
1049 mutex_lock(&ioapic_mutex);
1050 if (!(flags & IOAPIC_MAP_ALLOC)) {
1052 irq = irq_find_mapping(domain, pin);
1057 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1059 irq = alloc_isa_irq_from_domain(domain, irq,
1061 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1062 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1063 else if (!mp_check_pin_attr(irq, &tmp))
1066 data = irq_get_chip_data(irq);
1070 mutex_unlock(&ioapic_mutex);
1075 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1077 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1080 * Debugging check, we are in big trouble if this message pops up!
1082 if (mp_irqs[idx].dstirq != pin)
1083 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1085 #ifdef CONFIG_X86_32
1087 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1089 if ((pin >= 16) && (pin <= 23)) {
1090 if (pirq_entries[pin-16] != -1) {
1091 if (!pirq_entries[pin-16]) {
1092 apic_printk(APIC_VERBOSE, KERN_DEBUG
1093 "disabling PIRQ%d\n", pin-16);
1095 int irq = pirq_entries[pin-16];
1096 apic_printk(APIC_VERBOSE, KERN_DEBUG
1097 "using PIRQ%d -> IRQ %d\n",
1105 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1108 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1110 int ioapic, pin, idx;
1112 ioapic = mp_find_ioapic(gsi);
1116 pin = mp_find_ioapic_pin(ioapic, gsi);
1117 idx = find_irq_entry(ioapic, pin, mp_INT);
1118 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1121 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1124 void mp_unmap_irq(int irq)
1126 struct irq_data *irq_data = irq_get_irq_data(irq);
1127 struct mp_chip_data *data;
1129 if (!irq_data || !irq_data->domain)
1132 data = irq_data->chip_data;
1133 if (!data || data->isa_irq)
1136 mutex_lock(&ioapic_mutex);
1137 if (--data->count == 0)
1138 irq_domain_free_irqs(irq, 1);
1139 mutex_unlock(&ioapic_mutex);
1143 * Find a specific PCI IRQ entry.
1144 * Not an __init, possibly needed by modules
1146 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1148 int irq, i, best_ioapic = -1, best_idx = -1;
1150 apic_printk(APIC_DEBUG,
1151 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1153 if (test_bit(bus, mp_bus_not_pci)) {
1154 apic_printk(APIC_VERBOSE,
1155 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1159 for (i = 0; i < mp_irq_entries; i++) {
1160 int lbus = mp_irqs[i].srcbus;
1161 int ioapic_idx, found = 0;
1163 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1164 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1167 for_each_ioapic(ioapic_idx)
1168 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1169 mp_irqs[i].dstapic == MP_APIC_ALL) {
1177 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1178 if (irq > 0 && !IO_APIC_IRQ(irq))
1181 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1183 best_ioapic = ioapic_idx;
1188 * Use the first all-but-pin matching entry as a
1189 * best-guess fuzzy result for broken mptables.
1193 best_ioapic = ioapic_idx;
1200 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1203 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1205 static struct irq_chip ioapic_chip, ioapic_ir_chip;
1207 static void __init setup_IO_APIC_irqs(void)
1209 unsigned int ioapic, pin;
1212 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1214 for_each_ioapic_pin(ioapic, pin) {
1215 idx = find_irq_entry(ioapic, pin, mp_INT);
1217 apic_printk(APIC_VERBOSE,
1218 KERN_DEBUG " apic %d pin %d not connected\n",
1219 mpc_ioapic_id(ioapic), pin);
1221 pin_2_irq(idx, ioapic, pin,
1222 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1226 void ioapic_zap_locks(void)
1228 raw_spin_lock_init(&ioapic_lock);
1231 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1233 struct IO_APIC_route_entry entry;
1237 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1238 for (i = 0; i <= nr_entries; i++) {
1239 entry = ioapic_read_entry(apic, i);
1240 snprintf(buf, sizeof(buf),
1241 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1243 entry.masked ? "disabled" : "enabled ",
1244 entry.is_level ? "level" : "edge ",
1245 entry.active_low ? "low " : "high",
1246 entry.vector, entry.irr, entry.delivery_status);
1247 if (entry.ir_format) {
1248 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1250 (entry.ir_index_15 << 15) | entry.ir_index_0_14,
1253 printk(KERN_DEBUG "%s, %s, D(%02X%02X), M(%1d)\n", buf,
1254 entry.dest_mode_logical ? "logical " : "physical",
1255 entry.virt_destid_8_14, entry.destid_0_7,
1256 entry.delivery_mode);
1261 static void __init print_IO_APIC(int ioapic_idx)
1263 union IO_APIC_reg_00 reg_00;
1264 union IO_APIC_reg_01 reg_01;
1265 union IO_APIC_reg_02 reg_02;
1266 union IO_APIC_reg_03 reg_03;
1267 unsigned long flags;
1269 raw_spin_lock_irqsave(&ioapic_lock, flags);
1270 reg_00.raw = io_apic_read(ioapic_idx, 0);
1271 reg_01.raw = io_apic_read(ioapic_idx, 1);
1272 if (reg_01.bits.version >= 0x10)
1273 reg_02.raw = io_apic_read(ioapic_idx, 2);
1274 if (reg_01.bits.version >= 0x20)
1275 reg_03.raw = io_apic_read(ioapic_idx, 3);
1276 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1278 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1279 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1280 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1281 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1282 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1284 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1285 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1286 reg_01.bits.entries);
1288 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1289 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1290 reg_01.bits.version);
1293 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1294 * but the value of reg_02 is read as the previous read register
1295 * value, so ignore it if reg_02 == reg_01.
1297 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1298 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1299 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1303 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1304 * or reg_03, but the value of reg_0[23] is read as the previous read
1305 * register value, so ignore it if reg_03 == reg_0[12].
1307 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1308 reg_03.raw != reg_01.raw) {
1309 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1310 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1313 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1314 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1317 void __init print_IO_APICs(void)
1322 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1323 for_each_ioapic(ioapic_idx)
1324 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1325 mpc_ioapic_id(ioapic_idx),
1326 ioapics[ioapic_idx].nr_registers);
1329 * We are a bit conservative about what we expect. We have to
1330 * know about every hardware change ASAP.
1332 printk(KERN_INFO "testing the IO APIC.......................\n");
1334 for_each_ioapic(ioapic_idx)
1335 print_IO_APIC(ioapic_idx);
1337 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1338 for_each_active_irq(irq) {
1339 struct irq_pin_list *entry;
1340 struct irq_chip *chip;
1341 struct mp_chip_data *data;
1343 chip = irq_get_chip(irq);
1344 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1346 data = irq_get_chip_data(irq);
1349 if (list_empty(&data->irq_2_pin))
1352 printk(KERN_DEBUG "IRQ%d ", irq);
1353 for_each_irq_pin(entry, data->irq_2_pin)
1354 pr_cont("-> %d:%d", entry->apic, entry->pin);
1358 printk(KERN_INFO ".................................... done.\n");
1361 /* Where if anywhere is the i8259 connect in external int mode */
1362 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1364 void __init enable_IO_APIC(void)
1366 int i8259_apic, i8259_pin;
1369 if (skip_ioapic_setup)
1372 if (!nr_legacy_irqs() || !nr_ioapics)
1375 for_each_ioapic_pin(apic, pin) {
1376 /* See if any of the pins is in ExtINT mode */
1377 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1379 /* If the interrupt line is enabled and in ExtInt mode
1380 * I have found the pin where the i8259 is connected.
1382 if (!entry.masked &&
1383 entry.delivery_mode == APIC_DELIVERY_MODE_EXTINT) {
1384 ioapic_i8259.apic = apic;
1385 ioapic_i8259.pin = pin;
1390 /* Look to see what if the MP table has reported the ExtINT */
1391 /* If we could not find the appropriate pin by looking at the ioapic
1392 * the i8259 probably is not connected the ioapic but give the
1393 * mptable a chance anyway.
1395 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1396 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1397 /* Trust the MP table if nothing is setup in the hardware */
1398 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1399 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1400 ioapic_i8259.pin = i8259_pin;
1401 ioapic_i8259.apic = i8259_apic;
1403 /* Complain if the MP table and the hardware disagree */
1404 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1405 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1407 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1411 * Do not trust the IO-APIC being empty at bootup
1416 void native_restore_boot_irq_mode(void)
1419 * If the i8259 is routed through an IOAPIC
1420 * Put that IOAPIC in virtual wire mode
1421 * so legacy interrupts can be delivered.
1423 if (ioapic_i8259.pin != -1) {
1424 struct IO_APIC_route_entry entry;
1425 u32 apic_id = read_apic_id();
1427 memset(&entry, 0, sizeof(entry));
1428 entry.masked = false;
1429 entry.is_level = false;
1430 entry.active_low = false;
1431 entry.dest_mode_logical = false;
1432 entry.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
1433 entry.destid_0_7 = apic_id & 0xFF;
1434 entry.virt_destid_8_14 = apic_id >> 8;
1437 * Add it to the IO-APIC irq-routing table:
1439 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1442 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1443 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1446 void restore_boot_irq_mode(void)
1448 if (!nr_legacy_irqs())
1451 x86_apic_ops.restore();
1454 #ifdef CONFIG_X86_32
1456 * function to set the IO-APIC physical IDs based on the
1457 * values stored in the MPC table.
1459 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1461 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1463 union IO_APIC_reg_00 reg_00;
1464 physid_mask_t phys_id_present_map;
1467 unsigned char old_id;
1468 unsigned long flags;
1471 * This is broken; anything with a real cpu count has to
1472 * circumvent this idiocy regardless.
1474 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1477 * Set the IOAPIC ID to the value stored in the MPC table.
1479 for_each_ioapic(ioapic_idx) {
1480 /* Read the register 0 value */
1481 raw_spin_lock_irqsave(&ioapic_lock, flags);
1482 reg_00.raw = io_apic_read(ioapic_idx, 0);
1483 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1485 old_id = mpc_ioapic_id(ioapic_idx);
1487 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1488 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1489 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1490 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1492 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1496 * Sanity check, is the ID really free? Every APIC in a
1497 * system must have a unique ID or we get lots of nice
1498 * 'stuck on smp_invalidate_needed IPI wait' messages.
1500 if (apic->check_apicid_used(&phys_id_present_map,
1501 mpc_ioapic_id(ioapic_idx))) {
1502 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1503 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1504 for (i = 0; i < get_physical_broadcast(); i++)
1505 if (!physid_isset(i, phys_id_present_map))
1507 if (i >= get_physical_broadcast())
1508 panic("Max APIC ID exceeded!\n");
1509 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1511 physid_set(i, phys_id_present_map);
1512 ioapics[ioapic_idx].mp_config.apicid = i;
1515 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1517 apic_printk(APIC_VERBOSE, "Setting %d in the "
1518 "phys_id_present_map\n",
1519 mpc_ioapic_id(ioapic_idx));
1520 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1524 * We need to adjust the IRQ routing table
1525 * if the ID changed.
1527 if (old_id != mpc_ioapic_id(ioapic_idx))
1528 for (i = 0; i < mp_irq_entries; i++)
1529 if (mp_irqs[i].dstapic == old_id)
1531 = mpc_ioapic_id(ioapic_idx);
1534 * Update the ID register according to the right value
1535 * from the MPC table if they are different.
1537 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1540 apic_printk(APIC_VERBOSE, KERN_INFO
1541 "...changing IO-APIC physical APIC ID to %d ...",
1542 mpc_ioapic_id(ioapic_idx));
1544 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1545 raw_spin_lock_irqsave(&ioapic_lock, flags);
1546 io_apic_write(ioapic_idx, 0, reg_00.raw);
1547 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1552 raw_spin_lock_irqsave(&ioapic_lock, flags);
1553 reg_00.raw = io_apic_read(ioapic_idx, 0);
1554 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1555 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1556 pr_cont("could not set ID!\n");
1558 apic_printk(APIC_VERBOSE, " ok.\n");
1562 void __init setup_ioapic_ids_from_mpc(void)
1568 * Don't check I/O APIC IDs for xAPIC systems. They have
1569 * no meaning without the serial APIC bus.
1571 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1572 || APIC_XAPIC(boot_cpu_apic_version))
1574 setup_ioapic_ids_from_mpc_nocheck();
1578 int no_timer_check __initdata;
1580 static int __init notimercheck(char *s)
1585 __setup("no_timer_check", notimercheck);
1587 static void __init delay_with_tsc(void)
1589 unsigned long long start, now;
1590 unsigned long end = jiffies + 4;
1595 * We don't know the TSC frequency yet, but waiting for
1596 * 40000000000/HZ TSC cycles is safe:
1597 * 4 GHz == 10 jiffies
1598 * 1 GHz == 40 jiffies
1603 } while ((now - start) < 40000000000ULL / HZ &&
1604 time_before_eq(jiffies, end));
1607 static void __init delay_without_tsc(void)
1609 unsigned long end = jiffies + 4;
1613 * We don't know any frequency yet, but waiting for
1614 * 40940000000/HZ cycles is safe:
1615 * 4 GHz == 10 jiffies
1616 * 1 GHz == 40 jiffies
1617 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1620 __delay(((1U << band++) * 10000000UL) / HZ);
1621 } while (band < 12 && time_before_eq(jiffies, end));
1625 * There is a nasty bug in some older SMP boards, their mptable lies
1626 * about the timer IRQ. We do the following to work around the situation:
1628 * - timer IRQ defaults to IO-APIC IRQ
1629 * - if this function detects that timer IRQs are defunct, then we fall
1630 * back to ISA timer IRQs
1632 static int __init timer_irq_works(void)
1634 unsigned long t1 = jiffies;
1640 if (boot_cpu_has(X86_FEATURE_TSC))
1643 delay_without_tsc();
1646 * Expect a few ticks at least, to be sure some possible
1647 * glue logic does not lock up after one or two first
1648 * ticks in a non-ExtINT mode. Also the local APIC
1649 * might have cached one ExtINT interrupt. Finally, at
1650 * least one tick may be lost due to delays.
1653 local_irq_disable();
1655 /* Did jiffies advance? */
1656 return time_after(jiffies, t1 + 4);
1660 * In the SMP+IOAPIC case it might happen that there are an unspecified
1661 * number of pending IRQ events unhandled. These cases are very rare,
1662 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1663 * better to do it this way as thus we do not have to be aware of
1664 * 'pending' interrupts in the IRQ path, except at this point.
1667 * Edge triggered needs to resend any interrupt
1668 * that was delayed but this is now handled in the device
1673 * Starting up a edge-triggered IO-APIC interrupt is
1674 * nasty - we need to make sure that we get the edge.
1675 * If it is already asserted for some reason, we need
1676 * return 1 to indicate that is was pending.
1678 * This is not complete - we should be able to fake
1679 * an edge even if it isn't on the 8259A...
1681 static unsigned int startup_ioapic_irq(struct irq_data *data)
1683 int was_pending = 0, irq = data->irq;
1684 unsigned long flags;
1686 raw_spin_lock_irqsave(&ioapic_lock, flags);
1687 if (irq < nr_legacy_irqs()) {
1688 legacy_pic->mask(irq);
1689 if (legacy_pic->irq_pending(irq))
1692 __unmask_ioapic(data->chip_data);
1693 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1698 atomic_t irq_mis_count;
1700 #ifdef CONFIG_GENERIC_PENDING_IRQ
1701 static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1703 struct irq_pin_list *entry;
1704 unsigned long flags;
1706 raw_spin_lock_irqsave(&ioapic_lock, flags);
1707 for_each_irq_pin(entry, data->irq_2_pin) {
1708 struct IO_APIC_route_entry e;
1712 e.w1 = io_apic_read(entry->apic, 0x10 + pin*2);
1713 /* Is the remote IRR bit set? */
1715 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1719 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1724 static inline bool ioapic_prepare_move(struct irq_data *data)
1726 /* If we are moving the IRQ we need to mask it */
1727 if (unlikely(irqd_is_setaffinity_pending(data))) {
1728 if (!irqd_irq_masked(data))
1729 mask_ioapic_irq(data);
1735 static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1737 if (unlikely(moveit)) {
1738 /* Only migrate the irq if the ack has been received.
1740 * On rare occasions the broadcast level triggered ack gets
1741 * delayed going to ioapics, and if we reprogram the
1742 * vector while Remote IRR is still set the irq will never
1745 * To prevent this scenario we read the Remote IRR bit
1746 * of the ioapic. This has two effects.
1747 * - On any sane system the read of the ioapic will
1748 * flush writes (and acks) going to the ioapic from
1750 * - We get to see if the ACK has actually been delivered.
1752 * Based on failed experiments of reprogramming the
1753 * ioapic entry from outside of irq context starting
1754 * with masking the ioapic entry and then polling until
1755 * Remote IRR was clear before reprogramming the
1756 * ioapic I don't trust the Remote IRR bit to be
1757 * completely accurate.
1759 * However there appears to be no other way to plug
1760 * this race, so if the Remote IRR bit is not
1761 * accurate and is causing problems then it is a hardware bug
1762 * and you can go talk to the chipset vendor about it.
1764 if (!io_apic_level_ack_pending(data->chip_data))
1765 irq_move_masked_irq(data);
1766 /* If the IRQ is masked in the core, leave it: */
1767 if (!irqd_irq_masked(data))
1768 unmask_ioapic_irq(data);
1772 static inline bool ioapic_prepare_move(struct irq_data *data)
1776 static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1781 static void ioapic_ack_level(struct irq_data *irq_data)
1783 struct irq_cfg *cfg = irqd_cfg(irq_data);
1788 irq_complete_move(cfg);
1789 moveit = ioapic_prepare_move(irq_data);
1792 * It appears there is an erratum which affects at least version 0x11
1793 * of I/O APIC (that's the 82093AA and cores integrated into various
1794 * chipsets). Under certain conditions a level-triggered interrupt is
1795 * erroneously delivered as edge-triggered one but the respective IRR
1796 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1797 * message but it will never arrive and further interrupts are blocked
1798 * from the source. The exact reason is so far unknown, but the
1799 * phenomenon was observed when two consecutive interrupt requests
1800 * from a given source get delivered to the same CPU and the source is
1801 * temporarily disabled in between.
1803 * A workaround is to simulate an EOI message manually. We achieve it
1804 * by setting the trigger mode to edge and then to level when the edge
1805 * trigger mode gets detected in the TMR of a local APIC for a
1806 * level-triggered interrupt. We mask the source for the time of the
1807 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1808 * The idea is from Manfred Spraul. --macro
1810 * Also in the case when cpu goes offline, fixup_irqs() will forward
1811 * any unhandled interrupt on the offlined cpu to the new cpu
1812 * destination that is handling the corresponding interrupt. This
1813 * interrupt forwarding is done via IPI's. Hence, in this case also
1814 * level-triggered io-apic interrupt will be seen as an edge
1815 * interrupt in the IRR. And we can't rely on the cpu's EOI
1816 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1817 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1818 * supporting EOI register, we do an explicit EOI to clear the
1819 * remote IRR and on IO-APIC's which don't have an EOI register,
1820 * we use the above logic (mask+edge followed by unmask+level) from
1821 * Manfred Spraul to clear the remote IRR.
1824 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1827 * We must acknowledge the irq before we move it or the acknowledge will
1828 * not propagate properly.
1833 * Tail end of clearing remote IRR bit (either by delivering the EOI
1834 * message via io-apic EOI register write or simulating it using
1835 * mask+edge followed by unmask+level logic) manually when the
1836 * level triggered interrupt is seen as the edge triggered interrupt
1839 if (!(v & (1 << (i & 0x1f)))) {
1840 atomic_inc(&irq_mis_count);
1841 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1844 ioapic_finish_move(irq_data, moveit);
1847 static void ioapic_ir_ack_level(struct irq_data *irq_data)
1849 struct mp_chip_data *data = irq_data->chip_data;
1852 * Intr-remapping uses pin number as the virtual vector
1853 * in the RTE. Actual vector is programmed in
1854 * intr-remapping table entry. Hence for the io-apic
1855 * EOI we use the pin number.
1857 apic_ack_irq(irq_data);
1858 eoi_ioapic_pin(data->entry.vector, data);
1862 * The I/OAPIC is just a device for generating MSI messages from legacy
1863 * interrupt pins. Various fields of the RTE translate into bits of the
1864 * resulting MSI which had a historical meaning.
1866 * With interrupt remapping, many of those bits have different meanings
1867 * in the underlying MSI, but the way that the I/OAPIC transforms them
1868 * from its RTE to the MSI message is the same. This function allows
1869 * the parent IRQ domain to compose the MSI message, then takes the
1870 * relevant bits to put them in the appropriate places in the RTE in
1871 * order to generate that message when the IRQ happens.
1873 * The setup here relies on a preconfigured route entry (is_level,
1874 * active_low, masked) because the parent domain is merely composing the
1875 * generic message routing information which is used for the MSI.
1877 static void ioapic_setup_msg_from_msi(struct irq_data *irq_data,
1878 struct IO_APIC_route_entry *entry)
1882 /* Let the parent domain compose the MSI message */
1883 irq_chip_compose_msi_msg(irq_data, &msg);
1887 * - DMAR/IR: 8bit subhandle (ioapic.pin)
1888 * - AMD/IR: 8bit IRTE index
1890 entry->vector = msg.arch_data.vector;
1891 /* Delivery mode (for DMAR/IR all 0) */
1892 entry->delivery_mode = msg.arch_data.delivery_mode;
1893 /* Destination mode or DMAR/IR index bit 15 */
1894 entry->dest_mode_logical = msg.arch_addr_lo.dest_mode_logical;
1895 /* DMAR/IR: 1, 0 for all other modes */
1896 entry->ir_format = msg.arch_addr_lo.dmar_format;
1898 * - DMAR/IR: index bit 0-14.
1900 * - Virt: If the host supports x2apic without a virtualized IR
1901 * unit then bit 0-6 of dmar_index_0_14 are providing bit
1902 * 8-14 of the destination id.
1904 * All other modes have bit 0-6 of dmar_index_0_14 cleared and the
1905 * topmost 8 bits are destination id bit 0-7 (entry::destid_0_7).
1907 entry->ir_index_0_14 = msg.arch_addr_lo.dmar_index_0_14;
1910 static void ioapic_configure_entry(struct irq_data *irqd)
1912 struct mp_chip_data *mpd = irqd->chip_data;
1913 struct irq_pin_list *entry;
1915 ioapic_setup_msg_from_msi(irqd, &mpd->entry);
1917 for_each_irq_pin(entry, mpd->irq_2_pin)
1918 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1921 static int ioapic_set_affinity(struct irq_data *irq_data,
1922 const struct cpumask *mask, bool force)
1924 struct irq_data *parent = irq_data->parent_data;
1925 unsigned long flags;
1928 ret = parent->chip->irq_set_affinity(parent, mask, force);
1929 raw_spin_lock_irqsave(&ioapic_lock, flags);
1930 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1931 ioapic_configure_entry(irq_data);
1932 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1938 * Interrupt shutdown masks the ioapic pin, but the interrupt might already
1939 * be in flight, but not yet serviced by the target CPU. That means
1940 * __synchronize_hardirq() would return and claim that everything is calmed
1941 * down. So free_irq() would proceed and deactivate the interrupt and free
1944 * Once the target CPU comes around to service it it will find a cleared
1945 * vector and complain. While the spurious interrupt is harmless, the full
1946 * release of resources might prevent the interrupt from being acknowledged
1947 * which keeps the hardware in a weird state.
1949 * Verify that the corresponding Remote-IRR bits are clear.
1951 static int ioapic_irq_get_chip_state(struct irq_data *irqd,
1952 enum irqchip_irq_state which,
1955 struct mp_chip_data *mcd = irqd->chip_data;
1956 struct IO_APIC_route_entry rentry;
1957 struct irq_pin_list *p;
1959 if (which != IRQCHIP_STATE_ACTIVE)
1963 raw_spin_lock(&ioapic_lock);
1964 for_each_irq_pin(p, mcd->irq_2_pin) {
1965 rentry = __ioapic_read_entry(p->apic, p->pin);
1967 * The remote IRR is only valid in level trigger mode. It's
1968 * meaning is undefined for edge triggered interrupts and
1969 * irrelevant because the IO-APIC treats them as fire and
1972 if (rentry.irr && rentry.is_level) {
1977 raw_spin_unlock(&ioapic_lock);
1981 static struct irq_chip ioapic_chip __read_mostly = {
1983 .irq_startup = startup_ioapic_irq,
1984 .irq_mask = mask_ioapic_irq,
1985 .irq_unmask = unmask_ioapic_irq,
1986 .irq_ack = irq_chip_ack_parent,
1987 .irq_eoi = ioapic_ack_level,
1988 .irq_set_affinity = ioapic_set_affinity,
1989 .irq_retrigger = irq_chip_retrigger_hierarchy,
1990 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1991 .flags = IRQCHIP_SKIP_SET_WAKE |
1992 IRQCHIP_AFFINITY_PRE_STARTUP,
1995 static struct irq_chip ioapic_ir_chip __read_mostly = {
1996 .name = "IR-IO-APIC",
1997 .irq_startup = startup_ioapic_irq,
1998 .irq_mask = mask_ioapic_irq,
1999 .irq_unmask = unmask_ioapic_irq,
2000 .irq_ack = irq_chip_ack_parent,
2001 .irq_eoi = ioapic_ir_ack_level,
2002 .irq_set_affinity = ioapic_set_affinity,
2003 .irq_retrigger = irq_chip_retrigger_hierarchy,
2004 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
2005 .flags = IRQCHIP_SKIP_SET_WAKE |
2006 IRQCHIP_AFFINITY_PRE_STARTUP,
2009 static inline void init_IO_APIC_traps(void)
2011 struct irq_cfg *cfg;
2014 for_each_active_irq(irq) {
2016 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2018 * Hmm.. We don't have an entry for this,
2019 * so default to an old-fashioned 8259
2020 * interrupt if we can..
2022 if (irq < nr_legacy_irqs())
2023 legacy_pic->make_irq(irq);
2025 /* Strange. Oh, well.. */
2026 irq_set_chip(irq, &no_irq_chip);
2032 * The local APIC irq-chip implementation:
2035 static void mask_lapic_irq(struct irq_data *data)
2039 v = apic_read(APIC_LVT0);
2040 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2043 static void unmask_lapic_irq(struct irq_data *data)
2047 v = apic_read(APIC_LVT0);
2048 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2051 static void ack_lapic_irq(struct irq_data *data)
2056 static struct irq_chip lapic_chip __read_mostly = {
2057 .name = "local-APIC",
2058 .irq_mask = mask_lapic_irq,
2059 .irq_unmask = unmask_lapic_irq,
2060 .irq_ack = ack_lapic_irq,
2063 static void lapic_register_intr(int irq)
2065 irq_clear_status_flags(irq, IRQ_LEVEL);
2066 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2071 * This looks a bit hackish but it's about the only one way of sending
2072 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2073 * not support the ExtINT mode, unfortunately. We need to send these
2074 * cycles as some i82489DX-based boards have glue logic that keeps the
2075 * 8259A interrupt line asserted until INTA. --macro
2077 static inline void __init unlock_ExtINT_logic(void)
2080 struct IO_APIC_route_entry entry0, entry1;
2081 unsigned char save_control, save_freq_select;
2084 pin = find_isa_irq_pin(8, mp_INT);
2089 apic = find_isa_irq_apic(8, mp_INT);
2095 entry0 = ioapic_read_entry(apic, pin);
2096 clear_IO_APIC_pin(apic, pin);
2098 apic_id = hard_smp_processor_id();
2099 memset(&entry1, 0, sizeof(entry1));
2101 entry1.dest_mode_logical = true;
2102 entry1.masked = false;
2103 entry1.destid_0_7 = apic_id & 0xFF;
2104 entry1.virt_destid_8_14 = apic_id >> 8;
2105 entry1.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
2106 entry1.active_low = entry0.active_low;
2107 entry1.is_level = false;
2110 ioapic_write_entry(apic, pin, entry1);
2112 save_control = CMOS_READ(RTC_CONTROL);
2113 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2114 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2116 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2121 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2125 CMOS_WRITE(save_control, RTC_CONTROL);
2126 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2127 clear_IO_APIC_pin(apic, pin);
2129 ioapic_write_entry(apic, pin, entry0);
2132 static int disable_timer_pin_1 __initdata;
2133 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2134 static int __init disable_timer_pin_setup(char *arg)
2136 disable_timer_pin_1 = 1;
2139 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2141 static int mp_alloc_timer_irq(int ioapic, int pin)
2144 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2147 struct irq_alloc_info info;
2149 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2150 info.devid = mpc_ioapic_id(ioapic);
2151 info.ioapic.pin = pin;
2152 mutex_lock(&ioapic_mutex);
2153 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2154 mutex_unlock(&ioapic_mutex);
2161 * This code may look a bit paranoid, but it's supposed to cooperate with
2162 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2163 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2164 * fanatically on his truly buggy board.
2166 * FIXME: really need to revamp this for all platforms.
2168 static inline void __init check_timer(void)
2170 struct irq_data *irq_data = irq_get_irq_data(0);
2171 struct mp_chip_data *data = irq_data->chip_data;
2172 struct irq_cfg *cfg = irqd_cfg(irq_data);
2173 int node = cpu_to_node(0);
2174 int apic1, pin1, apic2, pin2;
2177 if (!global_clock_event)
2180 local_irq_disable();
2183 * get/set the timer IRQ vector:
2185 legacy_pic->mask(0);
2188 * As IRQ0 is to be enabled in the 8259A, the virtual
2189 * wire has to be disabled in the local APIC. Also
2190 * timer interrupts need to be acknowledged manually in
2191 * the 8259A for the i82489DX when using the NMI
2192 * watchdog as that APIC treats NMIs as level-triggered.
2193 * The AEOI mode will finish them in the 8259A
2196 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2197 legacy_pic->init(1);
2199 pin1 = find_isa_irq_pin(0, mp_INT);
2200 apic1 = find_isa_irq_apic(0, mp_INT);
2201 pin2 = ioapic_i8259.pin;
2202 apic2 = ioapic_i8259.apic;
2204 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2205 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2206 cfg->vector, apic1, pin1, apic2, pin2);
2209 * Some BIOS writers are clueless and report the ExtINTA
2210 * I/O APIC input from the cascaded 8259A as the timer
2211 * interrupt input. So just in case, if only one pin
2212 * was found above, try it both directly and through the
2216 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2220 } else if (pin2 == -1) {
2226 /* Ok, does IRQ0 through the IOAPIC work? */
2228 mp_alloc_timer_irq(apic1, pin1);
2231 * for edge trigger, it's already unmasked,
2232 * so only need to unmask if it is level-trigger
2233 * do we really have level trigger timer?
2235 int idx = find_irq_entry(apic1, pin1, mp_INT);
2237 if (idx != -1 && irq_is_level(idx))
2238 unmask_ioapic_irq(irq_get_irq_data(0));
2240 irq_domain_deactivate_irq(irq_data);
2241 irq_domain_activate_irq(irq_data, false);
2242 if (timer_irq_works()) {
2243 if (disable_timer_pin_1 > 0)
2244 clear_IO_APIC_pin(0, pin1);
2247 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2248 clear_IO_APIC_pin(apic1, pin1);
2250 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2251 "8254 timer not connected to IO-APIC\n");
2253 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2254 "(IRQ0) through the 8259A ...\n");
2255 apic_printk(APIC_QUIET, KERN_INFO
2256 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2258 * legacy devices should be connected to IO APIC #0
2260 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2261 irq_domain_deactivate_irq(irq_data);
2262 irq_domain_activate_irq(irq_data, false);
2263 legacy_pic->unmask(0);
2264 if (timer_irq_works()) {
2265 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2269 * Cleanup, just in case ...
2271 legacy_pic->mask(0);
2272 clear_IO_APIC_pin(apic2, pin2);
2273 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2276 apic_printk(APIC_QUIET, KERN_INFO
2277 "...trying to set up timer as Virtual Wire IRQ...\n");
2279 lapic_register_intr(0);
2280 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2281 legacy_pic->unmask(0);
2283 if (timer_irq_works()) {
2284 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2287 legacy_pic->mask(0);
2288 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2289 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2291 apic_printk(APIC_QUIET, KERN_INFO
2292 "...trying to set up timer as ExtINT IRQ...\n");
2294 legacy_pic->init(0);
2295 legacy_pic->make_irq(0);
2296 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2297 legacy_pic->unmask(0);
2299 unlock_ExtINT_logic();
2301 if (timer_irq_works()) {
2302 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2305 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2306 if (apic_is_x2apic_enabled())
2307 apic_printk(APIC_QUIET, KERN_INFO
2308 "Perhaps problem with the pre-enabled x2apic mode\n"
2309 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2310 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2311 "report. Then try booting with the 'noapic' option.\n");
2317 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2318 * to devices. However there may be an I/O APIC pin available for
2319 * this interrupt regardless. The pin may be left unconnected, but
2320 * typically it will be reused as an ExtINT cascade interrupt for
2321 * the master 8259A. In the MPS case such a pin will normally be
2322 * reported as an ExtINT interrupt in the MP table. With ACPI
2323 * there is no provision for ExtINT interrupts, and in the absence
2324 * of an override it would be treated as an ordinary ISA I/O APIC
2325 * interrupt, that is edge-triggered and unmasked by default. We
2326 * used to do this, but it caused problems on some systems because
2327 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2328 * the same ExtINT cascade interrupt to drive the local APIC of the
2329 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2330 * the I/O APIC in all cases now. No actual device should request
2331 * it anyway. --macro
2333 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2335 static int mp_irqdomain_create(int ioapic)
2337 struct irq_domain *parent;
2338 int hwirqs = mp_ioapic_pin_count(ioapic);
2339 struct ioapic *ip = &ioapics[ioapic];
2340 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2341 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2342 struct fwnode_handle *fn;
2343 struct irq_fwspec fwspec;
2345 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2348 /* Handle device tree enumerated APICs proper */
2350 fn = of_node_to_fwnode(cfg->dev);
2352 fn = irq_domain_alloc_named_id_fwnode("IO-APIC", mpc_ioapic_id(ioapic));
2358 fwspec.param_count = 1;
2359 fwspec.param[0] = mpc_ioapic_id(ioapic);
2361 parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_ANY);
2364 irq_domain_free_fwnode(fn);
2368 ip->irqdomain = irq_domain_create_hierarchy(parent, 0, hwirqs, fn, cfg->ops,
2369 (void *)(long)ioapic);
2370 if (!ip->irqdomain) {
2371 /* Release fw handle if it was allocated above */
2373 irq_domain_free_fwnode(fn);
2377 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2378 cfg->type == IOAPIC_DOMAIN_STRICT)
2379 ioapic_dynirq_base = max(ioapic_dynirq_base,
2380 gsi_cfg->gsi_end + 1);
2385 static void ioapic_destroy_irqdomain(int idx)
2387 struct ioapic_domain_cfg *cfg = &ioapics[idx].irqdomain_cfg;
2388 struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode;
2390 if (ioapics[idx].irqdomain) {
2391 irq_domain_remove(ioapics[idx].irqdomain);
2393 irq_domain_free_fwnode(fn);
2394 ioapics[idx].irqdomain = NULL;
2398 void __init setup_IO_APIC(void)
2402 if (skip_ioapic_setup || !nr_ioapics)
2405 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2407 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2408 for_each_ioapic(ioapic)
2409 BUG_ON(mp_irqdomain_create(ioapic));
2412 * Set up IO-APIC IRQ routing.
2414 x86_init.mpparse.setup_ioapic_ids();
2417 setup_IO_APIC_irqs();
2418 init_IO_APIC_traps();
2419 if (nr_legacy_irqs())
2422 ioapic_initialized = 1;
2425 static void resume_ioapic_id(int ioapic_idx)
2427 unsigned long flags;
2428 union IO_APIC_reg_00 reg_00;
2430 raw_spin_lock_irqsave(&ioapic_lock, flags);
2431 reg_00.raw = io_apic_read(ioapic_idx, 0);
2432 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2433 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2434 io_apic_write(ioapic_idx, 0, reg_00.raw);
2436 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2439 static void ioapic_resume(void)
2443 for_each_ioapic_reverse(ioapic_idx)
2444 resume_ioapic_id(ioapic_idx);
2446 restore_ioapic_entries();
2449 static struct syscore_ops ioapic_syscore_ops = {
2450 .suspend = save_ioapic_entries,
2451 .resume = ioapic_resume,
2454 static int __init ioapic_init_ops(void)
2456 register_syscore_ops(&ioapic_syscore_ops);
2461 device_initcall(ioapic_init_ops);
2463 static int io_apic_get_redir_entries(int ioapic)
2465 union IO_APIC_reg_01 reg_01;
2466 unsigned long flags;
2468 raw_spin_lock_irqsave(&ioapic_lock, flags);
2469 reg_01.raw = io_apic_read(ioapic, 1);
2470 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2472 /* The register returns the maximum index redir index
2473 * supported, which is one less than the total number of redir
2476 return reg_01.bits.entries + 1;
2479 unsigned int arch_dynirq_lower_bound(unsigned int from)
2484 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2485 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2487 ret = ioapic_dynirq_base ? : gsi_top;
2490 * For DT enabled machines ioapic_dynirq_base is irrelevant and
2491 * always 0. gsi_top can be 0 if there is no IO/APIC registered.
2492 * 0 is an invalid interrupt number for dynamic allocations. Return
2495 return ret ? : from;
2498 #ifdef CONFIG_X86_32
2499 static int io_apic_get_unique_id(int ioapic, int apic_id)
2501 union IO_APIC_reg_00 reg_00;
2502 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2504 unsigned long flags;
2508 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2509 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2510 * supports up to 16 on one shared APIC bus.
2512 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2513 * advantage of new APIC bus architecture.
2516 if (physids_empty(apic_id_map))
2517 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2519 raw_spin_lock_irqsave(&ioapic_lock, flags);
2520 reg_00.raw = io_apic_read(ioapic, 0);
2521 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2523 if (apic_id >= get_physical_broadcast()) {
2524 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2525 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2526 apic_id = reg_00.bits.ID;
2530 * Every APIC in a system must have a unique ID or we get lots of nice
2531 * 'stuck on smp_invalidate_needed IPI wait' messages.
2533 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2535 for (i = 0; i < get_physical_broadcast(); i++) {
2536 if (!apic->check_apicid_used(&apic_id_map, i))
2540 if (i == get_physical_broadcast())
2541 panic("Max apic_id exceeded!\n");
2543 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2544 "trying %d\n", ioapic, apic_id, i);
2549 apic->apicid_to_cpu_present(apic_id, &tmp);
2550 physids_or(apic_id_map, apic_id_map, tmp);
2552 if (reg_00.bits.ID != apic_id) {
2553 reg_00.bits.ID = apic_id;
2555 raw_spin_lock_irqsave(&ioapic_lock, flags);
2556 io_apic_write(ioapic, 0, reg_00.raw);
2557 reg_00.raw = io_apic_read(ioapic, 0);
2558 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2561 if (reg_00.bits.ID != apic_id) {
2562 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2568 apic_printk(APIC_VERBOSE, KERN_INFO
2569 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2574 static u8 io_apic_unique_id(int idx, u8 id)
2576 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2577 !APIC_XAPIC(boot_cpu_apic_version))
2578 return io_apic_get_unique_id(idx, id);
2583 static u8 io_apic_unique_id(int idx, u8 id)
2585 union IO_APIC_reg_00 reg_00;
2586 DECLARE_BITMAP(used, 256);
2587 unsigned long flags;
2591 bitmap_zero(used, 256);
2593 __set_bit(mpc_ioapic_id(i), used);
2595 /* Hand out the requested id if available */
2596 if (!test_bit(id, used))
2600 * Read the current id from the ioapic and keep it if
2603 raw_spin_lock_irqsave(&ioapic_lock, flags);
2604 reg_00.raw = io_apic_read(idx, 0);
2605 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2606 new_id = reg_00.bits.ID;
2607 if (!test_bit(new_id, used)) {
2608 apic_printk(APIC_VERBOSE, KERN_INFO
2609 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2615 * Get the next free id and write it to the ioapic.
2617 new_id = find_first_zero_bit(used, 256);
2618 reg_00.bits.ID = new_id;
2619 raw_spin_lock_irqsave(&ioapic_lock, flags);
2620 io_apic_write(idx, 0, reg_00.raw);
2621 reg_00.raw = io_apic_read(idx, 0);
2622 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2624 BUG_ON(reg_00.bits.ID != new_id);
2630 static int io_apic_get_version(int ioapic)
2632 union IO_APIC_reg_01 reg_01;
2633 unsigned long flags;
2635 raw_spin_lock_irqsave(&ioapic_lock, flags);
2636 reg_01.raw = io_apic_read(ioapic, 1);
2637 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2639 return reg_01.bits.version;
2643 * This function updates target affinity of IOAPIC interrupts to include
2644 * the CPUs which came online during SMP bringup.
2646 #define IOAPIC_RESOURCE_NAME_SIZE 11
2648 static struct resource *ioapic_resources;
2650 static struct resource * __init ioapic_setup_resources(void)
2653 struct resource *res;
2657 if (nr_ioapics == 0)
2660 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2663 mem = memblock_alloc(n, SMP_CACHE_BYTES);
2665 panic("%s: Failed to allocate %lu bytes\n", __func__, n);
2668 mem += sizeof(struct resource) * nr_ioapics;
2670 for_each_ioapic(i) {
2672 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2673 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2674 mem += IOAPIC_RESOURCE_NAME_SIZE;
2675 ioapics[i].iomem_res = &res[i];
2678 ioapic_resources = res;
2683 static void io_apic_set_fixmap(enum fixed_addresses idx, phys_addr_t phys)
2685 pgprot_t flags = FIXMAP_PAGE_NOCACHE;
2688 * Ensure fixmaps for IO-APIC MMIO respect memory encryption pgprot
2689 * bits, just like normal ioremap():
2691 if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) {
2692 if (x86_platform.hyper.is_private_mmio(phys))
2693 flags = pgprot_encrypted(flags);
2695 flags = pgprot_decrypted(flags);
2698 __set_fixmap(idx, phys, flags);
2701 void __init io_apic_init_mappings(void)
2703 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2704 struct resource *ioapic_res;
2707 ioapic_res = ioapic_setup_resources();
2708 for_each_ioapic(i) {
2709 if (smp_found_config) {
2710 ioapic_phys = mpc_ioapic_addr(i);
2711 #ifdef CONFIG_X86_32
2714 "WARNING: bogus zero IO-APIC "
2715 "address found in MPTABLE, "
2716 "disabling IO/APIC support!\n");
2717 smp_found_config = 0;
2718 skip_ioapic_setup = 1;
2719 goto fake_ioapic_page;
2723 #ifdef CONFIG_X86_32
2726 ioapic_phys = (unsigned long)memblock_alloc(PAGE_SIZE,
2729 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
2730 __func__, PAGE_SIZE, PAGE_SIZE);
2731 ioapic_phys = __pa(ioapic_phys);
2733 io_apic_set_fixmap(idx, ioapic_phys);
2734 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2735 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2739 ioapic_res->start = ioapic_phys;
2740 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2745 void __init ioapic_insert_resources(void)
2748 struct resource *r = ioapic_resources;
2753 "IO APIC resources couldn't be allocated.\n");
2757 for_each_ioapic(i) {
2758 insert_resource(&iomem_resource, r);
2763 int mp_find_ioapic(u32 gsi)
2767 if (nr_ioapics == 0)
2770 /* Find the IOAPIC that manages this GSI. */
2771 for_each_ioapic(i) {
2772 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2773 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2777 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2781 int mp_find_ioapic_pin(int ioapic, u32 gsi)
2783 struct mp_ioapic_gsi *gsi_cfg;
2785 if (WARN_ON(ioapic < 0))
2788 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2789 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2792 return gsi - gsi_cfg->gsi_base;
2795 static int bad_ioapic_register(int idx)
2797 union IO_APIC_reg_00 reg_00;
2798 union IO_APIC_reg_01 reg_01;
2799 union IO_APIC_reg_02 reg_02;
2801 reg_00.raw = io_apic_read(idx, 0);
2802 reg_01.raw = io_apic_read(idx, 1);
2803 reg_02.raw = io_apic_read(idx, 2);
2805 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2806 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2807 mpc_ioapic_addr(idx));
2814 static int find_free_ioapic_entry(void)
2818 for (idx = 0; idx < MAX_IO_APICS; idx++)
2819 if (ioapics[idx].nr_registers == 0)
2822 return MAX_IO_APICS;
2826 * mp_register_ioapic - Register an IOAPIC device
2827 * @id: hardware IOAPIC ID
2828 * @address: physical address of IOAPIC register area
2829 * @gsi_base: base of GSI associated with the IOAPIC
2830 * @cfg: configuration information for the IOAPIC
2832 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2833 struct ioapic_domain_cfg *cfg)
2835 bool hotplug = !!ioapic_initialized;
2836 struct mp_ioapic_gsi *gsi_cfg;
2837 int idx, ioapic, entries;
2841 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2844 for_each_ioapic(ioapic)
2845 if (ioapics[ioapic].mp_config.apicaddr == address) {
2846 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2851 idx = find_free_ioapic_entry();
2852 if (idx >= MAX_IO_APICS) {
2853 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2858 ioapics[idx].mp_config.type = MP_IOAPIC;
2859 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2860 ioapics[idx].mp_config.apicaddr = address;
2862 io_apic_set_fixmap(FIX_IO_APIC_BASE_0 + idx, address);
2863 if (bad_ioapic_register(idx)) {
2864 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2868 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2869 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2872 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2873 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2875 entries = io_apic_get_redir_entries(idx);
2876 gsi_end = gsi_base + entries - 1;
2877 for_each_ioapic(ioapic) {
2878 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2879 if ((gsi_base >= gsi_cfg->gsi_base &&
2880 gsi_base <= gsi_cfg->gsi_end) ||
2881 (gsi_end >= gsi_cfg->gsi_base &&
2882 gsi_end <= gsi_cfg->gsi_end)) {
2883 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2885 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2886 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2890 gsi_cfg = mp_ioapic_gsi_routing(idx);
2891 gsi_cfg->gsi_base = gsi_base;
2892 gsi_cfg->gsi_end = gsi_end;
2894 ioapics[idx].irqdomain = NULL;
2895 ioapics[idx].irqdomain_cfg = *cfg;
2898 * If mp_register_ioapic() is called during early boot stage when
2899 * walking ACPI/DT tables, it's too early to create irqdomain,
2900 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2903 if (mp_irqdomain_create(idx)) {
2904 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2907 alloc_ioapic_saved_registers(idx);
2910 if (gsi_cfg->gsi_end >= gsi_top)
2911 gsi_top = gsi_cfg->gsi_end + 1;
2912 if (nr_ioapics <= idx)
2913 nr_ioapics = idx + 1;
2915 /* Set nr_registers to mark entry present */
2916 ioapics[idx].nr_registers = entries;
2918 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2919 idx, mpc_ioapic_id(idx),
2920 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2921 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2926 int mp_unregister_ioapic(u32 gsi_base)
2931 for_each_ioapic(ioapic)
2932 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2937 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2941 for_each_pin(ioapic, pin) {
2942 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2943 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2944 struct mp_chip_data *data;
2947 data = irq_get_chip_data(irq);
2948 if (data && data->count) {
2949 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2956 /* Mark entry not present */
2957 ioapics[ioapic].nr_registers = 0;
2958 ioapic_destroy_irqdomain(ioapic);
2959 free_ioapic_saved_registers(ioapic);
2960 if (ioapics[ioapic].iomem_res)
2961 release_resource(ioapics[ioapic].iomem_res);
2962 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2963 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2968 int mp_ioapic_registered(u32 gsi_base)
2972 for_each_ioapic(ioapic)
2973 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2979 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2980 struct irq_alloc_info *info)
2982 if (info && info->ioapic.valid) {
2983 data->is_level = info->ioapic.is_level;
2984 data->active_low = info->ioapic.active_low;
2985 } else if (__acpi_get_override_irq(gsi, &data->is_level,
2986 &data->active_low) < 0) {
2987 /* PCI interrupts are always active low level triggered. */
2988 data->is_level = true;
2989 data->active_low = true;
2994 * Configure the I/O-APIC specific fields in the routing entry.
2996 * This is important to setup the I/O-APIC specific bits (is_level,
2997 * active_low, masked) because the underlying parent domain will only
2998 * provide the routing information and is oblivious of the I/O-APIC
3001 * The entry is just preconfigured at this point and not written into the
3002 * RTE. This happens later during activation which will fill in the actual
3003 * routing information.
3005 static void mp_preconfigure_entry(struct mp_chip_data *data)
3007 struct IO_APIC_route_entry *entry = &data->entry;
3009 memset(entry, 0, sizeof(*entry));
3010 entry->is_level = data->is_level;
3011 entry->active_low = data->active_low;
3013 * Mask level triggered irqs. Edge triggered irqs are masked
3014 * by the irq core code in case they fire.
3016 entry->masked = data->is_level;
3019 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
3020 unsigned int nr_irqs, void *arg)
3022 struct irq_alloc_info *info = arg;
3023 struct mp_chip_data *data;
3024 struct irq_data *irq_data;
3025 int ret, ioapic, pin;
3026 unsigned long flags;
3028 if (!info || nr_irqs > 1)
3030 irq_data = irq_domain_get_irq_data(domain, virq);
3034 ioapic = mp_irqdomain_ioapic_idx(domain);
3035 pin = info->ioapic.pin;
3036 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
3039 data = kzalloc(sizeof(*data), GFP_KERNEL);
3043 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
3049 INIT_LIST_HEAD(&data->irq_2_pin);
3050 irq_data->hwirq = info->ioapic.pin;
3051 irq_data->chip = (domain->parent == x86_vector_domain) ?
3052 &ioapic_chip : &ioapic_ir_chip;
3053 irq_data->chip_data = data;
3054 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
3056 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
3058 mp_preconfigure_entry(data);
3059 mp_register_handler(virq, data->is_level);
3061 local_irq_save(flags);
3062 if (virq < nr_legacy_irqs())
3063 legacy_pic->mask(virq);
3064 local_irq_restore(flags);
3066 apic_printk(APIC_VERBOSE, KERN_DEBUG
3067 "IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d Level:%i ActiveLow:%i)\n",
3068 ioapic, mpc_ioapic_id(ioapic), pin, virq,
3069 data->is_level, data->active_low);
3073 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
3074 unsigned int nr_irqs)
3076 struct irq_data *irq_data;
3077 struct mp_chip_data *data;
3079 BUG_ON(nr_irqs != 1);
3080 irq_data = irq_domain_get_irq_data(domain, virq);
3081 if (irq_data && irq_data->chip_data) {
3082 data = irq_data->chip_data;
3083 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
3084 (int)irq_data->hwirq);
3085 WARN_ON(!list_empty(&data->irq_2_pin));
3086 kfree(irq_data->chip_data);
3088 irq_domain_free_irqs_top(domain, virq, nr_irqs);
3091 int mp_irqdomain_activate(struct irq_domain *domain,
3092 struct irq_data *irq_data, bool reserve)
3094 unsigned long flags;
3096 raw_spin_lock_irqsave(&ioapic_lock, flags);
3097 ioapic_configure_entry(irq_data);
3098 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3102 void mp_irqdomain_deactivate(struct irq_domain *domain,
3103 struct irq_data *irq_data)
3105 /* It won't be called for IRQ with multiple IOAPIC pins associated */
3106 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3107 (int)irq_data->hwirq);
3110 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3112 return (int)(long)domain->host_data;
3115 const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3116 .alloc = mp_irqdomain_alloc,
3117 .free = mp_irqdomain_free,
3118 .activate = mp_irqdomain_activate,
3119 .deactivate = mp_irqdomain_deactivate,