2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/intr_remapping.h>
61 #include <asm/irq_remapping.h>
63 #include <asm/hw_irq.h>
67 #define __apicdebuginit(type) static type __init
69 #define for_each_irq_pin(entry, head) \
70 for (entry = head; entry; entry = entry->next)
72 static void __init __ioapic_init_mappings(void);
74 static unsigned int __io_apic_read (unsigned int apic, unsigned int reg);
75 static void __io_apic_write (unsigned int apic, unsigned int reg, unsigned int val);
76 static void __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val);
78 static struct io_apic_ops io_apic_ops = {
79 .init = __ioapic_init_mappings,
80 .read = __io_apic_read,
81 .write = __io_apic_write,
82 .modify = __io_apic_modify,
85 void __init set_io_apic_ops(const struct io_apic_ops *ops)
91 * Is the SiS APIC rmw bug present ?
92 * -1 = don't know, 0 = no, 1 = yes
94 int sis_apic_bug = -1;
96 static DEFINE_RAW_SPINLOCK(ioapic_lock);
97 static DEFINE_RAW_SPINLOCK(vector_lock);
99 static struct ioapic {
101 * # of IRQ routing registers
105 * Saved state during suspend/resume, or while enabling intr-remap.
107 struct IO_APIC_route_entry *saved_registers;
108 /* I/O APIC config */
109 struct mpc_ioapic mp_config;
110 /* IO APIC gsi routing info */
111 struct mp_ioapic_gsi gsi_config;
112 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
113 } ioapics[MAX_IO_APICS];
115 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
117 int mpc_ioapic_id(int ioapic_idx)
119 return ioapics[ioapic_idx].mp_config.apicid;
122 unsigned int mpc_ioapic_addr(int ioapic_idx)
124 return ioapics[ioapic_idx].mp_config.apicaddr;
127 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
129 return &ioapics[ioapic_idx].gsi_config;
134 /* The one past the highest gsi number used */
137 /* MP IRQ source entries */
138 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
140 /* # of MP IRQ source entries */
144 static int nr_irqs_gsi = NR_IRQS_LEGACY;
146 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
147 int mp_bus_id_to_type[MAX_MP_BUSSES];
150 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
152 int skip_ioapic_setup;
155 * disable_ioapic_support() - disables ioapic support at runtime
157 void disable_ioapic_support(void)
161 noioapicreroute = -1;
163 skip_ioapic_setup = 1;
166 static int __init parse_noapic(char *str)
168 /* disable IO-APIC */
169 disable_ioapic_support();
172 early_param("noapic", parse_noapic);
174 static int io_apic_setup_irq_pin(unsigned int irq, int node,
175 struct io_apic_irq_attr *attr);
177 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
178 void mp_save_irq(struct mpc_intsrc *m)
182 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
183 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
184 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
185 m->srcbusirq, m->dstapic, m->dstirq);
187 for (i = 0; i < mp_irq_entries; i++) {
188 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
192 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
193 if (++mp_irq_entries == MAX_IRQ_SOURCES)
194 panic("Max # of irq sources exceeded!!\n");
197 struct irq_pin_list {
199 struct irq_pin_list *next;
202 static struct irq_pin_list *alloc_irq_pin_list(int node)
204 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
208 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
209 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
211 int __init arch_early_irq_init(void)
216 if (!legacy_pic->nr_legacy_irqs)
219 for (i = 0; i < nr_ioapics; i++) {
220 ioapics[i].saved_registers =
221 kzalloc(sizeof(struct IO_APIC_route_entry) *
222 ioapics[i].nr_registers, GFP_KERNEL);
223 if (!ioapics[i].saved_registers)
224 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
228 count = ARRAY_SIZE(irq_cfgx);
229 node = cpu_to_node(0);
231 /* Make sure the legacy interrupts are marked in the bitmap */
232 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
234 for (i = 0; i < count; i++) {
235 irq_set_chip_data(i, &cfg[i]);
236 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
237 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
239 * For legacy IRQ's, start with assigning irq0 to irq15 to
240 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
242 if (i < legacy_pic->nr_legacy_irqs) {
243 cfg[i].vector = IRQ0_VECTOR + i;
244 cpumask_set_cpu(0, cfg[i].domain);
251 static struct irq_cfg *irq_cfg(unsigned int irq)
253 return irq_get_chip_data(irq);
256 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
260 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
263 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
265 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
269 free_cpumask_var(cfg->domain);
275 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
279 irq_set_chip_data(at, NULL);
280 free_cpumask_var(cfg->domain);
281 free_cpumask_var(cfg->old_domain);
285 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
287 int res = irq_alloc_desc_at(at, node);
293 cfg = irq_get_chip_data(at);
298 cfg = alloc_irq_cfg(at, node);
300 irq_set_chip_data(at, cfg);
306 static int alloc_irq_from(unsigned int from, int node)
308 return irq_alloc_desc_from(from, node);
311 static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
313 free_irq_cfg(at, cfg);
317 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
319 return io_apic_ops.read(apic, reg);
322 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
324 io_apic_ops.write(apic, reg, value);
327 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
329 io_apic_ops.modify(apic, reg, value);
335 unsigned int unused[3];
337 unsigned int unused2[11];
341 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
343 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
344 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
347 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
349 struct io_apic __iomem *io_apic = io_apic_base(apic);
350 writel(vector, &io_apic->eoi);
353 static unsigned int __io_apic_read(unsigned int apic, unsigned int reg)
355 struct io_apic __iomem *io_apic = io_apic_base(apic);
356 writel(reg, &io_apic->index);
357 return readl(&io_apic->data);
360 static void __io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
362 struct io_apic __iomem *io_apic = io_apic_base(apic);
364 writel(reg, &io_apic->index);
365 writel(value, &io_apic->data);
369 * Re-write a value: to be used for read-modify-write
370 * cycles where the read already set up the index register.
372 * Older SiS APIC requires we rewrite the index register
374 static void __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
376 struct io_apic __iomem *io_apic = io_apic_base(apic);
379 writel(reg, &io_apic->index);
380 writel(value, &io_apic->data);
383 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
385 struct irq_pin_list *entry;
388 raw_spin_lock_irqsave(&ioapic_lock, flags);
389 for_each_irq_pin(entry, cfg->irq_2_pin) {
394 reg = io_apic_read(entry->apic, 0x10 + pin*2);
395 /* Is the remote IRR bit set? */
396 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
397 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
401 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
407 struct { u32 w1, w2; };
408 struct IO_APIC_route_entry entry;
411 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
413 union entry_union eu;
415 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
416 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
421 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
423 union entry_union eu;
426 raw_spin_lock_irqsave(&ioapic_lock, flags);
427 eu.entry = __ioapic_read_entry(apic, pin);
428 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
434 * When we write a new IO APIC routing entry, we need to write the high
435 * word first! If the mask bit in the low word is clear, we will enable
436 * the interrupt, and we need to make sure the entry is fully populated
437 * before that happens.
439 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
441 union entry_union eu = {{0, 0}};
444 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
445 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
448 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
452 raw_spin_lock_irqsave(&ioapic_lock, flags);
453 __ioapic_write_entry(apic, pin, e);
454 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
458 * When we mask an IO APIC routing entry, we need to write the low
459 * word first, in order to set the mask bit before we change the
462 static void ioapic_mask_entry(int apic, int pin)
465 union entry_union eu = { .entry.mask = 1 };
467 raw_spin_lock_irqsave(&ioapic_lock, flags);
468 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
469 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
470 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
474 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
475 * shared ISA-space IRQs, so we have to support them. We are super
476 * fast in the common case, and fast for shared ISA-space IRQs.
478 static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
480 struct irq_pin_list **last, *entry;
482 /* don't allow duplicates */
483 last = &cfg->irq_2_pin;
484 for_each_irq_pin(entry, cfg->irq_2_pin) {
485 if (entry->apic == apic && entry->pin == pin)
490 entry = alloc_irq_pin_list(node);
492 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
503 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
505 if (__add_pin_to_irq_node(cfg, node, apic, pin))
506 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
510 * Reroute an IRQ to a different pin.
512 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
513 int oldapic, int oldpin,
514 int newapic, int newpin)
516 struct irq_pin_list *entry;
518 for_each_irq_pin(entry, cfg->irq_2_pin) {
519 if (entry->apic == oldapic && entry->pin == oldpin) {
520 entry->apic = newapic;
522 /* every one is different, right? */
527 /* old apic/pin didn't exist, so just add new ones */
528 add_pin_to_irq_node(cfg, node, newapic, newpin);
531 static void __io_apic_modify_irq(struct irq_pin_list *entry,
532 int mask_and, int mask_or,
533 void (*final)(struct irq_pin_list *entry))
535 unsigned int reg, pin;
538 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
541 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
546 static void io_apic_modify_irq(struct irq_cfg *cfg,
547 int mask_and, int mask_or,
548 void (*final)(struct irq_pin_list *entry))
550 struct irq_pin_list *entry;
552 for_each_irq_pin(entry, cfg->irq_2_pin)
553 __io_apic_modify_irq(entry, mask_and, mask_or, final);
556 static void io_apic_sync(struct irq_pin_list *entry)
559 * Synchronize the IO-APIC and the CPU by doing
560 * a dummy read from the IO-APIC
562 struct io_apic __iomem *io_apic;
564 io_apic = io_apic_base(entry->apic);
565 readl(&io_apic->data);
568 static void mask_ioapic(struct irq_cfg *cfg)
572 raw_spin_lock_irqsave(&ioapic_lock, flags);
573 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
574 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
577 static void mask_ioapic_irq(struct irq_data *data)
579 mask_ioapic(data->chip_data);
582 static void __unmask_ioapic(struct irq_cfg *cfg)
584 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
587 static void unmask_ioapic(struct irq_cfg *cfg)
591 raw_spin_lock_irqsave(&ioapic_lock, flags);
592 __unmask_ioapic(cfg);
593 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
596 static void unmask_ioapic_irq(struct irq_data *data)
598 unmask_ioapic(data->chip_data);
602 * IO-APIC versions below 0x20 don't support EOI register.
603 * For the record, here is the information about various versions:
605 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
606 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
609 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
610 * version as 0x2. This is an error with documentation and these ICH chips
611 * use io-apic's of version 0x20.
613 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
614 * Otherwise, we simulate the EOI message manually by changing the trigger
615 * mode to edge and then back to level, with RTE being masked during this.
617 static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg)
619 if (mpc_ioapic_ver(apic) >= 0x20) {
621 * Intr-remapping uses pin number as the virtual vector
622 * in the RTE. Actual vector is programmed in
623 * intr-remapping table entry. Hence for the io-apic
624 * EOI we use the pin number.
626 if (cfg && irq_remapped(cfg))
627 io_apic_eoi(apic, pin);
629 io_apic_eoi(apic, vector);
631 struct IO_APIC_route_entry entry, entry1;
633 entry = entry1 = __ioapic_read_entry(apic, pin);
636 * Mask the entry and change the trigger mode to edge.
639 entry1.trigger = IOAPIC_EDGE;
641 __ioapic_write_entry(apic, pin, entry1);
644 * Restore the previous level triggered entry.
646 __ioapic_write_entry(apic, pin, entry);
650 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
652 struct irq_pin_list *entry;
655 raw_spin_lock_irqsave(&ioapic_lock, flags);
656 for_each_irq_pin(entry, cfg->irq_2_pin)
657 __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg);
658 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
661 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
663 struct IO_APIC_route_entry entry;
665 /* Check delivery_mode to be sure we're not clearing an SMI pin */
666 entry = ioapic_read_entry(apic, pin);
667 if (entry.delivery_mode == dest_SMI)
671 * Make sure the entry is masked and re-read the contents to check
672 * if it is a level triggered pin and if the remote-IRR is set.
676 ioapic_write_entry(apic, pin, entry);
677 entry = ioapic_read_entry(apic, pin);
684 * Make sure the trigger mode is set to level. Explicit EOI
685 * doesn't clear the remote-IRR if the trigger mode is not
688 if (!entry.trigger) {
689 entry.trigger = IOAPIC_LEVEL;
690 ioapic_write_entry(apic, pin, entry);
693 raw_spin_lock_irqsave(&ioapic_lock, flags);
694 __eoi_ioapic_pin(apic, pin, entry.vector, NULL);
695 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
699 * Clear the rest of the bits in the IO-APIC RTE except for the mask
702 ioapic_mask_entry(apic, pin);
703 entry = ioapic_read_entry(apic, pin);
705 printk(KERN_ERR "Unable to reset IRR for apic: %d, pin :%d\n",
706 mpc_ioapic_id(apic), pin);
709 static void clear_IO_APIC (void)
713 for (apic = 0; apic < nr_ioapics; apic++)
714 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
715 clear_IO_APIC_pin(apic, pin);
720 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
721 * specific CPU-side IRQs.
725 static int pirq_entries[MAX_PIRQS] = {
726 [0 ... MAX_PIRQS - 1] = -1
729 static int __init ioapic_pirq_setup(char *str)
732 int ints[MAX_PIRQS+1];
734 get_options(str, ARRAY_SIZE(ints), ints);
736 apic_printk(APIC_VERBOSE, KERN_INFO
737 "PIRQ redirection, working around broken MP-BIOS.\n");
739 if (ints[0] < MAX_PIRQS)
742 for (i = 0; i < max; i++) {
743 apic_printk(APIC_VERBOSE, KERN_DEBUG
744 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
746 * PIRQs are mapped upside down, usually.
748 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
753 __setup("pirq=", ioapic_pirq_setup);
754 #endif /* CONFIG_X86_32 */
757 * Saves all the IO-APIC RTE's
759 int save_ioapic_entries(void)
764 for (apic = 0; apic < nr_ioapics; apic++) {
765 if (!ioapics[apic].saved_registers) {
770 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
771 ioapics[apic].saved_registers[pin] =
772 ioapic_read_entry(apic, pin);
779 * Mask all IO APIC entries.
781 void mask_ioapic_entries(void)
785 for (apic = 0; apic < nr_ioapics; apic++) {
786 if (!ioapics[apic].saved_registers)
789 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
790 struct IO_APIC_route_entry entry;
792 entry = ioapics[apic].saved_registers[pin];
795 ioapic_write_entry(apic, pin, entry);
802 * Restore IO APIC entries which was saved in the ioapic structure.
804 int restore_ioapic_entries(void)
808 for (apic = 0; apic < nr_ioapics; apic++) {
809 if (!ioapics[apic].saved_registers)
812 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
813 ioapic_write_entry(apic, pin,
814 ioapics[apic].saved_registers[pin]);
820 * Find the IRQ entry number of a certain pin.
822 static int find_irq_entry(int ioapic_idx, int pin, int type)
826 for (i = 0; i < mp_irq_entries; i++)
827 if (mp_irqs[i].irqtype == type &&
828 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
829 mp_irqs[i].dstapic == MP_APIC_ALL) &&
830 mp_irqs[i].dstirq == pin)
837 * Find the pin to which IRQ[irq] (ISA) is connected
839 static int __init find_isa_irq_pin(int irq, int type)
843 for (i = 0; i < mp_irq_entries; i++) {
844 int lbus = mp_irqs[i].srcbus;
846 if (test_bit(lbus, mp_bus_not_pci) &&
847 (mp_irqs[i].irqtype == type) &&
848 (mp_irqs[i].srcbusirq == irq))
850 return mp_irqs[i].dstirq;
855 static int __init find_isa_irq_apic(int irq, int type)
859 for (i = 0; i < mp_irq_entries; i++) {
860 int lbus = mp_irqs[i].srcbus;
862 if (test_bit(lbus, mp_bus_not_pci) &&
863 (mp_irqs[i].irqtype == type) &&
864 (mp_irqs[i].srcbusirq == irq))
868 if (i < mp_irq_entries) {
871 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
872 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
879 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
881 * EISA Edge/Level control register, ELCR
883 static int EISA_ELCR(unsigned int irq)
885 if (irq < legacy_pic->nr_legacy_irqs) {
886 unsigned int port = 0x4d0 + (irq >> 3);
887 return (inb(port) >> (irq & 7)) & 1;
889 apic_printk(APIC_VERBOSE, KERN_INFO
890 "Broken MPtable reports ISA irq %d\n", irq);
896 /* ISA interrupts are always polarity zero edge triggered,
897 * when listed as conforming in the MP table. */
899 #define default_ISA_trigger(idx) (0)
900 #define default_ISA_polarity(idx) (0)
902 /* EISA interrupts are always polarity zero and can be edge or level
903 * trigger depending on the ELCR value. If an interrupt is listed as
904 * EISA conforming in the MP table, that means its trigger type must
905 * be read in from the ELCR */
907 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
908 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
910 /* PCI interrupts are always polarity one level triggered,
911 * when listed as conforming in the MP table. */
913 #define default_PCI_trigger(idx) (1)
914 #define default_PCI_polarity(idx) (1)
916 /* MCA interrupts are always polarity zero level triggered,
917 * when listed as conforming in the MP table. */
919 #define default_MCA_trigger(idx) (1)
920 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
922 static int irq_polarity(int idx)
924 int bus = mp_irqs[idx].srcbus;
928 * Determine IRQ line polarity (high active or low active):
930 switch (mp_irqs[idx].irqflag & 3)
932 case 0: /* conforms, ie. bus-type dependent polarity */
933 if (test_bit(bus, mp_bus_not_pci))
934 polarity = default_ISA_polarity(idx);
936 polarity = default_PCI_polarity(idx);
938 case 1: /* high active */
943 case 2: /* reserved */
945 printk(KERN_WARNING "broken BIOS!!\n");
949 case 3: /* low active */
954 default: /* invalid */
956 printk(KERN_WARNING "broken BIOS!!\n");
964 static int irq_trigger(int idx)
966 int bus = mp_irqs[idx].srcbus;
970 * Determine IRQ trigger mode (edge or level sensitive):
972 switch ((mp_irqs[idx].irqflag>>2) & 3)
974 case 0: /* conforms, ie. bus-type dependent */
975 if (test_bit(bus, mp_bus_not_pci))
976 trigger = default_ISA_trigger(idx);
978 trigger = default_PCI_trigger(idx);
979 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
980 switch (mp_bus_id_to_type[bus]) {
981 case MP_BUS_ISA: /* ISA pin */
983 /* set before the switch */
986 case MP_BUS_EISA: /* EISA pin */
988 trigger = default_EISA_trigger(idx);
991 case MP_BUS_PCI: /* PCI pin */
993 /* set before the switch */
996 case MP_BUS_MCA: /* MCA pin */
998 trigger = default_MCA_trigger(idx);
1003 printk(KERN_WARNING "broken BIOS!!\n");
1015 case 2: /* reserved */
1017 printk(KERN_WARNING "broken BIOS!!\n");
1026 default: /* invalid */
1028 printk(KERN_WARNING "broken BIOS!!\n");
1036 static int pin_2_irq(int idx, int apic, int pin)
1039 int bus = mp_irqs[idx].srcbus;
1040 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
1043 * Debugging check, we are in big trouble if this message pops up!
1045 if (mp_irqs[idx].dstirq != pin)
1046 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1048 if (test_bit(bus, mp_bus_not_pci)) {
1049 irq = mp_irqs[idx].srcbusirq;
1051 u32 gsi = gsi_cfg->gsi_base + pin;
1053 if (gsi >= NR_IRQS_LEGACY)
1056 irq = gsi_top + gsi;
1059 #ifdef CONFIG_X86_32
1061 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1063 if ((pin >= 16) && (pin <= 23)) {
1064 if (pirq_entries[pin-16] != -1) {
1065 if (!pirq_entries[pin-16]) {
1066 apic_printk(APIC_VERBOSE, KERN_DEBUG
1067 "disabling PIRQ%d\n", pin-16);
1069 irq = pirq_entries[pin-16];
1070 apic_printk(APIC_VERBOSE, KERN_DEBUG
1071 "using PIRQ%d -> IRQ %d\n",
1082 * Find a specific PCI IRQ entry.
1083 * Not an __init, possibly needed by modules
1085 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1086 struct io_apic_irq_attr *irq_attr)
1088 int ioapic_idx, i, best_guess = -1;
1090 apic_printk(APIC_DEBUG,
1091 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1093 if (test_bit(bus, mp_bus_not_pci)) {
1094 apic_printk(APIC_VERBOSE,
1095 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1098 for (i = 0; i < mp_irq_entries; i++) {
1099 int lbus = mp_irqs[i].srcbus;
1101 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1102 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1103 mp_irqs[i].dstapic == MP_APIC_ALL)
1106 if (!test_bit(lbus, mp_bus_not_pci) &&
1107 !mp_irqs[i].irqtype &&
1109 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1110 int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
1112 if (!(ioapic_idx || IO_APIC_IRQ(irq)))
1115 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1116 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1123 * Use the first all-but-pin matching entry as a
1124 * best-guess fuzzy result for broken mptables.
1126 if (best_guess < 0) {
1127 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1137 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1139 void lock_vector_lock(void)
1141 /* Used to the online set of cpus does not change
1142 * during assign_irq_vector.
1144 raw_spin_lock(&vector_lock);
1147 void unlock_vector_lock(void)
1149 raw_spin_unlock(&vector_lock);
1153 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1156 * NOTE! The local APIC isn't very good at handling
1157 * multiple interrupts at the same interrupt level.
1158 * As the interrupt level is determined by taking the
1159 * vector number and shifting that right by 4, we
1160 * want to spread these out a bit so that they don't
1161 * all fall in the same interrupt level.
1163 * Also, we've got to be careful not to trash gate
1164 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1166 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1167 static int current_offset = VECTOR_OFFSET_START % 8;
1168 unsigned int old_vector;
1170 cpumask_var_t tmp_mask;
1172 if (cfg->move_in_progress)
1175 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1178 old_vector = cfg->vector;
1180 cpumask_and(tmp_mask, mask, cpu_online_mask);
1181 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1182 if (!cpumask_empty(tmp_mask)) {
1183 free_cpumask_var(tmp_mask);
1188 /* Only try and allocate irqs on cpus that are present */
1190 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1194 apic->vector_allocation_domain(cpu, tmp_mask);
1196 vector = current_vector;
1197 offset = current_offset;
1200 if (vector >= first_system_vector) {
1201 /* If out of vectors on large boxen, must share them. */
1202 offset = (offset + 1) % 8;
1203 vector = FIRST_EXTERNAL_VECTOR + offset;
1205 if (unlikely(current_vector == vector))
1208 if (test_bit(vector, used_vectors))
1211 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1212 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1215 current_vector = vector;
1216 current_offset = offset;
1218 cfg->move_in_progress = 1;
1219 cpumask_copy(cfg->old_domain, cfg->domain);
1221 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1222 per_cpu(vector_irq, new_cpu)[vector] = irq;
1223 cfg->vector = vector;
1224 cpumask_copy(cfg->domain, tmp_mask);
1228 free_cpumask_var(tmp_mask);
1232 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1235 unsigned long flags;
1237 raw_spin_lock_irqsave(&vector_lock, flags);
1238 err = __assign_irq_vector(irq, cfg, mask);
1239 raw_spin_unlock_irqrestore(&vector_lock, flags);
1243 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1247 BUG_ON(!cfg->vector);
1249 vector = cfg->vector;
1250 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1251 per_cpu(vector_irq, cpu)[vector] = -1;
1254 cpumask_clear(cfg->domain);
1256 if (likely(!cfg->move_in_progress))
1258 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1259 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1261 if (per_cpu(vector_irq, cpu)[vector] != irq)
1263 per_cpu(vector_irq, cpu)[vector] = -1;
1267 cfg->move_in_progress = 0;
1270 void __setup_vector_irq(int cpu)
1272 /* Initialize vector_irq on a new cpu */
1274 struct irq_cfg *cfg;
1277 * vector_lock will make sure that we don't run into irq vector
1278 * assignments that might be happening on another cpu in parallel,
1279 * while we setup our initial vector to irq mappings.
1281 raw_spin_lock(&vector_lock);
1282 /* Mark the inuse vectors */
1283 for_each_active_irq(irq) {
1284 cfg = irq_get_chip_data(irq);
1288 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1289 * will be part of the irq_cfg's domain.
1291 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1292 cpumask_set_cpu(cpu, cfg->domain);
1294 if (!cpumask_test_cpu(cpu, cfg->domain))
1296 vector = cfg->vector;
1297 per_cpu(vector_irq, cpu)[vector] = irq;
1299 /* Mark the free vectors */
1300 for (vector = 0; vector < NR_VECTORS; ++vector) {
1301 irq = per_cpu(vector_irq, cpu)[vector];
1306 if (!cpumask_test_cpu(cpu, cfg->domain))
1307 per_cpu(vector_irq, cpu)[vector] = -1;
1309 raw_spin_unlock(&vector_lock);
1312 static struct irq_chip ioapic_chip;
1314 #ifdef CONFIG_X86_32
1315 static inline int IO_APIC_irq_trigger(int irq)
1319 for (apic = 0; apic < nr_ioapics; apic++) {
1320 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1321 idx = find_irq_entry(apic, pin, mp_INT);
1322 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1323 return irq_trigger(idx);
1327 * nonexistent IRQs are edge default
1332 static inline int IO_APIC_irq_trigger(int irq)
1338 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1339 unsigned long trigger)
1341 struct irq_chip *chip = &ioapic_chip;
1342 irq_flow_handler_t hdl;
1345 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1346 trigger == IOAPIC_LEVEL) {
1347 irq_set_status_flags(irq, IRQ_LEVEL);
1350 irq_clear_status_flags(irq, IRQ_LEVEL);
1354 if (irq_remapped(cfg)) {
1355 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1356 irq_remap_modify_chip_defaults(chip);
1357 fasteoi = trigger != 0;
1360 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1361 irq_set_chip_and_handler_name(irq, chip, hdl,
1362 fasteoi ? "fasteoi" : "edge");
1366 static int setup_ir_ioapic_entry(int irq,
1367 struct IR_IO_APIC_route_entry *entry,
1368 unsigned int destination, int vector,
1369 struct io_apic_irq_attr *attr)
1373 int ioapic_id = mpc_ioapic_id(attr->ioapic);
1374 struct intel_iommu *iommu = map_ioapic_to_ir(ioapic_id);
1377 pr_warn("No mapping iommu for ioapic %d\n", ioapic_id);
1381 index = alloc_irte(iommu, irq, 1);
1383 pr_warn("Failed to allocate IRTE for ioapic %d\n", ioapic_id);
1387 prepare_irte(&irte, vector, destination);
1389 /* Set source-id of interrupt request */
1390 set_ioapic_sid(&irte, ioapic_id);
1392 modify_irte(irq, &irte);
1394 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
1395 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
1396 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
1397 "Avail:%X Vector:%02X Dest:%08X "
1398 "SID:%04X SQ:%X SVT:%X)\n",
1399 attr->ioapic, irte.present, irte.fpd, irte.dst_mode,
1400 irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
1401 irte.avail, irte.vector, irte.dest_id,
1402 irte.sid, irte.sq, irte.svt);
1404 memset(entry, 0, sizeof(*entry));
1406 entry->index2 = (index >> 15) & 0x1;
1409 entry->index = (index & 0x7fff);
1411 * IO-APIC RTE will be configured with virtual vector.
1412 * irq handler will do the explicit EOI to the io-apic.
1414 entry->vector = attr->ioapic_pin;
1415 entry->mask = 0; /* enable IRQ */
1416 entry->trigger = attr->trigger;
1417 entry->polarity = attr->polarity;
1419 /* Mask level triggered irqs.
1420 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1428 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1429 unsigned int destination, int vector,
1430 struct io_apic_irq_attr *attr)
1432 if (intr_remapping_enabled)
1433 return setup_ir_ioapic_entry(irq,
1434 (struct IR_IO_APIC_route_entry *)entry,
1435 destination, vector, attr);
1437 memset(entry, 0, sizeof(*entry));
1439 entry->delivery_mode = apic->irq_delivery_mode;
1440 entry->dest_mode = apic->irq_dest_mode;
1441 entry->dest = destination;
1442 entry->vector = vector;
1443 entry->mask = 0; /* enable IRQ */
1444 entry->trigger = attr->trigger;
1445 entry->polarity = attr->polarity;
1448 * Mask level triggered irqs.
1449 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1457 static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1458 struct io_apic_irq_attr *attr)
1460 struct IO_APIC_route_entry entry;
1463 if (!IO_APIC_IRQ(irq))
1466 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1467 * controllers like 8259. Now that IO-APIC can handle this irq, update
1470 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1471 apic->vector_allocation_domain(0, cfg->domain);
1473 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1476 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1478 apic_printk(APIC_VERBOSE,KERN_DEBUG
1479 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1480 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1481 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1482 cfg->vector, irq, attr->trigger, attr->polarity, dest);
1484 if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) {
1485 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1486 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1487 __clear_irq_vector(irq, cfg);
1492 ioapic_register_intr(irq, cfg, attr->trigger);
1493 if (irq < legacy_pic->nr_legacy_irqs)
1494 legacy_pic->mask(irq);
1496 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1499 static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
1504 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1505 mpc_ioapic_id(ioapic_idx), pin);
1509 static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
1511 int idx, node = cpu_to_node(0);
1512 struct io_apic_irq_attr attr;
1513 unsigned int pin, irq;
1515 for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
1516 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1517 if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
1520 irq = pin_2_irq(idx, ioapic_idx, pin);
1522 if ((ioapic_idx > 0) && (irq > 16))
1526 * Skip the timer IRQ if there's a quirk handler
1527 * installed and if it returns 1:
1529 if (apic->multi_timer_check &&
1530 apic->multi_timer_check(ioapic_idx, irq))
1533 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1536 io_apic_setup_irq_pin(irq, node, &attr);
1540 static void __init setup_IO_APIC_irqs(void)
1542 unsigned int ioapic_idx;
1544 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1546 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1547 __io_apic_setup_irqs(ioapic_idx);
1551 * for the gsit that is not in first ioapic
1552 * but could not use acpi_register_gsi()
1553 * like some special sci in IBM x3330
1555 void setup_IO_APIC_irq_extra(u32 gsi)
1557 int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
1558 struct io_apic_irq_attr attr;
1561 * Convert 'gsi' to 'ioapic.pin'.
1563 ioapic_idx = mp_find_ioapic(gsi);
1567 pin = mp_find_ioapic_pin(ioapic_idx, gsi);
1568 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1572 irq = pin_2_irq(idx, ioapic_idx, pin);
1574 /* Only handle the non legacy irqs on secondary ioapics */
1575 if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
1578 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1581 io_apic_setup_irq_pin_once(irq, node, &attr);
1585 * Set up the timer pin, possibly with the 8259A-master behind.
1587 static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1588 unsigned int pin, int vector)
1590 struct IO_APIC_route_entry entry;
1592 if (intr_remapping_enabled)
1595 memset(&entry, 0, sizeof(entry));
1598 * We use logical delivery to get the timer IRQ
1601 entry.dest_mode = apic->irq_dest_mode;
1602 entry.mask = 0; /* don't mask IRQ for edge */
1603 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1604 entry.delivery_mode = apic->irq_delivery_mode;
1607 entry.vector = vector;
1610 * The timer IRQ doesn't have to know that behind the
1611 * scene we may have a 8259A-master in AEOI mode ...
1613 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1617 * Add it to the IO-APIC irq-routing table:
1619 ioapic_write_entry(ioapic_idx, pin, entry);
1622 __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
1625 union IO_APIC_reg_00 reg_00;
1626 union IO_APIC_reg_01 reg_01;
1627 union IO_APIC_reg_02 reg_02;
1628 union IO_APIC_reg_03 reg_03;
1629 unsigned long flags;
1631 raw_spin_lock_irqsave(&ioapic_lock, flags);
1632 reg_00.raw = io_apic_read(ioapic_idx, 0);
1633 reg_01.raw = io_apic_read(ioapic_idx, 1);
1634 if (reg_01.bits.version >= 0x10)
1635 reg_02.raw = io_apic_read(ioapic_idx, 2);
1636 if (reg_01.bits.version >= 0x20)
1637 reg_03.raw = io_apic_read(ioapic_idx, 3);
1638 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1641 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1642 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1643 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1644 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1645 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1647 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1648 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1649 reg_01.bits.entries);
1651 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1652 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1653 reg_01.bits.version);
1656 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1657 * but the value of reg_02 is read as the previous read register
1658 * value, so ignore it if reg_02 == reg_01.
1660 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1661 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1662 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1666 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1667 * or reg_03, but the value of reg_0[23] is read as the previous read
1668 * register value, so ignore it if reg_03 == reg_0[12].
1670 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1671 reg_03.raw != reg_01.raw) {
1672 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1673 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1676 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1678 if (intr_remapping_enabled) {
1679 printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
1680 " Pol Stat Indx2 Zero Vect:\n");
1682 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1683 " Stat Dmod Deli Vect:\n");
1686 for (i = 0; i <= reg_01.bits.entries; i++) {
1687 if (intr_remapping_enabled) {
1688 struct IO_APIC_route_entry entry;
1689 struct IR_IO_APIC_route_entry *ir_entry;
1691 entry = ioapic_read_entry(ioapic_idx, i);
1692 ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
1693 printk(KERN_DEBUG " %02x %04X ",
1697 printk("%1d %1d %1d %1d %1d "
1698 "%1d %1d %X %02X\n",
1704 ir_entry->delivery_status,
1710 struct IO_APIC_route_entry entry;
1712 entry = ioapic_read_entry(ioapic_idx, i);
1713 printk(KERN_DEBUG " %02x %02X ",
1717 printk("%1d %1d %1d %1d %1d "
1723 entry.delivery_status,
1725 entry.delivery_mode,
1732 __apicdebuginit(void) print_IO_APICs(void)
1735 struct irq_cfg *cfg;
1737 struct irq_chip *chip;
1739 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1740 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1741 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1742 mpc_ioapic_id(ioapic_idx),
1743 ioapics[ioapic_idx].nr_registers);
1746 * We are a bit conservative about what we expect. We have to
1747 * know about every hardware change ASAP.
1749 printk(KERN_INFO "testing the IO APIC.......................\n");
1751 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1752 print_IO_APIC(ioapic_idx);
1754 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1755 for_each_active_irq(irq) {
1756 struct irq_pin_list *entry;
1758 chip = irq_get_chip(irq);
1759 if (chip != &ioapic_chip)
1762 cfg = irq_get_chip_data(irq);
1765 entry = cfg->irq_2_pin;
1768 printk(KERN_DEBUG "IRQ%d ", irq);
1769 for_each_irq_pin(entry, cfg->irq_2_pin)
1770 printk("-> %d:%d", entry->apic, entry->pin);
1774 printk(KERN_INFO ".................................... done.\n");
1777 __apicdebuginit(void) print_APIC_field(int base)
1783 for (i = 0; i < 8; i++)
1784 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1786 printk(KERN_CONT "\n");
1789 __apicdebuginit(void) print_local_APIC(void *dummy)
1791 unsigned int i, v, ver, maxlvt;
1794 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1795 smp_processor_id(), hard_smp_processor_id());
1796 v = apic_read(APIC_ID);
1797 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1798 v = apic_read(APIC_LVR);
1799 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1800 ver = GET_APIC_VERSION(v);
1801 maxlvt = lapic_get_maxlvt();
1803 v = apic_read(APIC_TASKPRI);
1804 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1806 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1807 if (!APIC_XAPIC(ver)) {
1808 v = apic_read(APIC_ARBPRI);
1809 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1810 v & APIC_ARBPRI_MASK);
1812 v = apic_read(APIC_PROCPRI);
1813 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1817 * Remote read supported only in the 82489DX and local APIC for
1818 * Pentium processors.
1820 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1821 v = apic_read(APIC_RRR);
1822 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1825 v = apic_read(APIC_LDR);
1826 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1827 if (!x2apic_enabled()) {
1828 v = apic_read(APIC_DFR);
1829 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1831 v = apic_read(APIC_SPIV);
1832 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1834 printk(KERN_DEBUG "... APIC ISR field:\n");
1835 print_APIC_field(APIC_ISR);
1836 printk(KERN_DEBUG "... APIC TMR field:\n");
1837 print_APIC_field(APIC_TMR);
1838 printk(KERN_DEBUG "... APIC IRR field:\n");
1839 print_APIC_field(APIC_IRR);
1841 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1842 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1843 apic_write(APIC_ESR, 0);
1845 v = apic_read(APIC_ESR);
1846 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1849 icr = apic_icr_read();
1850 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1851 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1853 v = apic_read(APIC_LVTT);
1854 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1856 if (maxlvt > 3) { /* PC is LVT#4. */
1857 v = apic_read(APIC_LVTPC);
1858 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1860 v = apic_read(APIC_LVT0);
1861 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1862 v = apic_read(APIC_LVT1);
1863 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1865 if (maxlvt > 2) { /* ERR is LVT#3. */
1866 v = apic_read(APIC_LVTERR);
1867 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1870 v = apic_read(APIC_TMICT);
1871 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1872 v = apic_read(APIC_TMCCT);
1873 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1874 v = apic_read(APIC_TDCR);
1875 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1877 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1878 v = apic_read(APIC_EFEAT);
1879 maxlvt = (v >> 16) & 0xff;
1880 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1881 v = apic_read(APIC_ECTRL);
1882 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1883 for (i = 0; i < maxlvt; i++) {
1884 v = apic_read(APIC_EILVTn(i));
1885 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1891 __apicdebuginit(void) print_local_APICs(int maxcpu)
1899 for_each_online_cpu(cpu) {
1902 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1907 __apicdebuginit(void) print_PIC(void)
1910 unsigned long flags;
1912 if (!legacy_pic->nr_legacy_irqs)
1915 printk(KERN_DEBUG "\nprinting PIC contents\n");
1917 raw_spin_lock_irqsave(&i8259A_lock, flags);
1919 v = inb(0xa1) << 8 | inb(0x21);
1920 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1922 v = inb(0xa0) << 8 | inb(0x20);
1923 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1927 v = inb(0xa0) << 8 | inb(0x20);
1931 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1933 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1935 v = inb(0x4d1) << 8 | inb(0x4d0);
1936 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1939 static int __initdata show_lapic = 1;
1940 static __init int setup_show_lapic(char *arg)
1944 if (strcmp(arg, "all") == 0) {
1945 show_lapic = CONFIG_NR_CPUS;
1947 get_option(&arg, &num);
1954 __setup("show_lapic=", setup_show_lapic);
1956 __apicdebuginit(int) print_ICs(void)
1958 if (apic_verbosity == APIC_QUIET)
1963 /* don't print out if apic is not there */
1964 if (!cpu_has_apic && !apic_from_smp_config())
1967 print_local_APICs(show_lapic);
1973 late_initcall(print_ICs);
1976 /* Where if anywhere is the i8259 connect in external int mode */
1977 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1979 void __init enable_IO_APIC(void)
1981 int i8259_apic, i8259_pin;
1984 if (!legacy_pic->nr_legacy_irqs)
1987 for(apic = 0; apic < nr_ioapics; apic++) {
1989 /* See if any of the pins is in ExtINT mode */
1990 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1991 struct IO_APIC_route_entry entry;
1992 entry = ioapic_read_entry(apic, pin);
1994 /* If the interrupt line is enabled and in ExtInt mode
1995 * I have found the pin where the i8259 is connected.
1997 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1998 ioapic_i8259.apic = apic;
1999 ioapic_i8259.pin = pin;
2005 /* Look to see what if the MP table has reported the ExtINT */
2006 /* If we could not find the appropriate pin by looking at the ioapic
2007 * the i8259 probably is not connected the ioapic but give the
2008 * mptable a chance anyway.
2010 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
2011 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2012 /* Trust the MP table if nothing is setup in the hardware */
2013 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2014 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2015 ioapic_i8259.pin = i8259_pin;
2016 ioapic_i8259.apic = i8259_apic;
2018 /* Complain if the MP table and the hardware disagree */
2019 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2020 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2022 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2026 * Do not trust the IO-APIC being empty at bootup
2032 * Not an __init, needed by the reboot code
2034 void disable_IO_APIC(void)
2037 * Clear the IO-APIC before rebooting:
2041 if (!legacy_pic->nr_legacy_irqs)
2045 * If the i8259 is routed through an IOAPIC
2046 * Put that IOAPIC in virtual wire mode
2047 * so legacy interrupts can be delivered.
2049 * With interrupt-remapping, for now we will use virtual wire A mode,
2050 * as virtual wire B is little complex (need to configure both
2051 * IOAPIC RTE as well as interrupt-remapping table entry).
2052 * As this gets called during crash dump, keep this simple for now.
2054 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2055 struct IO_APIC_route_entry entry;
2057 memset(&entry, 0, sizeof(entry));
2058 entry.mask = 0; /* Enabled */
2059 entry.trigger = 0; /* Edge */
2061 entry.polarity = 0; /* High */
2062 entry.delivery_status = 0;
2063 entry.dest_mode = 0; /* Physical */
2064 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2066 entry.dest = read_apic_id();
2069 * Add it to the IO-APIC irq-routing table:
2071 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2075 * Use virtual wire A mode when interrupt remapping is enabled.
2077 if (cpu_has_apic || apic_from_smp_config())
2078 disconnect_bsp_APIC(!intr_remapping_enabled &&
2079 ioapic_i8259.pin != -1);
2082 #ifdef CONFIG_X86_32
2084 * function to set the IO-APIC physical IDs based on the
2085 * values stored in the MPC table.
2087 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2089 void __init setup_ioapic_ids_from_mpc_nocheck(void)
2091 union IO_APIC_reg_00 reg_00;
2092 physid_mask_t phys_id_present_map;
2095 unsigned char old_id;
2096 unsigned long flags;
2099 * This is broken; anything with a real cpu count has to
2100 * circumvent this idiocy regardless.
2102 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2105 * Set the IOAPIC ID to the value stored in the MPC table.
2107 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
2108 /* Read the register 0 value */
2109 raw_spin_lock_irqsave(&ioapic_lock, flags);
2110 reg_00.raw = io_apic_read(ioapic_idx, 0);
2111 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2113 old_id = mpc_ioapic_id(ioapic_idx);
2115 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
2116 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2117 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2118 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2120 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
2124 * Sanity check, is the ID really free? Every APIC in a
2125 * system must have a unique ID or we get lots of nice
2126 * 'stuck on smp_invalidate_needed IPI wait' messages.
2128 if (apic->check_apicid_used(&phys_id_present_map,
2129 mpc_ioapic_id(ioapic_idx))) {
2130 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2131 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2132 for (i = 0; i < get_physical_broadcast(); i++)
2133 if (!physid_isset(i, phys_id_present_map))
2135 if (i >= get_physical_broadcast())
2136 panic("Max APIC ID exceeded!\n");
2137 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2139 physid_set(i, phys_id_present_map);
2140 ioapics[ioapic_idx].mp_config.apicid = i;
2143 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
2145 apic_printk(APIC_VERBOSE, "Setting %d in the "
2146 "phys_id_present_map\n",
2147 mpc_ioapic_id(ioapic_idx));
2148 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2152 * We need to adjust the IRQ routing table
2153 * if the ID changed.
2155 if (old_id != mpc_ioapic_id(ioapic_idx))
2156 for (i = 0; i < mp_irq_entries; i++)
2157 if (mp_irqs[i].dstapic == old_id)
2159 = mpc_ioapic_id(ioapic_idx);
2162 * Update the ID register according to the right value
2163 * from the MPC table if they are different.
2165 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
2168 apic_printk(APIC_VERBOSE, KERN_INFO
2169 "...changing IO-APIC physical APIC ID to %d ...",
2170 mpc_ioapic_id(ioapic_idx));
2172 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2173 raw_spin_lock_irqsave(&ioapic_lock, flags);
2174 io_apic_write(ioapic_idx, 0, reg_00.raw);
2175 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2180 raw_spin_lock_irqsave(&ioapic_lock, flags);
2181 reg_00.raw = io_apic_read(ioapic_idx, 0);
2182 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2183 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
2184 printk("could not set ID!\n");
2186 apic_printk(APIC_VERBOSE, " ok.\n");
2190 void __init setup_ioapic_ids_from_mpc(void)
2196 * Don't check I/O APIC IDs for xAPIC systems. They have
2197 * no meaning without the serial APIC bus.
2199 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2200 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2202 setup_ioapic_ids_from_mpc_nocheck();
2206 int no_timer_check __initdata;
2208 static int __init notimercheck(char *s)
2213 __setup("no_timer_check", notimercheck);
2216 * There is a nasty bug in some older SMP boards, their mptable lies
2217 * about the timer IRQ. We do the following to work around the situation:
2219 * - timer IRQ defaults to IO-APIC IRQ
2220 * - if this function detects that timer IRQs are defunct, then we fall
2221 * back to ISA timer IRQs
2223 static int __init timer_irq_works(void)
2225 unsigned long t1 = jiffies;
2226 unsigned long flags;
2231 local_save_flags(flags);
2233 /* Let ten ticks pass... */
2234 mdelay((10 * 1000) / HZ);
2235 local_irq_restore(flags);
2238 * Expect a few ticks at least, to be sure some possible
2239 * glue logic does not lock up after one or two first
2240 * ticks in a non-ExtINT mode. Also the local APIC
2241 * might have cached one ExtINT interrupt. Finally, at
2242 * least one tick may be lost due to delays.
2246 if (time_after(jiffies, t1 + 4))
2252 * In the SMP+IOAPIC case it might happen that there are an unspecified
2253 * number of pending IRQ events unhandled. These cases are very rare,
2254 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2255 * better to do it this way as thus we do not have to be aware of
2256 * 'pending' interrupts in the IRQ path, except at this point.
2259 * Edge triggered needs to resend any interrupt
2260 * that was delayed but this is now handled in the device
2265 * Starting up a edge-triggered IO-APIC interrupt is
2266 * nasty - we need to make sure that we get the edge.
2267 * If it is already asserted for some reason, we need
2268 * return 1 to indicate that is was pending.
2270 * This is not complete - we should be able to fake
2271 * an edge even if it isn't on the 8259A...
2274 static unsigned int startup_ioapic_irq(struct irq_data *data)
2276 int was_pending = 0, irq = data->irq;
2277 unsigned long flags;
2279 raw_spin_lock_irqsave(&ioapic_lock, flags);
2280 if (irq < legacy_pic->nr_legacy_irqs) {
2281 legacy_pic->mask(irq);
2282 if (legacy_pic->irq_pending(irq))
2285 __unmask_ioapic(data->chip_data);
2286 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2291 static int ioapic_retrigger_irq(struct irq_data *data)
2293 struct irq_cfg *cfg = data->chip_data;
2294 unsigned long flags;
2296 raw_spin_lock_irqsave(&vector_lock, flags);
2297 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2298 raw_spin_unlock_irqrestore(&vector_lock, flags);
2304 * Level and edge triggered IO-APIC interrupts need different handling,
2305 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2306 * handled with the level-triggered descriptor, but that one has slightly
2307 * more overhead. Level-triggered interrupts cannot be handled with the
2308 * edge-triggered handler, without risking IRQ storms and other ugly
2313 void send_cleanup_vector(struct irq_cfg *cfg)
2315 cpumask_var_t cleanup_mask;
2317 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2319 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2320 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2322 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2323 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2324 free_cpumask_var(cleanup_mask);
2326 cfg->move_in_progress = 0;
2329 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2332 struct irq_pin_list *entry;
2333 u8 vector = cfg->vector;
2335 for_each_irq_pin(entry, cfg->irq_2_pin) {
2341 * With interrupt-remapping, destination information comes
2342 * from interrupt-remapping table entry.
2344 if (!irq_remapped(cfg))
2345 io_apic_write(apic, 0x11 + pin*2, dest);
2346 reg = io_apic_read(apic, 0x10 + pin*2);
2347 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2349 io_apic_modify(apic, 0x10 + pin*2, reg);
2354 * Either sets data->affinity to a valid value, and returns
2355 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2356 * leaves data->affinity untouched.
2358 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2359 unsigned int *dest_id)
2361 struct irq_cfg *cfg = data->chip_data;
2363 if (!cpumask_intersects(mask, cpu_online_mask))
2366 if (assign_irq_vector(data->irq, data->chip_data, mask))
2369 cpumask_copy(data->affinity, mask);
2371 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
2376 ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2379 unsigned int dest, irq = data->irq;
2380 unsigned long flags;
2383 raw_spin_lock_irqsave(&ioapic_lock, flags);
2384 ret = __ioapic_set_affinity(data, mask, &dest);
2386 /* Only the high 8 bits are valid. */
2387 dest = SET_APIC_LOGICAL_ID(dest);
2388 __target_IO_APIC_irq(irq, dest, data->chip_data);
2390 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2394 #ifdef CONFIG_IRQ_REMAP
2397 * Migrate the IO-APIC irq in the presence of intr-remapping.
2399 * For both level and edge triggered, irq migration is a simple atomic
2400 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2402 * For level triggered, we eliminate the io-apic RTE modification (with the
2403 * updated vector information), by using a virtual vector (io-apic pin number).
2404 * Real vector that is used for interrupting cpu will be coming from
2405 * the interrupt-remapping table entry.
2407 * As the migration is a simple atomic update of IRTE, the same mechanism
2408 * is used to migrate MSI irq's in the presence of interrupt-remapping.
2411 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2414 struct irq_cfg *cfg = data->chip_data;
2415 unsigned int dest, irq = data->irq;
2418 if (!cpumask_intersects(mask, cpu_online_mask))
2421 if (get_irte(irq, &irte))
2424 if (assign_irq_vector(irq, cfg, mask))
2427 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2429 irte.vector = cfg->vector;
2430 irte.dest_id = IRTE_DEST(dest);
2433 * Atomically updates the IRTE with the new destination, vector
2434 * and flushes the interrupt entry cache.
2436 modify_irte(irq, &irte);
2439 * After this point, all the interrupts will start arriving
2440 * at the new destination. So, time to cleanup the previous
2441 * vector allocation.
2443 if (cfg->move_in_progress)
2444 send_cleanup_vector(cfg);
2446 cpumask_copy(data->affinity, mask);
2452 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2459 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2461 unsigned vector, me;
2467 me = smp_processor_id();
2468 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2471 struct irq_desc *desc;
2472 struct irq_cfg *cfg;
2473 irq = __this_cpu_read(vector_irq[vector]);
2478 desc = irq_to_desc(irq);
2483 raw_spin_lock(&desc->lock);
2486 * Check if the irq migration is in progress. If so, we
2487 * haven't received the cleanup request yet for this irq.
2489 if (cfg->move_in_progress)
2492 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2495 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2497 * Check if the vector that needs to be cleanedup is
2498 * registered at the cpu's IRR. If so, then this is not
2499 * the best time to clean it up. Lets clean it up in the
2500 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2503 if (irr & (1 << (vector % 32))) {
2504 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2507 __this_cpu_write(vector_irq[vector], -1);
2509 raw_spin_unlock(&desc->lock);
2515 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2519 if (likely(!cfg->move_in_progress))
2522 me = smp_processor_id();
2524 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2525 send_cleanup_vector(cfg);
2528 static void irq_complete_move(struct irq_cfg *cfg)
2530 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2533 void irq_force_complete_move(int irq)
2535 struct irq_cfg *cfg = irq_get_chip_data(irq);
2540 __irq_complete_move(cfg, cfg->vector);
2543 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2546 static void ack_apic_edge(struct irq_data *data)
2548 irq_complete_move(data->chip_data);
2553 atomic_t irq_mis_count;
2555 #ifdef CONFIG_GENERIC_PENDING_IRQ
2556 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2558 /* If we are moving the irq we need to mask it */
2559 if (unlikely(irqd_is_setaffinity_pending(data))) {
2566 static inline void ioapic_irqd_unmask(struct irq_data *data,
2567 struct irq_cfg *cfg, bool masked)
2569 if (unlikely(masked)) {
2570 /* Only migrate the irq if the ack has been received.
2572 * On rare occasions the broadcast level triggered ack gets
2573 * delayed going to ioapics, and if we reprogram the
2574 * vector while Remote IRR is still set the irq will never
2577 * To prevent this scenario we read the Remote IRR bit
2578 * of the ioapic. This has two effects.
2579 * - On any sane system the read of the ioapic will
2580 * flush writes (and acks) going to the ioapic from
2582 * - We get to see if the ACK has actually been delivered.
2584 * Based on failed experiments of reprogramming the
2585 * ioapic entry from outside of irq context starting
2586 * with masking the ioapic entry and then polling until
2587 * Remote IRR was clear before reprogramming the
2588 * ioapic I don't trust the Remote IRR bit to be
2589 * completey accurate.
2591 * However there appears to be no other way to plug
2592 * this race, so if the Remote IRR bit is not
2593 * accurate and is causing problems then it is a hardware bug
2594 * and you can go talk to the chipset vendor about it.
2596 if (!io_apic_level_ack_pending(cfg))
2597 irq_move_masked_irq(data);
2602 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2606 static inline void ioapic_irqd_unmask(struct irq_data *data,
2607 struct irq_cfg *cfg, bool masked)
2612 static void ack_apic_level(struct irq_data *data)
2614 struct irq_cfg *cfg = data->chip_data;
2615 int i, irq = data->irq;
2619 irq_complete_move(cfg);
2620 masked = ioapic_irqd_mask(data, cfg);
2623 * It appears there is an erratum which affects at least version 0x11
2624 * of I/O APIC (that's the 82093AA and cores integrated into various
2625 * chipsets). Under certain conditions a level-triggered interrupt is
2626 * erroneously delivered as edge-triggered one but the respective IRR
2627 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2628 * message but it will never arrive and further interrupts are blocked
2629 * from the source. The exact reason is so far unknown, but the
2630 * phenomenon was observed when two consecutive interrupt requests
2631 * from a given source get delivered to the same CPU and the source is
2632 * temporarily disabled in between.
2634 * A workaround is to simulate an EOI message manually. We achieve it
2635 * by setting the trigger mode to edge and then to level when the edge
2636 * trigger mode gets detected in the TMR of a local APIC for a
2637 * level-triggered interrupt. We mask the source for the time of the
2638 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2639 * The idea is from Manfred Spraul. --macro
2641 * Also in the case when cpu goes offline, fixup_irqs() will forward
2642 * any unhandled interrupt on the offlined cpu to the new cpu
2643 * destination that is handling the corresponding interrupt. This
2644 * interrupt forwarding is done via IPI's. Hence, in this case also
2645 * level-triggered io-apic interrupt will be seen as an edge
2646 * interrupt in the IRR. And we can't rely on the cpu's EOI
2647 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2648 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2649 * supporting EOI register, we do an explicit EOI to clear the
2650 * remote IRR and on IO-APIC's which don't have an EOI register,
2651 * we use the above logic (mask+edge followed by unmask+level) from
2652 * Manfred Spraul to clear the remote IRR.
2655 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2658 * We must acknowledge the irq before we move it or the acknowledge will
2659 * not propagate properly.
2664 * Tail end of clearing remote IRR bit (either by delivering the EOI
2665 * message via io-apic EOI register write or simulating it using
2666 * mask+edge followed by unnask+level logic) manually when the
2667 * level triggered interrupt is seen as the edge triggered interrupt
2670 if (!(v & (1 << (i & 0x1f)))) {
2671 atomic_inc(&irq_mis_count);
2673 eoi_ioapic_irq(irq, cfg);
2676 ioapic_irqd_unmask(data, cfg, masked);
2679 #ifdef CONFIG_IRQ_REMAP
2680 static void ir_ack_apic_edge(struct irq_data *data)
2685 static void ir_ack_apic_level(struct irq_data *data)
2688 eoi_ioapic_irq(data->irq, data->chip_data);
2691 static void ir_print_prefix(struct irq_data *data, struct seq_file *p)
2693 seq_printf(p, " IR-%s", data->chip->name);
2696 static void irq_remap_modify_chip_defaults(struct irq_chip *chip)
2698 chip->irq_print_chip = ir_print_prefix;
2699 chip->irq_ack = ir_ack_apic_edge;
2700 chip->irq_eoi = ir_ack_apic_level;
2703 chip->irq_set_affinity = ir_ioapic_set_affinity;
2706 #endif /* CONFIG_IRQ_REMAP */
2708 static struct irq_chip ioapic_chip __read_mostly = {
2710 .irq_startup = startup_ioapic_irq,
2711 .irq_mask = mask_ioapic_irq,
2712 .irq_unmask = unmask_ioapic_irq,
2713 .irq_ack = ack_apic_edge,
2714 .irq_eoi = ack_apic_level,
2716 .irq_set_affinity = ioapic_set_affinity,
2718 .irq_retrigger = ioapic_retrigger_irq,
2721 static inline void init_IO_APIC_traps(void)
2723 struct irq_cfg *cfg;
2727 * NOTE! The local APIC isn't very good at handling
2728 * multiple interrupts at the same interrupt level.
2729 * As the interrupt level is determined by taking the
2730 * vector number and shifting that right by 4, we
2731 * want to spread these out a bit so that they don't
2732 * all fall in the same interrupt level.
2734 * Also, we've got to be careful not to trash gate
2735 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2737 for_each_active_irq(irq) {
2738 cfg = irq_get_chip_data(irq);
2739 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2741 * Hmm.. We don't have an entry for this,
2742 * so default to an old-fashioned 8259
2743 * interrupt if we can..
2745 if (irq < legacy_pic->nr_legacy_irqs)
2746 legacy_pic->make_irq(irq);
2748 /* Strange. Oh, well.. */
2749 irq_set_chip(irq, &no_irq_chip);
2755 * The local APIC irq-chip implementation:
2758 static void mask_lapic_irq(struct irq_data *data)
2762 v = apic_read(APIC_LVT0);
2763 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2766 static void unmask_lapic_irq(struct irq_data *data)
2770 v = apic_read(APIC_LVT0);
2771 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2774 static void ack_lapic_irq(struct irq_data *data)
2779 static struct irq_chip lapic_chip __read_mostly = {
2780 .name = "local-APIC",
2781 .irq_mask = mask_lapic_irq,
2782 .irq_unmask = unmask_lapic_irq,
2783 .irq_ack = ack_lapic_irq,
2786 static void lapic_register_intr(int irq)
2788 irq_clear_status_flags(irq, IRQ_LEVEL);
2789 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2794 * This looks a bit hackish but it's about the only one way of sending
2795 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2796 * not support the ExtINT mode, unfortunately. We need to send these
2797 * cycles as some i82489DX-based boards have glue logic that keeps the
2798 * 8259A interrupt line asserted until INTA. --macro
2800 static inline void __init unlock_ExtINT_logic(void)
2803 struct IO_APIC_route_entry entry0, entry1;
2804 unsigned char save_control, save_freq_select;
2806 pin = find_isa_irq_pin(8, mp_INT);
2811 apic = find_isa_irq_apic(8, mp_INT);
2817 entry0 = ioapic_read_entry(apic, pin);
2818 clear_IO_APIC_pin(apic, pin);
2820 memset(&entry1, 0, sizeof(entry1));
2822 entry1.dest_mode = 0; /* physical delivery */
2823 entry1.mask = 0; /* unmask IRQ now */
2824 entry1.dest = hard_smp_processor_id();
2825 entry1.delivery_mode = dest_ExtINT;
2826 entry1.polarity = entry0.polarity;
2830 ioapic_write_entry(apic, pin, entry1);
2832 save_control = CMOS_READ(RTC_CONTROL);
2833 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2834 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2836 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2841 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2845 CMOS_WRITE(save_control, RTC_CONTROL);
2846 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2847 clear_IO_APIC_pin(apic, pin);
2849 ioapic_write_entry(apic, pin, entry0);
2852 static int disable_timer_pin_1 __initdata;
2853 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2854 static int __init disable_timer_pin_setup(char *arg)
2856 disable_timer_pin_1 = 1;
2859 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2861 int timer_through_8259 __initdata;
2864 * This code may look a bit paranoid, but it's supposed to cooperate with
2865 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2866 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2867 * fanatically on his truly buggy board.
2869 * FIXME: really need to revamp this for all platforms.
2871 static inline void __init check_timer(void)
2873 struct irq_cfg *cfg = irq_get_chip_data(0);
2874 int node = cpu_to_node(0);
2875 int apic1, pin1, apic2, pin2;
2876 unsigned long flags;
2879 local_irq_save(flags);
2882 * get/set the timer IRQ vector:
2884 legacy_pic->mask(0);
2885 assign_irq_vector(0, cfg, apic->target_cpus());
2888 * As IRQ0 is to be enabled in the 8259A, the virtual
2889 * wire has to be disabled in the local APIC. Also
2890 * timer interrupts need to be acknowledged manually in
2891 * the 8259A for the i82489DX when using the NMI
2892 * watchdog as that APIC treats NMIs as level-triggered.
2893 * The AEOI mode will finish them in the 8259A
2896 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2897 legacy_pic->init(1);
2899 pin1 = find_isa_irq_pin(0, mp_INT);
2900 apic1 = find_isa_irq_apic(0, mp_INT);
2901 pin2 = ioapic_i8259.pin;
2902 apic2 = ioapic_i8259.apic;
2904 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2905 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2906 cfg->vector, apic1, pin1, apic2, pin2);
2909 * Some BIOS writers are clueless and report the ExtINTA
2910 * I/O APIC input from the cascaded 8259A as the timer
2911 * interrupt input. So just in case, if only one pin
2912 * was found above, try it both directly and through the
2916 if (intr_remapping_enabled)
2917 panic("BIOS bug: timer not connected to IO-APIC");
2921 } else if (pin2 == -1) {
2928 * Ok, does IRQ0 through the IOAPIC work?
2931 add_pin_to_irq_node(cfg, node, apic1, pin1);
2932 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2934 /* for edge trigger, setup_ioapic_irq already
2935 * leave it unmasked.
2936 * so only need to unmask if it is level-trigger
2937 * do we really have level trigger timer?
2940 idx = find_irq_entry(apic1, pin1, mp_INT);
2941 if (idx != -1 && irq_trigger(idx))
2944 if (timer_irq_works()) {
2945 if (disable_timer_pin_1 > 0)
2946 clear_IO_APIC_pin(0, pin1);
2949 if (intr_remapping_enabled)
2950 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2951 local_irq_disable();
2952 clear_IO_APIC_pin(apic1, pin1);
2954 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2955 "8254 timer not connected to IO-APIC\n");
2957 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2958 "(IRQ0) through the 8259A ...\n");
2959 apic_printk(APIC_QUIET, KERN_INFO
2960 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2962 * legacy devices should be connected to IO APIC #0
2964 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2965 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2966 legacy_pic->unmask(0);
2967 if (timer_irq_works()) {
2968 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2969 timer_through_8259 = 1;
2973 * Cleanup, just in case ...
2975 local_irq_disable();
2976 legacy_pic->mask(0);
2977 clear_IO_APIC_pin(apic2, pin2);
2978 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2981 apic_printk(APIC_QUIET, KERN_INFO
2982 "...trying to set up timer as Virtual Wire IRQ...\n");
2984 lapic_register_intr(0);
2985 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2986 legacy_pic->unmask(0);
2988 if (timer_irq_works()) {
2989 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2992 local_irq_disable();
2993 legacy_pic->mask(0);
2994 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2995 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2997 apic_printk(APIC_QUIET, KERN_INFO
2998 "...trying to set up timer as ExtINT IRQ...\n");
3000 legacy_pic->init(0);
3001 legacy_pic->make_irq(0);
3002 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3004 unlock_ExtINT_logic();
3006 if (timer_irq_works()) {
3007 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3010 local_irq_disable();
3011 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3012 if (x2apic_preenabled)
3013 apic_printk(APIC_QUIET, KERN_INFO
3014 "Perhaps problem with the pre-enabled x2apic mode\n"
3015 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
3016 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3017 "report. Then try booting with the 'noapic' option.\n");
3019 local_irq_restore(flags);
3023 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3024 * to devices. However there may be an I/O APIC pin available for
3025 * this interrupt regardless. The pin may be left unconnected, but
3026 * typically it will be reused as an ExtINT cascade interrupt for
3027 * the master 8259A. In the MPS case such a pin will normally be
3028 * reported as an ExtINT interrupt in the MP table. With ACPI
3029 * there is no provision for ExtINT interrupts, and in the absence
3030 * of an override it would be treated as an ordinary ISA I/O APIC
3031 * interrupt, that is edge-triggered and unmasked by default. We
3032 * used to do this, but it caused problems on some systems because
3033 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3034 * the same ExtINT cascade interrupt to drive the local APIC of the
3035 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3036 * the I/O APIC in all cases now. No actual device should request
3037 * it anyway. --macro
3039 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3041 void __init setup_IO_APIC(void)
3045 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3047 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3049 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3051 * Set up IO-APIC IRQ routing.
3053 x86_init.mpparse.setup_ioapic_ids();
3056 setup_IO_APIC_irqs();
3057 init_IO_APIC_traps();
3058 if (legacy_pic->nr_legacy_irqs)
3063 * Called after all the initialization is done. If we didn't find any
3064 * APIC bugs then we can allow the modify fast path
3067 static int __init io_apic_bug_finalize(void)
3069 if (sis_apic_bug == -1)
3074 late_initcall(io_apic_bug_finalize);
3076 static void resume_ioapic_id(int ioapic_idx)
3078 unsigned long flags;
3079 union IO_APIC_reg_00 reg_00;
3081 raw_spin_lock_irqsave(&ioapic_lock, flags);
3082 reg_00.raw = io_apic_read(ioapic_idx, 0);
3083 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
3084 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
3085 io_apic_write(ioapic_idx, 0, reg_00.raw);
3087 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3090 static void ioapic_resume(void)
3094 for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--)
3095 resume_ioapic_id(ioapic_idx);
3097 restore_ioapic_entries();
3100 static struct syscore_ops ioapic_syscore_ops = {
3101 .suspend = save_ioapic_entries,
3102 .resume = ioapic_resume,
3105 static int __init ioapic_init_ops(void)
3107 register_syscore_ops(&ioapic_syscore_ops);
3112 device_initcall(ioapic_init_ops);
3115 * Dynamic irq allocate and deallocation
3117 unsigned int create_irq_nr(unsigned int from, int node)
3119 struct irq_cfg *cfg;
3120 unsigned long flags;
3121 unsigned int ret = 0;
3124 if (from < nr_irqs_gsi)
3127 irq = alloc_irq_from(from, node);
3130 cfg = alloc_irq_cfg(irq, node);
3132 free_irq_at(irq, NULL);
3136 raw_spin_lock_irqsave(&vector_lock, flags);
3137 if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
3139 raw_spin_unlock_irqrestore(&vector_lock, flags);
3142 irq_set_chip_data(irq, cfg);
3143 irq_clear_status_flags(irq, IRQ_NOREQUEST);
3145 free_irq_at(irq, cfg);
3150 int create_irq(void)
3152 int node = cpu_to_node(0);
3153 unsigned int irq_want;
3156 irq_want = nr_irqs_gsi;
3157 irq = create_irq_nr(irq_want, node);
3165 void destroy_irq(unsigned int irq)
3167 struct irq_cfg *cfg = irq_get_chip_data(irq);
3168 unsigned long flags;
3170 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3172 if (irq_remapped(cfg))
3174 raw_spin_lock_irqsave(&vector_lock, flags);
3175 __clear_irq_vector(irq, cfg);
3176 raw_spin_unlock_irqrestore(&vector_lock, flags);
3177 free_irq_at(irq, cfg);
3181 * MSI message composition
3183 #ifdef CONFIG_PCI_MSI
3184 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3185 struct msi_msg *msg, u8 hpet_id)
3187 struct irq_cfg *cfg;
3195 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3199 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3201 if (irq_remapped(cfg)) {
3206 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3207 BUG_ON(ir_index == -1);
3209 prepare_irte(&irte, cfg->vector, dest);
3211 /* Set source-id of interrupt request */
3213 set_msi_sid(&irte, pdev);
3215 set_hpet_sid(&irte, hpet_id);
3217 modify_irte(irq, &irte);
3219 msg->address_hi = MSI_ADDR_BASE_HI;
3220 msg->data = sub_handle;
3221 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3223 MSI_ADDR_IR_INDEX1(ir_index) |
3224 MSI_ADDR_IR_INDEX2(ir_index);
3226 if (x2apic_enabled())
3227 msg->address_hi = MSI_ADDR_BASE_HI |
3228 MSI_ADDR_EXT_DEST_ID(dest);
3230 msg->address_hi = MSI_ADDR_BASE_HI;
3234 ((apic->irq_dest_mode == 0) ?
3235 MSI_ADDR_DEST_MODE_PHYSICAL:
3236 MSI_ADDR_DEST_MODE_LOGICAL) |
3237 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3238 MSI_ADDR_REDIRECTION_CPU:
3239 MSI_ADDR_REDIRECTION_LOWPRI) |
3240 MSI_ADDR_DEST_ID(dest);
3243 MSI_DATA_TRIGGER_EDGE |
3244 MSI_DATA_LEVEL_ASSERT |
3245 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3246 MSI_DATA_DELIVERY_FIXED:
3247 MSI_DATA_DELIVERY_LOWPRI) |
3248 MSI_DATA_VECTOR(cfg->vector);
3255 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3257 struct irq_cfg *cfg = data->chip_data;
3261 if (__ioapic_set_affinity(data, mask, &dest))
3264 __get_cached_msi_msg(data->msi_desc, &msg);
3266 msg.data &= ~MSI_DATA_VECTOR_MASK;
3267 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3268 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3269 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3271 __write_msi_msg(data->msi_desc, &msg);
3275 #endif /* CONFIG_SMP */
3278 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3279 * which implement the MSI or MSI-X Capability Structure.
3281 static struct irq_chip msi_chip = {
3283 .irq_unmask = unmask_msi_irq,
3284 .irq_mask = mask_msi_irq,
3285 .irq_ack = ack_apic_edge,
3287 .irq_set_affinity = msi_set_affinity,
3289 .irq_retrigger = ioapic_retrigger_irq,
3293 * Map the PCI dev to the corresponding remapping hardware unit
3294 * and allocate 'nvec' consecutive interrupt-remapping table entries
3297 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3299 struct intel_iommu *iommu;
3302 iommu = map_dev_to_ir(dev);
3305 "Unable to map PCI %s to iommu\n", pci_name(dev));
3309 index = alloc_irte(iommu, irq, nvec);
3312 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3319 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3321 struct irq_chip *chip = &msi_chip;
3325 ret = msi_compose_msg(dev, irq, &msg, -1);
3329 irq_set_msi_desc(irq, msidesc);
3330 write_msi_msg(irq, &msg);
3332 if (irq_remapped(irq_get_chip_data(irq))) {
3333 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3334 irq_remap_modify_chip_defaults(chip);
3337 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3339 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3344 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3346 int node, ret, sub_handle, index = 0;
3347 unsigned int irq, irq_want;
3348 struct msi_desc *msidesc;
3349 struct intel_iommu *iommu = NULL;
3351 /* x86 doesn't support multiple MSI yet */
3352 if (type == PCI_CAP_ID_MSI && nvec > 1)
3355 node = dev_to_node(&dev->dev);
3356 irq_want = nr_irqs_gsi;
3358 list_for_each_entry(msidesc, &dev->msi_list, list) {
3359 irq = create_irq_nr(irq_want, node);
3363 if (!intr_remapping_enabled)
3368 * allocate the consecutive block of IRTE's
3371 index = msi_alloc_irte(dev, irq, nvec);
3377 iommu = map_dev_to_ir(dev);
3383 * setup the mapping between the irq and the IRTE
3384 * base index, the sub_handle pointing to the
3385 * appropriate interrupt remap table entry.
3387 set_irte_irq(irq, iommu, index, sub_handle);
3390 ret = setup_msi_irq(dev, msidesc, irq);
3402 void native_teardown_msi_irq(unsigned int irq)
3407 #ifdef CONFIG_DMAR_TABLE
3410 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3413 struct irq_cfg *cfg = data->chip_data;
3414 unsigned int dest, irq = data->irq;
3417 if (__ioapic_set_affinity(data, mask, &dest))
3420 dmar_msi_read(irq, &msg);
3422 msg.data &= ~MSI_DATA_VECTOR_MASK;
3423 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3424 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3425 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3426 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3428 dmar_msi_write(irq, &msg);
3433 #endif /* CONFIG_SMP */
3435 static struct irq_chip dmar_msi_type = {
3437 .irq_unmask = dmar_msi_unmask,
3438 .irq_mask = dmar_msi_mask,
3439 .irq_ack = ack_apic_edge,
3441 .irq_set_affinity = dmar_msi_set_affinity,
3443 .irq_retrigger = ioapic_retrigger_irq,
3446 int arch_setup_dmar_msi(unsigned int irq)
3451 ret = msi_compose_msg(NULL, irq, &msg, -1);
3454 dmar_msi_write(irq, &msg);
3455 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3461 #ifdef CONFIG_HPET_TIMER
3464 static int hpet_msi_set_affinity(struct irq_data *data,
3465 const struct cpumask *mask, bool force)
3467 struct irq_cfg *cfg = data->chip_data;
3471 if (__ioapic_set_affinity(data, mask, &dest))
3474 hpet_msi_read(data->handler_data, &msg);
3476 msg.data &= ~MSI_DATA_VECTOR_MASK;
3477 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3478 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3479 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3481 hpet_msi_write(data->handler_data, &msg);
3486 #endif /* CONFIG_SMP */
3488 static struct irq_chip hpet_msi_type = {
3490 .irq_unmask = hpet_msi_unmask,
3491 .irq_mask = hpet_msi_mask,
3492 .irq_ack = ack_apic_edge,
3494 .irq_set_affinity = hpet_msi_set_affinity,
3496 .irq_retrigger = ioapic_retrigger_irq,
3499 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3501 struct irq_chip *chip = &hpet_msi_type;
3505 if (intr_remapping_enabled) {
3506 struct intel_iommu *iommu = map_hpet_to_ir(id);
3512 index = alloc_irte(iommu, irq, 1);
3517 ret = msi_compose_msg(NULL, irq, &msg, id);
3521 hpet_msi_write(irq_get_handler_data(irq), &msg);
3522 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3523 if (irq_remapped(irq_get_chip_data(irq)))
3524 irq_remap_modify_chip_defaults(chip);
3526 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3531 #endif /* CONFIG_PCI_MSI */
3533 * Hypertransport interrupt support
3535 #ifdef CONFIG_HT_IRQ
3539 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3541 struct ht_irq_msg msg;
3542 fetch_ht_irq_msg(irq, &msg);
3544 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3545 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3547 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3548 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3550 write_ht_irq_msg(irq, &msg);
3554 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3556 struct irq_cfg *cfg = data->chip_data;
3559 if (__ioapic_set_affinity(data, mask, &dest))
3562 target_ht_irq(data->irq, dest, cfg->vector);
3568 static struct irq_chip ht_irq_chip = {
3570 .irq_mask = mask_ht_irq,
3571 .irq_unmask = unmask_ht_irq,
3572 .irq_ack = ack_apic_edge,
3574 .irq_set_affinity = ht_set_affinity,
3576 .irq_retrigger = ioapic_retrigger_irq,
3579 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3581 struct irq_cfg *cfg;
3588 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3590 struct ht_irq_msg msg;
3593 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3594 apic->target_cpus());
3596 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3600 HT_IRQ_LOW_DEST_ID(dest) |
3601 HT_IRQ_LOW_VECTOR(cfg->vector) |
3602 ((apic->irq_dest_mode == 0) ?
3603 HT_IRQ_LOW_DM_PHYSICAL :
3604 HT_IRQ_LOW_DM_LOGICAL) |
3605 HT_IRQ_LOW_RQEOI_EDGE |
3606 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3607 HT_IRQ_LOW_MT_FIXED :
3608 HT_IRQ_LOW_MT_ARBITRATED) |
3609 HT_IRQ_LOW_IRQ_MASKED;
3611 write_ht_irq_msg(irq, &msg);
3613 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3614 handle_edge_irq, "edge");
3616 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3620 #endif /* CONFIG_HT_IRQ */
3623 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3625 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3630 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3632 setup_ioapic_irq(irq, cfg, attr);
3636 int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3637 struct io_apic_irq_attr *attr)
3639 unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
3642 /* Avoid redundant programming */
3643 if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
3644 pr_debug("Pin %d-%d already programmed\n",
3645 mpc_ioapic_id(ioapic_idx), pin);
3648 ret = io_apic_setup_irq_pin(irq, node, attr);
3650 set_bit(pin, ioapics[ioapic_idx].pin_programmed);
3654 static int __init io_apic_get_redir_entries(int ioapic)
3656 union IO_APIC_reg_01 reg_01;
3657 unsigned long flags;
3659 raw_spin_lock_irqsave(&ioapic_lock, flags);
3660 reg_01.raw = io_apic_read(ioapic, 1);
3661 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3663 /* The register returns the maximum index redir index
3664 * supported, which is one less than the total number of redir
3667 return reg_01.bits.entries + 1;
3670 static void __init probe_nr_irqs_gsi(void)
3674 nr = gsi_top + NR_IRQS_LEGACY;
3675 if (nr > nr_irqs_gsi)
3678 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3681 int get_nr_irqs_gsi(void)
3686 int __init arch_probe_nr_irqs(void)
3690 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3691 nr_irqs = NR_VECTORS * nr_cpu_ids;
3693 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3694 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3696 * for MSI and HT dyn irq
3698 nr += nr_irqs_gsi * 16;
3703 return NR_IRQS_LEGACY;
3706 int io_apic_set_pci_routing(struct device *dev, int irq,
3707 struct io_apic_irq_attr *irq_attr)
3711 if (!IO_APIC_IRQ(irq)) {
3712 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3717 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3719 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3722 #ifdef CONFIG_X86_32
3723 static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3725 union IO_APIC_reg_00 reg_00;
3726 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3728 unsigned long flags;
3732 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3733 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3734 * supports up to 16 on one shared APIC bus.
3736 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3737 * advantage of new APIC bus architecture.
3740 if (physids_empty(apic_id_map))
3741 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3743 raw_spin_lock_irqsave(&ioapic_lock, flags);
3744 reg_00.raw = io_apic_read(ioapic, 0);
3745 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3747 if (apic_id >= get_physical_broadcast()) {
3748 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3749 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3750 apic_id = reg_00.bits.ID;
3754 * Every APIC in a system must have a unique ID or we get lots of nice
3755 * 'stuck on smp_invalidate_needed IPI wait' messages.
3757 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3759 for (i = 0; i < get_physical_broadcast(); i++) {
3760 if (!apic->check_apicid_used(&apic_id_map, i))
3764 if (i == get_physical_broadcast())
3765 panic("Max apic_id exceeded!\n");
3767 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3768 "trying %d\n", ioapic, apic_id, i);
3773 apic->apicid_to_cpu_present(apic_id, &tmp);
3774 physids_or(apic_id_map, apic_id_map, tmp);
3776 if (reg_00.bits.ID != apic_id) {
3777 reg_00.bits.ID = apic_id;
3779 raw_spin_lock_irqsave(&ioapic_lock, flags);
3780 io_apic_write(ioapic, 0, reg_00.raw);
3781 reg_00.raw = io_apic_read(ioapic, 0);
3782 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3785 if (reg_00.bits.ID != apic_id) {
3786 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3791 apic_printk(APIC_VERBOSE, KERN_INFO
3792 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3797 static u8 __init io_apic_unique_id(u8 id)
3799 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3800 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3801 return io_apic_get_unique_id(nr_ioapics, id);
3806 static u8 __init io_apic_unique_id(u8 id)
3809 DECLARE_BITMAP(used, 256);
3811 bitmap_zero(used, 256);
3812 for (i = 0; i < nr_ioapics; i++) {
3813 __set_bit(mpc_ioapic_id(i), used);
3815 if (!test_bit(id, used))
3817 return find_first_zero_bit(used, 256);
3821 static int __init io_apic_get_version(int ioapic)
3823 union IO_APIC_reg_01 reg_01;
3824 unsigned long flags;
3826 raw_spin_lock_irqsave(&ioapic_lock, flags);
3827 reg_01.raw = io_apic_read(ioapic, 1);
3828 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3830 return reg_01.bits.version;
3833 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3835 int ioapic, pin, idx;
3837 if (skip_ioapic_setup)
3840 ioapic = mp_find_ioapic(gsi);
3844 pin = mp_find_ioapic_pin(ioapic, gsi);
3848 idx = find_irq_entry(ioapic, pin, mp_INT);
3852 *trigger = irq_trigger(idx);
3853 *polarity = irq_polarity(idx);
3858 * This function currently is only a helper for the i386 smp boot process where
3859 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3860 * so mask in all cases should simply be apic->target_cpus()
3863 void __init setup_ioapic_dest(void)
3865 int pin, ioapic, irq, irq_entry;
3866 const struct cpumask *mask;
3867 struct irq_data *idata;
3869 if (skip_ioapic_setup == 1)
3872 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3873 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3874 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3875 if (irq_entry == -1)
3877 irq = pin_2_irq(irq_entry, ioapic, pin);
3879 if ((ioapic > 0) && (irq > 16))
3882 idata = irq_get_irq_data(irq);
3885 * Honour affinities which have been set in early boot
3887 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3888 mask = idata->affinity;
3890 mask = apic->target_cpus();
3892 if (intr_remapping_enabled)
3893 ir_ioapic_set_affinity(idata, mask, false);
3895 ioapic_set_affinity(idata, mask, false);
3901 #define IOAPIC_RESOURCE_NAME_SIZE 11
3903 static struct resource *ioapic_resources;
3905 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3908 struct resource *res;
3912 if (nr_ioapics <= 0)
3915 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3918 mem = alloc_bootmem(n);
3921 mem += sizeof(struct resource) * nr_ioapics;
3923 for (i = 0; i < nr_ioapics; i++) {
3925 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3926 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3927 mem += IOAPIC_RESOURCE_NAME_SIZE;
3930 ioapic_resources = res;
3935 void __init ioapic_and_gsi_init(void)
3940 static void __init __ioapic_init_mappings(void)
3942 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3943 struct resource *ioapic_res;
3946 ioapic_res = ioapic_setup_resources(nr_ioapics);
3947 for (i = 0; i < nr_ioapics; i++) {
3948 if (smp_found_config) {
3949 ioapic_phys = mpc_ioapic_addr(i);
3950 #ifdef CONFIG_X86_32
3953 "WARNING: bogus zero IO-APIC "
3954 "address found in MPTABLE, "
3955 "disabling IO/APIC support!\n");
3956 smp_found_config = 0;
3957 skip_ioapic_setup = 1;
3958 goto fake_ioapic_page;
3962 #ifdef CONFIG_X86_32
3965 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3966 ioapic_phys = __pa(ioapic_phys);
3968 set_fixmap_nocache(idx, ioapic_phys);
3969 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3970 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3974 ioapic_res->start = ioapic_phys;
3975 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3979 probe_nr_irqs_gsi();
3982 void __init ioapic_insert_resources(void)
3985 struct resource *r = ioapic_resources;
3990 "IO APIC resources couldn't be allocated.\n");
3994 for (i = 0; i < nr_ioapics; i++) {
3995 insert_resource(&iomem_resource, r);
4000 int mp_find_ioapic(u32 gsi)
4004 if (nr_ioapics == 0)
4007 /* Find the IOAPIC that manages this GSI. */
4008 for (i = 0; i < nr_ioapics; i++) {
4009 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
4010 if ((gsi >= gsi_cfg->gsi_base)
4011 && (gsi <= gsi_cfg->gsi_end))
4015 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4019 int mp_find_ioapic_pin(int ioapic, u32 gsi)
4021 struct mp_ioapic_gsi *gsi_cfg;
4023 if (WARN_ON(ioapic == -1))
4026 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
4027 if (WARN_ON(gsi > gsi_cfg->gsi_end))
4030 return gsi - gsi_cfg->gsi_base;
4033 static __init int bad_ioapic(unsigned long address)
4035 if (nr_ioapics >= MAX_IO_APICS) {
4036 pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
4037 MAX_IO_APICS, nr_ioapics);
4041 pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
4047 static __init int bad_ioapic_register(int idx)
4049 union IO_APIC_reg_00 reg_00;
4050 union IO_APIC_reg_01 reg_01;
4051 union IO_APIC_reg_02 reg_02;
4053 reg_00.raw = io_apic_read(idx, 0);
4054 reg_01.raw = io_apic_read(idx, 1);
4055 reg_02.raw = io_apic_read(idx, 2);
4057 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
4058 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
4059 mpc_ioapic_addr(idx));
4066 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4070 struct mp_ioapic_gsi *gsi_cfg;
4072 if (bad_ioapic(address))
4077 ioapics[idx].mp_config.type = MP_IOAPIC;
4078 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
4079 ioapics[idx].mp_config.apicaddr = address;
4081 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4083 if (bad_ioapic_register(idx)) {
4084 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
4088 ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
4089 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
4092 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4093 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4095 entries = io_apic_get_redir_entries(idx);
4096 gsi_cfg = mp_ioapic_gsi_routing(idx);
4097 gsi_cfg->gsi_base = gsi_base;
4098 gsi_cfg->gsi_end = gsi_base + entries - 1;
4101 * The number of IO-APIC IRQ registers (== #pins):
4103 ioapics[idx].nr_registers = entries;
4105 if (gsi_cfg->gsi_end >= gsi_top)
4106 gsi_top = gsi_cfg->gsi_end + 1;
4108 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
4109 idx, mpc_ioapic_id(idx),
4110 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
4111 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
4116 /* Enable IOAPIC early just for system timer */
4117 void __init pre_init_apic_IRQ0(void)
4119 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
4121 printk(KERN_INFO "Early APIC setup for system timer0\n");
4123 physid_set_mask_of_physid(boot_cpu_physical_apicid,
4124 &phys_cpu_present_map);
4128 io_apic_setup_irq_pin(0, 0, &attr);
4129 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,