2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/sysdev.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/dmar.h>
31 #include <linux/init.h>
32 #include <linux/cpu.h>
33 #include <linux/dmi.h>
34 #include <linux/nmi.h>
35 #include <linux/smp.h>
38 #include <asm/perf_event.h>
39 #include <asm/x86_init.h>
40 #include <asm/pgalloc.h>
41 #include <asm/atomic.h>
42 #include <asm/mpspec.h>
43 #include <asm/i8253.h>
44 #include <asm/i8259.h>
45 #include <asm/proto.h>
53 #include <asm/kvm_para.h>
55 unsigned int num_processors;
57 unsigned disabled_cpus __cpuinitdata;
59 /* Processor that is doing the boot up */
60 unsigned int boot_cpu_physical_apicid = -1U;
63 * The highest APIC ID seen during enumeration.
65 unsigned int max_physical_apicid;
68 * Bitmask of physically existing CPUs:
70 physid_mask_t phys_cpu_present_map;
73 * Map cpu index to physical APIC ID
75 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
76 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
77 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
78 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
82 * Knob to control our willingness to enable the local APIC.
86 static int force_enable_local_apic;
88 * APIC command line parameters
90 static int __init parse_lapic(char *arg)
92 force_enable_local_apic = 1;
95 early_param("lapic", parse_lapic);
96 /* Local APIC was disabled by the BIOS and enabled by the kernel */
97 static int enabled_via_apicbase;
100 * Handle interrupt mode configuration register (IMCR).
101 * This register controls whether the interrupt signals
102 * that reach the BSP come from the master PIC or from the
103 * local APIC. Before entering Symmetric I/O Mode, either
104 * the BIOS or the operating system must switch out of
105 * PIC Mode by changing the IMCR.
107 static inline void imcr_pic_to_apic(void)
109 /* select IMCR register */
111 /* NMI and 8259 INTR go through APIC */
115 static inline void imcr_apic_to_pic(void)
117 /* select IMCR register */
119 /* NMI and 8259 INTR go directly to BSP */
125 static int apic_calibrate_pmtmr __initdata;
126 static __init int setup_apicpmtimer(char *s)
128 apic_calibrate_pmtmr = 1;
132 __setup("apicpmtimer", setup_apicpmtimer);
136 #ifdef CONFIG_X86_X2APIC
137 /* x2apic enabled before OS handover */
138 static int x2apic_preenabled;
139 static __init int setup_nox2apic(char *str)
141 if (x2apic_enabled()) {
142 pr_warning("Bios already enabled x2apic, "
143 "can't enforce nox2apic");
147 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
150 early_param("nox2apic", setup_nox2apic);
153 unsigned long mp_lapic_addr;
155 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
156 static int disable_apic_timer __cpuinitdata;
157 /* Local APIC timer works in C2 */
158 int local_apic_timer_c2_ok;
159 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
161 int first_system_vector = 0xfe;
164 * Debug level, exported for io_apic.c
166 unsigned int apic_verbosity;
170 /* Have we found an MP table */
171 int smp_found_config;
173 static struct resource lapic_resource = {
174 .name = "Local APIC",
175 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
178 static unsigned int calibration_result;
180 static int lapic_next_event(unsigned long delta,
181 struct clock_event_device *evt);
182 static void lapic_timer_setup(enum clock_event_mode mode,
183 struct clock_event_device *evt);
184 static void lapic_timer_broadcast(const struct cpumask *mask);
185 static void apic_pm_activate(void);
188 * The local apic timer can be used for any function which is CPU local.
190 static struct clock_event_device lapic_clockevent = {
192 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
193 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
195 .set_mode = lapic_timer_setup,
196 .set_next_event = lapic_next_event,
197 .broadcast = lapic_timer_broadcast,
201 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
203 static unsigned long apic_phys;
206 * Get the LAPIC version
208 static inline int lapic_get_version(void)
210 return GET_APIC_VERSION(apic_read(APIC_LVR));
214 * Check, if the APIC is integrated or a separate chip
216 static inline int lapic_is_integrated(void)
221 return APIC_INTEGRATED(lapic_get_version());
226 * Check, whether this is a modern or a first generation APIC
228 static int modern_apic(void)
230 /* AMD systems use old APIC versions, so check the CPU */
231 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
232 boot_cpu_data.x86 >= 0xf)
234 return lapic_get_version() >= 0x14;
238 * right after this call apic become NOOP driven
239 * so apic->write/read doesn't do anything
241 void apic_disable(void)
243 pr_info("APIC: switched to apic NOOP\n");
247 void native_apic_wait_icr_idle(void)
249 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
253 u32 native_safe_apic_wait_icr_idle(void)
260 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
264 } while (timeout++ < 1000);
269 void native_apic_icr_write(u32 low, u32 id)
271 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
272 apic_write(APIC_ICR, low);
275 u64 native_apic_icr_read(void)
279 icr2 = apic_read(APIC_ICR2);
280 icr1 = apic_read(APIC_ICR);
282 return icr1 | ((u64)icr2 << 32);
286 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
288 void __cpuinit enable_NMI_through_LVT0(void)
292 /* unmask and set to NMI */
295 /* Level triggered for 82489DX (32bit mode) */
296 if (!lapic_is_integrated())
297 v |= APIC_LVT_LEVEL_TRIGGER;
299 apic_write(APIC_LVT0, v);
304 * get_physical_broadcast - Get number of physical broadcast IDs
306 int get_physical_broadcast(void)
308 return modern_apic() ? 0xff : 0xf;
313 * lapic_get_maxlvt - get the maximum number of local vector table entries
315 int lapic_get_maxlvt(void)
319 v = apic_read(APIC_LVR);
321 * - we always have APIC integrated on 64bit mode
322 * - 82489DXs do not report # of LVT entries
324 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
332 #define APIC_DIVISOR 16
335 * This function sets up the local APIC timer, with a timeout of
336 * 'clocks' APIC bus clock. During calibration we actually call
337 * this function twice on the boot CPU, once with a bogus timeout
338 * value, second time for real. The other (noncalibrating) CPUs
339 * call this function only once, with the real, calibrated value.
341 * We do reads before writes even if unnecessary, to get around the
342 * P5 APIC double write bug.
344 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
346 unsigned int lvtt_value, tmp_value;
348 lvtt_value = LOCAL_TIMER_VECTOR;
350 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
351 if (!lapic_is_integrated())
352 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
355 lvtt_value |= APIC_LVT_MASKED;
357 apic_write(APIC_LVTT, lvtt_value);
362 tmp_value = apic_read(APIC_TDCR);
363 apic_write(APIC_TDCR,
364 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
368 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
372 * Setup extended LVT, AMD specific (K8, family 10h)
374 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
375 * MCE interrupts are supported. Thus MCE offset must be set to 0.
377 * If mask=1, the LVT entry does not generate interrupts while mask=0
378 * enables the vector. See also the BKDGs.
381 #define APIC_EILVT_LVTOFF_MCE 0
382 #define APIC_EILVT_LVTOFF_IBS 1
384 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
386 unsigned long reg = (lvt_off << 4) + APIC_EILVTn(0);
387 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
392 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
394 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
395 return APIC_EILVT_LVTOFF_MCE;
398 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
400 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
401 return APIC_EILVT_LVTOFF_IBS;
403 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
406 * Program the next event, relative to now
408 static int lapic_next_event(unsigned long delta,
409 struct clock_event_device *evt)
411 apic_write(APIC_TMICT, delta);
416 * Setup the lapic timer in periodic or oneshot mode
418 static void lapic_timer_setup(enum clock_event_mode mode,
419 struct clock_event_device *evt)
424 /* Lapic used as dummy for broadcast ? */
425 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
428 local_irq_save(flags);
431 case CLOCK_EVT_MODE_PERIODIC:
432 case CLOCK_EVT_MODE_ONESHOT:
433 __setup_APIC_LVTT(calibration_result,
434 mode != CLOCK_EVT_MODE_PERIODIC, 1);
436 case CLOCK_EVT_MODE_UNUSED:
437 case CLOCK_EVT_MODE_SHUTDOWN:
438 v = apic_read(APIC_LVTT);
439 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
440 apic_write(APIC_LVTT, v);
441 apic_write(APIC_TMICT, 0);
443 case CLOCK_EVT_MODE_RESUME:
444 /* Nothing to do here */
448 local_irq_restore(flags);
452 * Local APIC timer broadcast function
454 static void lapic_timer_broadcast(const struct cpumask *mask)
457 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
462 * Setup the local APIC timer for this CPU. Copy the initilized values
463 * of the boot CPU and register the clock event in the framework.
465 static void __cpuinit setup_APIC_timer(void)
467 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
469 if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) {
470 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
471 /* Make LAPIC timer preferrable over percpu HPET */
472 lapic_clockevent.rating = 150;
475 memcpy(levt, &lapic_clockevent, sizeof(*levt));
476 levt->cpumask = cpumask_of(smp_processor_id());
478 clockevents_register_device(levt);
482 * In this functions we calibrate APIC bus clocks to the external timer.
484 * We want to do the calibration only once since we want to have local timer
485 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
488 * This was previously done by reading the PIT/HPET and waiting for a wrap
489 * around to find out, that a tick has elapsed. I have a box, where the PIT
490 * readout is broken, so it never gets out of the wait loop again. This was
491 * also reported by others.
493 * Monitoring the jiffies value is inaccurate and the clockevents
494 * infrastructure allows us to do a simple substitution of the interrupt
497 * The calibration routine also uses the pm_timer when possible, as the PIT
498 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
499 * back to normal later in the boot process).
502 #define LAPIC_CAL_LOOPS (HZ/10)
504 static __initdata int lapic_cal_loops = -1;
505 static __initdata long lapic_cal_t1, lapic_cal_t2;
506 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
507 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
508 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
511 * Temporary interrupt handler.
513 static void __init lapic_cal_handler(struct clock_event_device *dev)
515 unsigned long long tsc = 0;
516 long tapic = apic_read(APIC_TMCCT);
517 unsigned long pm = acpi_pm_read_early();
522 switch (lapic_cal_loops++) {
524 lapic_cal_t1 = tapic;
525 lapic_cal_tsc1 = tsc;
527 lapic_cal_j1 = jiffies;
530 case LAPIC_CAL_LOOPS:
531 lapic_cal_t2 = tapic;
532 lapic_cal_tsc2 = tsc;
533 if (pm < lapic_cal_pm1)
534 pm += ACPI_PM_OVRRUN;
536 lapic_cal_j2 = jiffies;
542 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
544 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
545 const long pm_thresh = pm_100ms / 100;
549 #ifndef CONFIG_X86_PM_TIMER
553 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
555 /* Check, if the PM timer is available */
559 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
561 if (deltapm > (pm_100ms - pm_thresh) &&
562 deltapm < (pm_100ms + pm_thresh)) {
563 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
567 res = (((u64)deltapm) * mult) >> 22;
568 do_div(res, 1000000);
569 pr_warning("APIC calibration not consistent "
570 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
572 /* Correct the lapic counter value */
573 res = (((u64)(*delta)) * pm_100ms);
574 do_div(res, deltapm);
575 pr_info("APIC delta adjusted to PM-Timer: "
576 "%lu (%ld)\n", (unsigned long)res, *delta);
579 /* Correct the tsc counter value */
581 res = (((u64)(*deltatsc)) * pm_100ms);
582 do_div(res, deltapm);
583 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
584 "PM-Timer: %lu (%ld)\n",
585 (unsigned long)res, *deltatsc);
586 *deltatsc = (long)res;
592 static int __init calibrate_APIC_clock(void)
594 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
595 void (*real_handler)(struct clock_event_device *dev);
596 unsigned long deltaj;
597 long delta, deltatsc;
598 int pm_referenced = 0;
602 /* Replace the global interrupt handler */
603 real_handler = global_clock_event->event_handler;
604 global_clock_event->event_handler = lapic_cal_handler;
607 * Setup the APIC counter to maximum. There is no way the lapic
608 * can underflow in the 100ms detection time frame
610 __setup_APIC_LVTT(0xffffffff, 0, 0);
612 /* Let the interrupts run */
615 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
620 /* Restore the real event handler */
621 global_clock_event->event_handler = real_handler;
623 /* Build delta t1-t2 as apic timer counts down */
624 delta = lapic_cal_t1 - lapic_cal_t2;
625 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
627 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
629 /* we trust the PM based calibration if possible */
630 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
633 /* Calculate the scaled math multiplication factor */
634 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
635 lapic_clockevent.shift);
636 lapic_clockevent.max_delta_ns =
637 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
638 lapic_clockevent.min_delta_ns =
639 clockevent_delta2ns(0xF, &lapic_clockevent);
641 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
643 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
644 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
645 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
649 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
651 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
652 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
655 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
657 calibration_result / (1000000 / HZ),
658 calibration_result % (1000000 / HZ));
661 * Do a sanity check on the APIC calibration result
663 if (calibration_result < (1000000 / HZ)) {
665 pr_warning("APIC frequency too slow, disabling apic timer\n");
669 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
672 * PM timer calibration failed or not turned on
673 * so lets try APIC timer based calibration
675 if (!pm_referenced) {
676 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
679 * Setup the apic timer manually
681 levt->event_handler = lapic_cal_handler;
682 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
683 lapic_cal_loops = -1;
685 /* Let the interrupts run */
688 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
691 /* Stop the lapic timer */
692 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
695 deltaj = lapic_cal_j2 - lapic_cal_j1;
696 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
698 /* Check, if the jiffies result is consistent */
699 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
700 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
702 levt->features |= CLOCK_EVT_FEAT_DUMMY;
706 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
707 pr_warning("APIC timer disabled due to verification failure\n");
715 * Setup the boot APIC
717 * Calibrate and verify the result.
719 void __init setup_boot_APIC_clock(void)
722 * The local apic timer can be disabled via the kernel
723 * commandline or from the CPU detection code. Register the lapic
724 * timer as a dummy clock event source on SMP systems, so the
725 * broadcast mechanism is used. On UP systems simply ignore it.
727 if (disable_apic_timer) {
728 pr_info("Disabling APIC timer\n");
729 /* No broadcast on UP ! */
730 if (num_possible_cpus() > 1) {
731 lapic_clockevent.mult = 1;
737 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
738 "calibrating APIC timer ...\n");
740 if (calibrate_APIC_clock()) {
741 /* No broadcast on UP ! */
742 if (num_possible_cpus() > 1)
748 * If nmi_watchdog is set to IO_APIC, we need the
749 * PIT/HPET going. Otherwise register lapic as a dummy
752 if (nmi_watchdog != NMI_IO_APIC)
753 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
755 pr_warning("APIC timer registered as dummy,"
756 " due to nmi_watchdog=%d!\n", nmi_watchdog);
758 /* Setup the lapic or request the broadcast */
762 void __cpuinit setup_secondary_APIC_clock(void)
768 * The guts of the apic timer interrupt
770 static void local_apic_timer_interrupt(void)
772 int cpu = smp_processor_id();
773 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
776 * Normally we should not be here till LAPIC has been initialized but
777 * in some cases like kdump, its possible that there is a pending LAPIC
778 * timer interrupt from previous kernel's context and is delivered in
779 * new kernel the moment interrupts are enabled.
781 * Interrupts are enabled early and LAPIC is setup much later, hence
782 * its possible that when we get here evt->event_handler is NULL.
783 * Check for event_handler being NULL and discard the interrupt as
786 if (!evt->event_handler) {
787 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
789 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
794 * the NMI deadlock-detector uses this.
796 inc_irq_stat(apic_timer_irqs);
798 evt->event_handler(evt);
802 * Local APIC timer interrupt. This is the most natural way for doing
803 * local interrupts, but local timer interrupts can be emulated by
804 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
806 * [ if a single-CPU system runs an SMP kernel then we call the local
807 * interrupt as well. Thus we cannot inline the local irq ... ]
809 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
811 struct pt_regs *old_regs = set_irq_regs(regs);
814 * NOTE! We'd better ACK the irq immediately,
815 * because timer handling can be slow.
819 * update_process_times() expects us to have done irq_enter().
820 * Besides, if we don't timer interrupts ignore the global
821 * interrupt lock, which is the WrongThing (tm) to do.
825 local_apic_timer_interrupt();
828 set_irq_regs(old_regs);
831 int setup_profiling_timer(unsigned int multiplier)
837 * Local APIC start and shutdown
841 * clear_local_APIC - shutdown the local APIC
843 * This is called, when a CPU is disabled and before rebooting, so the state of
844 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
845 * leftovers during boot.
847 void clear_local_APIC(void)
852 /* APIC hasn't been mapped yet */
853 if (!x2apic_mode && !apic_phys)
856 maxlvt = lapic_get_maxlvt();
858 * Masking an LVT entry can trigger a local APIC error
859 * if the vector is zero. Mask LVTERR first to prevent this.
862 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
863 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
866 * Careful: we have to set masks only first to deassert
867 * any level-triggered sources.
869 v = apic_read(APIC_LVTT);
870 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
871 v = apic_read(APIC_LVT0);
872 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
873 v = apic_read(APIC_LVT1);
874 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
876 v = apic_read(APIC_LVTPC);
877 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
880 /* lets not touch this if we didn't frob it */
881 #ifdef CONFIG_X86_THERMAL_VECTOR
883 v = apic_read(APIC_LVTTHMR);
884 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
887 #ifdef CONFIG_X86_MCE_INTEL
889 v = apic_read(APIC_LVTCMCI);
890 if (!(v & APIC_LVT_MASKED))
891 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
896 * Clean APIC state for other OSs:
898 apic_write(APIC_LVTT, APIC_LVT_MASKED);
899 apic_write(APIC_LVT0, APIC_LVT_MASKED);
900 apic_write(APIC_LVT1, APIC_LVT_MASKED);
902 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
904 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
906 /* Integrated APIC (!82489DX) ? */
907 if (lapic_is_integrated()) {
909 /* Clear ESR due to Pentium errata 3AP and 11AP */
910 apic_write(APIC_ESR, 0);
916 * disable_local_APIC - clear and disable the local APIC
918 void disable_local_APIC(void)
922 /* APIC hasn't been mapped yet */
929 * Disable APIC (implies clearing of registers
932 value = apic_read(APIC_SPIV);
933 value &= ~APIC_SPIV_APIC_ENABLED;
934 apic_write(APIC_SPIV, value);
938 * When LAPIC was disabled by the BIOS and enabled by the kernel,
939 * restore the disabled state.
941 if (enabled_via_apicbase) {
944 rdmsr(MSR_IA32_APICBASE, l, h);
945 l &= ~MSR_IA32_APICBASE_ENABLE;
946 wrmsr(MSR_IA32_APICBASE, l, h);
952 * If Linux enabled the LAPIC against the BIOS default disable it down before
953 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
954 * not power-off. Additionally clear all LVT entries before disable_local_APIC
955 * for the case where Linux didn't enable the LAPIC.
957 void lapic_shutdown(void)
961 if (!cpu_has_apic && !apic_from_smp_config())
964 local_irq_save(flags);
967 if (!enabled_via_apicbase)
971 disable_local_APIC();
974 local_irq_restore(flags);
978 * This is to verify that we're looking at a real local APIC.
979 * Check these against your board if the CPUs aren't getting
980 * started for no apparent reason.
982 int __init verify_local_APIC(void)
984 unsigned int reg0, reg1;
987 * The version register is read-only in a real APIC.
989 reg0 = apic_read(APIC_LVR);
990 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
991 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
992 reg1 = apic_read(APIC_LVR);
993 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
996 * The two version reads above should print the same
997 * numbers. If the second one is different, then we
998 * poke at a non-APIC.
1004 * Check if the version looks reasonably.
1006 reg1 = GET_APIC_VERSION(reg0);
1007 if (reg1 == 0x00 || reg1 == 0xff)
1009 reg1 = lapic_get_maxlvt();
1010 if (reg1 < 0x02 || reg1 == 0xff)
1014 * The ID register is read/write in a real APIC.
1016 reg0 = apic_read(APIC_ID);
1017 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1018 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1019 reg1 = apic_read(APIC_ID);
1020 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1021 apic_write(APIC_ID, reg0);
1022 if (reg1 != (reg0 ^ apic->apic_id_mask))
1026 * The next two are just to see if we have sane values.
1027 * They're only really relevant if we're in Virtual Wire
1028 * compatibility mode, but most boxes are anymore.
1030 reg0 = apic_read(APIC_LVT0);
1031 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1032 reg1 = apic_read(APIC_LVT1);
1033 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1039 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1041 void __init sync_Arb_IDs(void)
1044 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1047 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1053 apic_wait_icr_idle();
1055 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1056 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1057 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1061 * An initial setup of the virtual wire mode.
1063 void __init init_bsp_APIC(void)
1068 * Don't do the setup now if we have a SMP BIOS as the
1069 * through-I/O-APIC virtual wire mode might be active.
1071 if (smp_found_config || !cpu_has_apic)
1075 * Do not trust the local APIC being empty at bootup.
1082 value = apic_read(APIC_SPIV);
1083 value &= ~APIC_VECTOR_MASK;
1084 value |= APIC_SPIV_APIC_ENABLED;
1086 #ifdef CONFIG_X86_32
1087 /* This bit is reserved on P4/Xeon and should be cleared */
1088 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1089 (boot_cpu_data.x86 == 15))
1090 value &= ~APIC_SPIV_FOCUS_DISABLED;
1093 value |= APIC_SPIV_FOCUS_DISABLED;
1094 value |= SPURIOUS_APIC_VECTOR;
1095 apic_write(APIC_SPIV, value);
1098 * Set up the virtual wire mode.
1100 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1101 value = APIC_DM_NMI;
1102 if (!lapic_is_integrated()) /* 82489DX */
1103 value |= APIC_LVT_LEVEL_TRIGGER;
1104 apic_write(APIC_LVT1, value);
1107 static void __cpuinit lapic_setup_esr(void)
1109 unsigned int oldvalue, value, maxlvt;
1111 if (!lapic_is_integrated()) {
1112 pr_info("No ESR for 82489DX.\n");
1116 if (apic->disable_esr) {
1118 * Something untraceable is creating bad interrupts on
1119 * secondary quads ... for the moment, just leave the
1120 * ESR disabled - we can't do anything useful with the
1121 * errors anyway - mbligh
1123 pr_info("Leaving ESR disabled.\n");
1127 maxlvt = lapic_get_maxlvt();
1128 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1129 apic_write(APIC_ESR, 0);
1130 oldvalue = apic_read(APIC_ESR);
1132 /* enables sending errors */
1133 value = ERROR_APIC_VECTOR;
1134 apic_write(APIC_LVTERR, value);
1137 * spec says clear errors after enabling vector.
1140 apic_write(APIC_ESR, 0);
1141 value = apic_read(APIC_ESR);
1142 if (value != oldvalue)
1143 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1144 "vector: 0x%08x after: 0x%08x\n",
1150 * setup_local_APIC - setup the local APIC
1152 void __cpuinit setup_local_APIC(void)
1158 arch_disable_smp_support();
1162 #ifdef CONFIG_X86_32
1163 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1164 if (lapic_is_integrated() && apic->disable_esr) {
1165 apic_write(APIC_ESR, 0);
1166 apic_write(APIC_ESR, 0);
1167 apic_write(APIC_ESR, 0);
1168 apic_write(APIC_ESR, 0);
1171 perf_events_lapic_init();
1176 * Double-check whether this APIC is really registered.
1177 * This is meaningless in clustered apic mode, so we skip it.
1179 BUG_ON(!apic->apic_id_registered());
1182 * Intel recommends to set DFR, LDR and TPR before enabling
1183 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1184 * document number 292116). So here it goes...
1186 apic->init_apic_ldr();
1189 * Set Task Priority to 'accept all'. We never change this
1192 value = apic_read(APIC_TASKPRI);
1193 value &= ~APIC_TPRI_MASK;
1194 apic_write(APIC_TASKPRI, value);
1197 * After a crash, we no longer service the interrupts and a pending
1198 * interrupt from previous kernel might still have ISR bit set.
1200 * Most probably by now CPU has serviced that pending interrupt and
1201 * it might not have done the ack_APIC_irq() because it thought,
1202 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1203 * does not clear the ISR bit and cpu thinks it has already serivced
1204 * the interrupt. Hence a vector might get locked. It was noticed
1205 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1207 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1208 value = apic_read(APIC_ISR + i*0x10);
1209 for (j = 31; j >= 0; j--) {
1216 * Now that we are all set up, enable the APIC
1218 value = apic_read(APIC_SPIV);
1219 value &= ~APIC_VECTOR_MASK;
1223 value |= APIC_SPIV_APIC_ENABLED;
1225 #ifdef CONFIG_X86_32
1227 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1228 * certain networking cards. If high frequency interrupts are
1229 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1230 * entry is masked/unmasked at a high rate as well then sooner or
1231 * later IOAPIC line gets 'stuck', no more interrupts are received
1232 * from the device. If focus CPU is disabled then the hang goes
1235 * [ This bug can be reproduced easily with a level-triggered
1236 * PCI Ne2000 networking cards and PII/PIII processors, dual
1240 * Actually disabling the focus CPU check just makes the hang less
1241 * frequent as it makes the interrupt distributon model be more
1242 * like LRU than MRU (the short-term load is more even across CPUs).
1243 * See also the comment in end_level_ioapic_irq(). --macro
1247 * - enable focus processor (bit==0)
1248 * - 64bit mode always use processor focus
1249 * so no need to set it
1251 value &= ~APIC_SPIV_FOCUS_DISABLED;
1255 * Set spurious IRQ vector
1257 value |= SPURIOUS_APIC_VECTOR;
1258 apic_write(APIC_SPIV, value);
1261 * Set up LVT0, LVT1:
1263 * set up through-local-APIC on the BP's LINT0. This is not
1264 * strictly necessary in pure symmetric-IO mode, but sometimes
1265 * we delegate interrupts to the 8259A.
1268 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1270 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1271 if (!smp_processor_id() && (pic_mode || !value)) {
1272 value = APIC_DM_EXTINT;
1273 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1274 smp_processor_id());
1276 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1277 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1278 smp_processor_id());
1280 apic_write(APIC_LVT0, value);
1283 * only the BP should see the LINT1 NMI signal, obviously.
1285 if (!smp_processor_id())
1286 value = APIC_DM_NMI;
1288 value = APIC_DM_NMI | APIC_LVT_MASKED;
1289 if (!lapic_is_integrated()) /* 82489DX */
1290 value |= APIC_LVT_LEVEL_TRIGGER;
1291 apic_write(APIC_LVT1, value);
1295 #ifdef CONFIG_X86_MCE_INTEL
1296 /* Recheck CMCI information after local APIC is up on CPU #0 */
1297 if (smp_processor_id() == 0)
1302 void __cpuinit end_local_APIC_setup(void)
1306 #ifdef CONFIG_X86_32
1309 /* Disable the local apic timer */
1310 value = apic_read(APIC_LVTT);
1311 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1312 apic_write(APIC_LVTT, value);
1316 setup_apic_nmi_watchdog(NULL);
1320 #ifdef CONFIG_X86_X2APIC
1321 void check_x2apic(void)
1323 if (x2apic_enabled()) {
1324 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1325 x2apic_preenabled = x2apic_mode = 1;
1329 void enable_x2apic(void)
1336 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1337 if (!(msr & X2APIC_ENABLE)) {
1338 printk_once(KERN_INFO "Enabling x2apic\n");
1339 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1342 #endif /* CONFIG_X86_X2APIC */
1344 int __init enable_IR(void)
1346 #ifdef CONFIG_INTR_REMAP
1347 if (!intr_remapping_supported()) {
1348 pr_debug("intr-remapping not supported\n");
1352 if (!x2apic_preenabled && skip_ioapic_setup) {
1353 pr_info("Skipped enabling intr-remap because of skipping "
1358 if (enable_intr_remapping(x2apic_supported()))
1361 pr_info("Enabled Interrupt-remapping\n");
1369 void __init enable_IR_x2apic(void)
1371 unsigned long flags;
1372 struct IO_APIC_route_entry **ioapic_entries = NULL;
1373 int ret, x2apic_enabled = 0;
1374 int dmar_table_init_ret;
1376 dmar_table_init_ret = dmar_table_init();
1377 if (dmar_table_init_ret && !x2apic_supported())
1380 ioapic_entries = alloc_ioapic_entries();
1381 if (!ioapic_entries) {
1382 pr_err("Allocate ioapic_entries failed\n");
1386 ret = save_IO_APIC_setup(ioapic_entries);
1388 pr_info("Saving IO-APIC state failed: %d\n", ret);
1392 local_irq_save(flags);
1393 legacy_pic->mask_all();
1394 mask_IO_APIC_setup(ioapic_entries);
1396 if (dmar_table_init_ret)
1402 /* IR is required if there is APIC ID > 255 even when running
1405 if (max_physical_apicid > 255 || !kvm_para_available())
1408 * without IR all CPUs can be addressed by IOAPIC/MSI
1409 * only in physical mode
1411 x2apic_force_phys();
1416 if (x2apic_supported() && !x2apic_mode) {
1419 pr_info("Enabled x2apic\n");
1423 if (!ret) /* IR enabling failed */
1424 restore_IO_APIC_setup(ioapic_entries);
1425 legacy_pic->restore_mask();
1426 local_irq_restore(flags);
1430 free_ioapic_entries(ioapic_entries);
1435 if (x2apic_preenabled)
1436 panic("x2apic: enabled by BIOS but kernel init failed.");
1437 else if (cpu_has_x2apic)
1438 pr_info("Not enabling x2apic, Intr-remapping init failed.\n");
1441 #ifdef CONFIG_X86_64
1443 * Detect and enable local APICs on non-SMP boards.
1444 * Original code written by Keir Fraser.
1445 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1446 * not correctly set up (usually the APIC timer won't work etc.)
1448 static int __init detect_init_APIC(void)
1450 if (!cpu_has_apic) {
1451 pr_info("No local APIC present\n");
1455 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1460 * Detect and initialize APIC
1462 static int __init detect_init_APIC(void)
1466 /* Disabled by kernel option? */
1470 switch (boot_cpu_data.x86_vendor) {
1471 case X86_VENDOR_AMD:
1472 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1473 (boot_cpu_data.x86 >= 15))
1476 case X86_VENDOR_INTEL:
1477 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1478 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1485 if (!cpu_has_apic) {
1487 * Over-ride BIOS and try to enable the local APIC only if
1488 * "lapic" specified.
1490 if (!force_enable_local_apic) {
1491 pr_info("Local APIC disabled by BIOS -- "
1492 "you can enable it with \"lapic\"\n");
1496 * Some BIOSes disable the local APIC in the APIC_BASE
1497 * MSR. This can only be done in software for Intel P6 or later
1498 * and AMD K7 (Model > 1) or later.
1500 rdmsr(MSR_IA32_APICBASE, l, h);
1501 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1502 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1503 l &= ~MSR_IA32_APICBASE_BASE;
1504 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1505 wrmsr(MSR_IA32_APICBASE, l, h);
1506 enabled_via_apicbase = 1;
1510 * The APIC feature bit should now be enabled
1513 features = cpuid_edx(1);
1514 if (!(features & (1 << X86_FEATURE_APIC))) {
1515 pr_warning("Could not enable APIC!\n");
1518 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1519 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1521 /* The BIOS may have set up the APIC at some other address */
1522 rdmsr(MSR_IA32_APICBASE, l, h);
1523 if (l & MSR_IA32_APICBASE_ENABLE)
1524 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1526 pr_info("Found and enabled local APIC!\n");
1533 pr_info("No local APIC present or hardware disabled\n");
1538 #ifdef CONFIG_X86_64
1539 void __init early_init_lapic_mapping(void)
1542 * If no local APIC can be found then go out
1543 * : it means there is no mpatable and MADT
1545 if (!smp_found_config)
1548 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
1549 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1550 APIC_BASE, mp_lapic_addr);
1553 * Fetch the APIC ID of the BSP in case we have a
1554 * default configuration (or the MP table is broken).
1556 boot_cpu_physical_apicid = read_apic_id();
1561 * init_apic_mappings - initialize APIC mappings
1563 void __init init_apic_mappings(void)
1565 unsigned int new_apicid;
1568 boot_cpu_physical_apicid = read_apic_id();
1572 /* If no local APIC can be found return early */
1573 if (!smp_found_config && detect_init_APIC()) {
1574 /* lets NOP'ify apic operations */
1575 pr_info("APIC: disable apic facility\n");
1578 apic_phys = mp_lapic_addr;
1581 * acpi lapic path already maps that address in
1582 * acpi_register_lapic_address()
1585 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1587 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
1588 APIC_BASE, apic_phys);
1592 * Fetch the APIC ID of the BSP in case we have a
1593 * default configuration (or the MP table is broken).
1595 new_apicid = read_apic_id();
1596 if (boot_cpu_physical_apicid != new_apicid) {
1597 boot_cpu_physical_apicid = new_apicid;
1599 * yeah -- we lie about apic_version
1600 * in case if apic was disabled via boot option
1601 * but it's not a problem for SMP compiled kernel
1602 * since smp_sanity_check is prepared for such a case
1603 * and disable smp mode
1605 apic_version[new_apicid] =
1606 GET_APIC_VERSION(apic_read(APIC_LVR));
1611 * This initializes the IO-APIC and APIC hardware if this is
1614 int apic_version[MAX_APICS];
1616 int __init APIC_init_uniprocessor(void)
1619 pr_info("Apic disabled\n");
1622 #ifdef CONFIG_X86_64
1623 if (!cpu_has_apic) {
1625 pr_info("Apic disabled by BIOS\n");
1629 if (!smp_found_config && !cpu_has_apic)
1633 * Complain if the BIOS pretends there is one.
1635 if (!cpu_has_apic &&
1636 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1637 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1638 boot_cpu_physical_apicid);
1645 default_setup_apic_routing();
1648 verify_local_APIC();
1651 #ifdef CONFIG_X86_64
1652 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1655 * Hack: In case of kdump, after a crash, kernel might be booting
1656 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1657 * might be zero if read from MP tables. Get it from LAPIC.
1659 # ifdef CONFIG_CRASH_DUMP
1660 boot_cpu_physical_apicid = read_apic_id();
1663 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1666 #ifdef CONFIG_X86_IO_APIC
1668 * Now enable IO-APICs, actually call clear_IO_APIC
1669 * We need clear_IO_APIC before enabling error vector
1671 if (!skip_ioapic_setup && nr_ioapics)
1675 end_local_APIC_setup();
1677 #ifdef CONFIG_X86_IO_APIC
1678 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1682 localise_nmi_watchdog();
1685 localise_nmi_watchdog();
1688 x86_init.timers.setup_percpu_clockev();
1689 #ifdef CONFIG_X86_64
1690 check_nmi_watchdog();
1697 * Local APIC interrupts
1701 * This interrupt should _never_ happen with our APIC/SMP architecture
1703 void smp_spurious_interrupt(struct pt_regs *regs)
1710 * Check if this really is a spurious interrupt and ACK it
1711 * if it is a vectored one. Just in case...
1712 * Spurious interrupts should not be ACKed.
1714 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1715 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1718 inc_irq_stat(irq_spurious_count);
1720 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1721 pr_info("spurious APIC interrupt on CPU#%d, "
1722 "should never happen.\n", smp_processor_id());
1727 * This interrupt should never happen with our APIC/SMP architecture
1729 void smp_error_interrupt(struct pt_regs *regs)
1735 /* First tickle the hardware, only then report what went on. -- REW */
1736 v = apic_read(APIC_ESR);
1737 apic_write(APIC_ESR, 0);
1738 v1 = apic_read(APIC_ESR);
1740 atomic_inc(&irq_err_count);
1743 * Here is what the APIC error bits mean:
1745 * 1: Receive CS error
1746 * 2: Send accept error
1747 * 3: Receive accept error
1749 * 5: Send illegal vector
1750 * 6: Received illegal vector
1751 * 7: Illegal register address
1753 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1754 smp_processor_id(), v , v1);
1759 * connect_bsp_APIC - attach the APIC to the interrupt system
1761 void __init connect_bsp_APIC(void)
1763 #ifdef CONFIG_X86_32
1766 * Do not trust the local APIC being empty at bootup.
1770 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1771 * local APIC to INT and NMI lines.
1773 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1774 "enabling APIC mode.\n");
1778 if (apic->enable_apic_mode)
1779 apic->enable_apic_mode();
1783 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1784 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1786 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1789 void disconnect_bsp_APIC(int virt_wire_setup)
1793 #ifdef CONFIG_X86_32
1796 * Put the board back into PIC mode (has an effect only on
1797 * certain older boards). Note that APIC interrupts, including
1798 * IPIs, won't work beyond this point! The only exception are
1801 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1802 "entering PIC mode.\n");
1808 /* Go back to Virtual Wire compatibility mode */
1810 /* For the spurious interrupt use vector F, and enable it */
1811 value = apic_read(APIC_SPIV);
1812 value &= ~APIC_VECTOR_MASK;
1813 value |= APIC_SPIV_APIC_ENABLED;
1815 apic_write(APIC_SPIV, value);
1817 if (!virt_wire_setup) {
1819 * For LVT0 make it edge triggered, active high,
1820 * external and enabled
1822 value = apic_read(APIC_LVT0);
1823 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1824 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1825 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1826 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1827 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1828 apic_write(APIC_LVT0, value);
1831 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1835 * For LVT1 make it edge triggered, active high,
1838 value = apic_read(APIC_LVT1);
1839 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1840 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1841 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1842 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1843 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1844 apic_write(APIC_LVT1, value);
1847 void __cpuinit generic_processor_info(int apicid, int version)
1854 if (version == 0x0) {
1855 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1856 "fixing up to 0x10. (tell your hw vendor)\n",
1860 apic_version[apicid] = version;
1862 if (num_processors >= nr_cpu_ids) {
1863 int max = nr_cpu_ids;
1864 int thiscpu = max + disabled_cpus;
1867 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1868 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1875 cpu = cpumask_next_zero(-1, cpu_present_mask);
1877 if (version != apic_version[boot_cpu_physical_apicid])
1879 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1880 apic_version[boot_cpu_physical_apicid], cpu, version);
1882 physid_set(apicid, phys_cpu_present_map);
1883 if (apicid == boot_cpu_physical_apicid) {
1885 * x86_bios_cpu_apicid is required to have processors listed
1886 * in same order as logical cpu numbers. Hence the first
1887 * entry is BSP, and so on.
1891 if (apicid > max_physical_apicid)
1892 max_physical_apicid = apicid;
1894 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1895 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1896 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1899 set_cpu_possible(cpu, true);
1900 set_cpu_present(cpu, true);
1903 int hard_smp_processor_id(void)
1905 return read_apic_id();
1908 void default_init_apic_ldr(void)
1912 apic_write(APIC_DFR, APIC_DFR_VALUE);
1913 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
1914 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1915 apic_write(APIC_LDR, val);
1918 #ifdef CONFIG_X86_32
1919 int default_apicid_to_node(int logical_apicid)
1922 return apicid_2_node[hard_smp_processor_id()];
1936 * 'active' is true if the local APIC was enabled by us and
1937 * not the BIOS; this signifies that we are also responsible
1938 * for disabling it before entering apm/acpi suspend
1941 /* r/w apic fields */
1942 unsigned int apic_id;
1943 unsigned int apic_taskpri;
1944 unsigned int apic_ldr;
1945 unsigned int apic_dfr;
1946 unsigned int apic_spiv;
1947 unsigned int apic_lvtt;
1948 unsigned int apic_lvtpc;
1949 unsigned int apic_lvt0;
1950 unsigned int apic_lvt1;
1951 unsigned int apic_lvterr;
1952 unsigned int apic_tmict;
1953 unsigned int apic_tdcr;
1954 unsigned int apic_thmr;
1957 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1959 unsigned long flags;
1962 if (!apic_pm_state.active)
1965 maxlvt = lapic_get_maxlvt();
1967 apic_pm_state.apic_id = apic_read(APIC_ID);
1968 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1969 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1970 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1971 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1972 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1974 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1975 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1976 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1977 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1978 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1979 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1980 #ifdef CONFIG_X86_THERMAL_VECTOR
1982 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1985 local_irq_save(flags);
1986 disable_local_APIC();
1988 if (intr_remapping_enabled)
1989 disable_intr_remapping();
1991 local_irq_restore(flags);
1995 static int lapic_resume(struct sys_device *dev)
1998 unsigned long flags;
2001 struct IO_APIC_route_entry **ioapic_entries = NULL;
2003 if (!apic_pm_state.active)
2006 local_irq_save(flags);
2007 if (intr_remapping_enabled) {
2008 ioapic_entries = alloc_ioapic_entries();
2009 if (!ioapic_entries) {
2010 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2015 ret = save_IO_APIC_setup(ioapic_entries);
2017 WARN(1, "Saving IO-APIC state failed: %d\n", ret);
2018 free_ioapic_entries(ioapic_entries);
2022 mask_IO_APIC_setup(ioapic_entries);
2023 legacy_pic->mask_all();
2030 * Make sure the APICBASE points to the right address
2032 * FIXME! This will be wrong if we ever support suspend on
2033 * SMP! We'll need to do this as part of the CPU restore!
2035 rdmsr(MSR_IA32_APICBASE, l, h);
2036 l &= ~MSR_IA32_APICBASE_BASE;
2037 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2038 wrmsr(MSR_IA32_APICBASE, l, h);
2041 maxlvt = lapic_get_maxlvt();
2042 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2043 apic_write(APIC_ID, apic_pm_state.apic_id);
2044 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2045 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2046 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2047 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2048 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2049 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2050 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2052 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2055 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2056 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2057 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2058 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2059 apic_write(APIC_ESR, 0);
2060 apic_read(APIC_ESR);
2061 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2062 apic_write(APIC_ESR, 0);
2063 apic_read(APIC_ESR);
2065 if (intr_remapping_enabled) {
2066 reenable_intr_remapping(x2apic_mode);
2067 legacy_pic->restore_mask();
2068 restore_IO_APIC_setup(ioapic_entries);
2069 free_ioapic_entries(ioapic_entries);
2072 local_irq_restore(flags);
2078 * This device has no shutdown method - fully functioning local APICs
2079 * are needed on every CPU up until machine_halt/restart/poweroff.
2082 static struct sysdev_class lapic_sysclass = {
2084 .resume = lapic_resume,
2085 .suspend = lapic_suspend,
2088 static struct sys_device device_lapic = {
2090 .cls = &lapic_sysclass,
2093 static void __cpuinit apic_pm_activate(void)
2095 apic_pm_state.active = 1;
2098 static int __init init_lapic_sysfs(void)
2104 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2106 error = sysdev_class_register(&lapic_sysclass);
2108 error = sysdev_register(&device_lapic);
2112 /* local apic needs to resume before other devices access its registers. */
2113 core_initcall(init_lapic_sysfs);
2115 #else /* CONFIG_PM */
2117 static void apic_pm_activate(void) { }
2119 #endif /* CONFIG_PM */
2121 #ifdef CONFIG_X86_64
2123 static int __cpuinit apic_cluster_num(void)
2125 int i, clusters, zeros;
2127 u16 *bios_cpu_apicid;
2128 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2130 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2131 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2133 for (i = 0; i < nr_cpu_ids; i++) {
2134 /* are we being called early in kernel startup? */
2135 if (bios_cpu_apicid) {
2136 id = bios_cpu_apicid[i];
2137 } else if (i < nr_cpu_ids) {
2139 id = per_cpu(x86_bios_cpu_apicid, i);
2145 if (id != BAD_APICID)
2146 __set_bit(APIC_CLUSTERID(id), clustermap);
2149 /* Problem: Partially populated chassis may not have CPUs in some of
2150 * the APIC clusters they have been allocated. Only present CPUs have
2151 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2152 * Since clusters are allocated sequentially, count zeros only if
2153 * they are bounded by ones.
2157 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2158 if (test_bit(i, clustermap)) {
2159 clusters += 1 + zeros;
2168 static int __cpuinitdata multi_checked;
2169 static int __cpuinitdata multi;
2171 static int __cpuinit set_multi(const struct dmi_system_id *d)
2175 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2180 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
2182 .callback = set_multi,
2183 .ident = "IBM System Summit2",
2185 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2186 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2192 static void __cpuinit dmi_check_multi(void)
2197 dmi_check_system(multi_dmi_table);
2202 * apic_is_clustered_box() -- Check if we can expect good TSC
2204 * Thus far, the major user of this is IBM's Summit2 series:
2205 * Clustered boxes may have unsynced TSC problems if they are
2207 * Use DMI to check them
2209 __cpuinit int apic_is_clustered_box(void)
2219 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2220 * not guaranteed to be synced between boards
2222 if (apic_cluster_num() > 1)
2230 * APIC command line parameters
2232 static int __init setup_disableapic(char *arg)
2235 setup_clear_cpu_cap(X86_FEATURE_APIC);
2238 early_param("disableapic", setup_disableapic);
2240 /* same as disableapic, for compatibility */
2241 static int __init setup_nolapic(char *arg)
2243 return setup_disableapic(arg);
2245 early_param("nolapic", setup_nolapic);
2247 static int __init parse_lapic_timer_c2_ok(char *arg)
2249 local_apic_timer_c2_ok = 1;
2252 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2254 static int __init parse_disable_apic_timer(char *arg)
2256 disable_apic_timer = 1;
2259 early_param("noapictimer", parse_disable_apic_timer);
2261 static int __init parse_nolapic_timer(char *arg)
2263 disable_apic_timer = 1;
2266 early_param("nolapic_timer", parse_nolapic_timer);
2268 static int __init apic_set_verbosity(char *arg)
2271 #ifdef CONFIG_X86_64
2272 skip_ioapic_setup = 0;
2278 if (strcmp("debug", arg) == 0)
2279 apic_verbosity = APIC_DEBUG;
2280 else if (strcmp("verbose", arg) == 0)
2281 apic_verbosity = APIC_VERBOSE;
2283 pr_warning("APIC Verbosity level %s not recognised"
2284 " use apic=verbose or apic=debug\n", arg);
2290 early_param("apic", apic_set_verbosity);
2292 static int __init lapic_insert_resource(void)
2297 /* Put local APIC into the resource map. */
2298 lapic_resource.start = apic_phys;
2299 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2300 insert_resource(&iomem_resource, &lapic_resource);
2306 * need call insert after e820_reserve_resources()
2307 * that is using request_resource
2309 late_initcall(lapic_insert_resource);