2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
38 #include <asm/perf_event.h>
39 #include <asm/x86_init.h>
40 #include <asm/pgalloc.h>
41 #include <linux/atomic.h>
42 #include <asm/mpspec.h>
43 #include <asm/i8259.h>
44 #include <asm/proto.h>
46 #include <asm/io_apic.h>
55 #include <asm/hypervisor.h>
57 unsigned int num_processors;
59 unsigned disabled_cpus __cpuinitdata;
61 /* Processor that is doing the boot up */
62 unsigned int boot_cpu_physical_apicid = -1U;
65 * The highest APIC ID seen during enumeration.
67 unsigned int max_physical_apicid;
70 * Bitmask of physically existing CPUs:
72 physid_mask_t phys_cpu_present_map;
75 * Map cpu index to physical APIC ID
77 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
78 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
85 * On x86_32, the mapping between cpu and logical apicid may vary
86 * depending on apic in use. The following early percpu variable is
87 * used for the mapping. This is where the behaviors of x86_64 and 32
88 * actually diverge. Let's keep it ugly for now.
90 DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID);
93 * Knob to control our willingness to enable the local APIC.
97 static int force_enable_local_apic __initdata;
99 * APIC command line parameters
101 static int __init parse_lapic(char *arg)
103 force_enable_local_apic = 1;
106 early_param("lapic", parse_lapic);
107 /* Local APIC was disabled by the BIOS and enabled by the kernel */
108 static int enabled_via_apicbase;
111 * Handle interrupt mode configuration register (IMCR).
112 * This register controls whether the interrupt signals
113 * that reach the BSP come from the master PIC or from the
114 * local APIC. Before entering Symmetric I/O Mode, either
115 * the BIOS or the operating system must switch out of
116 * PIC Mode by changing the IMCR.
118 static inline void imcr_pic_to_apic(void)
120 /* select IMCR register */
122 /* NMI and 8259 INTR go through APIC */
126 static inline void imcr_apic_to_pic(void)
128 /* select IMCR register */
130 /* NMI and 8259 INTR go directly to BSP */
136 static int apic_calibrate_pmtmr __initdata;
137 static __init int setup_apicpmtimer(char *s)
139 apic_calibrate_pmtmr = 1;
143 __setup("apicpmtimer", setup_apicpmtimer);
147 #ifdef CONFIG_X86_X2APIC
148 /* x2apic enabled before OS handover */
149 static int x2apic_preenabled;
150 static __init int setup_nox2apic(char *str)
152 if (x2apic_enabled()) {
153 pr_warning("Bios already enabled x2apic, "
154 "can't enforce nox2apic");
158 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
161 early_param("nox2apic", setup_nox2apic);
164 unsigned long mp_lapic_addr;
166 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
167 static int disable_apic_timer __initdata;
168 /* Local APIC timer works in C2 */
169 int local_apic_timer_c2_ok;
170 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
172 int first_system_vector = 0xfe;
175 * Debug level, exported for io_apic.c
177 unsigned int apic_verbosity;
181 /* Have we found an MP table */
182 int smp_found_config;
184 static struct resource lapic_resource = {
185 .name = "Local APIC",
186 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
189 static unsigned int calibration_result;
191 static void apic_pm_activate(void);
193 static unsigned long apic_phys;
196 * Get the LAPIC version
198 static inline int lapic_get_version(void)
200 return GET_APIC_VERSION(apic_read(APIC_LVR));
204 * Check, if the APIC is integrated or a separate chip
206 static inline int lapic_is_integrated(void)
211 return APIC_INTEGRATED(lapic_get_version());
216 * Check, whether this is a modern or a first generation APIC
218 static int modern_apic(void)
220 /* AMD systems use old APIC versions, so check the CPU */
221 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
222 boot_cpu_data.x86 >= 0xf)
224 return lapic_get_version() >= 0x14;
228 * right after this call apic become NOOP driven
229 * so apic->write/read doesn't do anything
231 static void __init apic_disable(void)
233 pr_info("APIC: switched to apic NOOP\n");
237 void native_apic_wait_icr_idle(void)
239 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
243 u32 native_safe_apic_wait_icr_idle(void)
250 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
254 } while (timeout++ < 1000);
259 void native_apic_icr_write(u32 low, u32 id)
261 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
262 apic_write(APIC_ICR, low);
265 u64 native_apic_icr_read(void)
269 icr2 = apic_read(APIC_ICR2);
270 icr1 = apic_read(APIC_ICR);
272 return icr1 | ((u64)icr2 << 32);
277 * get_physical_broadcast - Get number of physical broadcast IDs
279 int get_physical_broadcast(void)
281 return modern_apic() ? 0xff : 0xf;
286 * lapic_get_maxlvt - get the maximum number of local vector table entries
288 int lapic_get_maxlvt(void)
292 v = apic_read(APIC_LVR);
294 * - we always have APIC integrated on 64bit mode
295 * - 82489DXs do not report # of LVT entries
297 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
305 #define APIC_DIVISOR 16
308 * This function sets up the local APIC timer, with a timeout of
309 * 'clocks' APIC bus clock. During calibration we actually call
310 * this function twice on the boot CPU, once with a bogus timeout
311 * value, second time for real. The other (noncalibrating) CPUs
312 * call this function only once, with the real, calibrated value.
314 * We do reads before writes even if unnecessary, to get around the
315 * P5 APIC double write bug.
317 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
319 unsigned int lvtt_value, tmp_value;
321 lvtt_value = LOCAL_TIMER_VECTOR;
323 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
324 if (!lapic_is_integrated())
325 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
328 lvtt_value |= APIC_LVT_MASKED;
330 apic_write(APIC_LVTT, lvtt_value);
335 tmp_value = apic_read(APIC_TDCR);
336 apic_write(APIC_TDCR,
337 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
341 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
345 * Setup extended LVT, AMD specific
347 * Software should use the LVT offsets the BIOS provides. The offsets
348 * are determined by the subsystems using it like those for MCE
349 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
350 * are supported. Beginning with family 10h at least 4 offsets are
353 * Since the offsets must be consistent for all cores, we keep track
354 * of the LVT offsets in software and reserve the offset for the same
355 * vector also to be used on other cores. An offset is freed by
356 * setting the entry to APIC_EILVT_MASKED.
358 * If the BIOS is right, there should be no conflicts. Otherwise a
359 * "[Firmware Bug]: ..." error message is generated. However, if
360 * software does not properly determines the offsets, it is not
361 * necessarily a BIOS bug.
364 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
366 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
368 return (old & APIC_EILVT_MASKED)
369 || (new == APIC_EILVT_MASKED)
370 || ((new & ~APIC_EILVT_MASKED) == old);
373 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
375 unsigned int rsvd; /* 0: uninitialized */
377 if (offset >= APIC_EILVT_NR_MAX)
380 rsvd = atomic_read(&eilvt_offsets[offset]) & ~APIC_EILVT_MASKED;
383 !eilvt_entry_is_changeable(rsvd, new))
384 /* may not change if vectors are different */
386 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
387 } while (rsvd != new);
393 * If mask=1, the LVT entry does not generate interrupts while mask=0
394 * enables the vector. See also the BKDGs. Must be called with
395 * preemption disabled.
398 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
400 unsigned long reg = APIC_EILVTn(offset);
401 unsigned int new, old, reserved;
403 new = (mask << 16) | (msg_type << 8) | vector;
404 old = apic_read(reg);
405 reserved = reserve_eilvt_offset(offset, new);
407 if (reserved != new) {
408 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
409 "vector 0x%x, but the register is already in use for "
410 "vector 0x%x on another cpu\n",
411 smp_processor_id(), reg, offset, new, reserved);
415 if (!eilvt_entry_is_changeable(old, new)) {
416 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
417 "vector 0x%x, but the register is already in use for "
418 "vector 0x%x on this cpu\n",
419 smp_processor_id(), reg, offset, new, old);
423 apic_write(reg, new);
427 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
430 * Program the next event, relative to now
432 static int lapic_next_event(unsigned long delta,
433 struct clock_event_device *evt)
435 apic_write(APIC_TMICT, delta);
440 * Setup the lapic timer in periodic or oneshot mode
442 static void lapic_timer_setup(enum clock_event_mode mode,
443 struct clock_event_device *evt)
448 /* Lapic used as dummy for broadcast ? */
449 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
452 local_irq_save(flags);
455 case CLOCK_EVT_MODE_PERIODIC:
456 case CLOCK_EVT_MODE_ONESHOT:
457 __setup_APIC_LVTT(calibration_result,
458 mode != CLOCK_EVT_MODE_PERIODIC, 1);
460 case CLOCK_EVT_MODE_UNUSED:
461 case CLOCK_EVT_MODE_SHUTDOWN:
462 v = apic_read(APIC_LVTT);
463 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
464 apic_write(APIC_LVTT, v);
465 apic_write(APIC_TMICT, 0);
467 case CLOCK_EVT_MODE_RESUME:
468 /* Nothing to do here */
472 local_irq_restore(flags);
476 * Local APIC timer broadcast function
478 static void lapic_timer_broadcast(const struct cpumask *mask)
481 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
487 * The local apic timer can be used for any function which is CPU local.
489 static struct clock_event_device lapic_clockevent = {
491 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
492 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
494 .set_mode = lapic_timer_setup,
495 .set_next_event = lapic_next_event,
496 .broadcast = lapic_timer_broadcast,
500 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
503 * Setup the local APIC timer for this CPU. Copy the initialized values
504 * of the boot CPU and register the clock event in the framework.
506 static void __cpuinit setup_APIC_timer(void)
508 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
510 if (this_cpu_has(X86_FEATURE_ARAT)) {
511 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
512 /* Make LAPIC timer preferrable over percpu HPET */
513 lapic_clockevent.rating = 150;
516 memcpy(levt, &lapic_clockevent, sizeof(*levt));
517 levt->cpumask = cpumask_of(smp_processor_id());
519 clockevents_register_device(levt);
523 * In this functions we calibrate APIC bus clocks to the external timer.
525 * We want to do the calibration only once since we want to have local timer
526 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
529 * This was previously done by reading the PIT/HPET and waiting for a wrap
530 * around to find out, that a tick has elapsed. I have a box, where the PIT
531 * readout is broken, so it never gets out of the wait loop again. This was
532 * also reported by others.
534 * Monitoring the jiffies value is inaccurate and the clockevents
535 * infrastructure allows us to do a simple substitution of the interrupt
538 * The calibration routine also uses the pm_timer when possible, as the PIT
539 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
540 * back to normal later in the boot process).
543 #define LAPIC_CAL_LOOPS (HZ/10)
545 static __initdata int lapic_cal_loops = -1;
546 static __initdata long lapic_cal_t1, lapic_cal_t2;
547 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
548 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
549 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
552 * Temporary interrupt handler.
554 static void __init lapic_cal_handler(struct clock_event_device *dev)
556 unsigned long long tsc = 0;
557 long tapic = apic_read(APIC_TMCCT);
558 unsigned long pm = acpi_pm_read_early();
563 switch (lapic_cal_loops++) {
565 lapic_cal_t1 = tapic;
566 lapic_cal_tsc1 = tsc;
568 lapic_cal_j1 = jiffies;
571 case LAPIC_CAL_LOOPS:
572 lapic_cal_t2 = tapic;
573 lapic_cal_tsc2 = tsc;
574 if (pm < lapic_cal_pm1)
575 pm += ACPI_PM_OVRRUN;
577 lapic_cal_j2 = jiffies;
583 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
585 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
586 const long pm_thresh = pm_100ms / 100;
590 #ifndef CONFIG_X86_PM_TIMER
594 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
596 /* Check, if the PM timer is available */
600 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
602 if (deltapm > (pm_100ms - pm_thresh) &&
603 deltapm < (pm_100ms + pm_thresh)) {
604 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
608 res = (((u64)deltapm) * mult) >> 22;
609 do_div(res, 1000000);
610 pr_warning("APIC calibration not consistent "
611 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
613 /* Correct the lapic counter value */
614 res = (((u64)(*delta)) * pm_100ms);
615 do_div(res, deltapm);
616 pr_info("APIC delta adjusted to PM-Timer: "
617 "%lu (%ld)\n", (unsigned long)res, *delta);
620 /* Correct the tsc counter value */
622 res = (((u64)(*deltatsc)) * pm_100ms);
623 do_div(res, deltapm);
624 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
625 "PM-Timer: %lu (%ld)\n",
626 (unsigned long)res, *deltatsc);
627 *deltatsc = (long)res;
633 static int __init calibrate_APIC_clock(void)
635 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
636 void (*real_handler)(struct clock_event_device *dev);
637 unsigned long deltaj;
638 long delta, deltatsc;
639 int pm_referenced = 0;
643 /* Replace the global interrupt handler */
644 real_handler = global_clock_event->event_handler;
645 global_clock_event->event_handler = lapic_cal_handler;
648 * Setup the APIC counter to maximum. There is no way the lapic
649 * can underflow in the 100ms detection time frame
651 __setup_APIC_LVTT(0xffffffff, 0, 0);
653 /* Let the interrupts run */
656 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
661 /* Restore the real event handler */
662 global_clock_event->event_handler = real_handler;
664 /* Build delta t1-t2 as apic timer counts down */
665 delta = lapic_cal_t1 - lapic_cal_t2;
666 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
668 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
670 /* we trust the PM based calibration if possible */
671 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
674 /* Calculate the scaled math multiplication factor */
675 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
676 lapic_clockevent.shift);
677 lapic_clockevent.max_delta_ns =
678 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
679 lapic_clockevent.min_delta_ns =
680 clockevent_delta2ns(0xF, &lapic_clockevent);
682 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
684 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
685 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
686 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
690 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
692 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
693 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
696 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
698 calibration_result / (1000000 / HZ),
699 calibration_result % (1000000 / HZ));
702 * Do a sanity check on the APIC calibration result
704 if (calibration_result < (1000000 / HZ)) {
706 pr_warning("APIC frequency too slow, disabling apic timer\n");
710 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
713 * PM timer calibration failed or not turned on
714 * so lets try APIC timer based calibration
716 if (!pm_referenced) {
717 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
720 * Setup the apic timer manually
722 levt->event_handler = lapic_cal_handler;
723 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
724 lapic_cal_loops = -1;
726 /* Let the interrupts run */
729 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
732 /* Stop the lapic timer */
733 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
736 deltaj = lapic_cal_j2 - lapic_cal_j1;
737 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
739 /* Check, if the jiffies result is consistent */
740 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
741 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
743 levt->features |= CLOCK_EVT_FEAT_DUMMY;
747 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
748 pr_warning("APIC timer disabled due to verification failure\n");
756 * Setup the boot APIC
758 * Calibrate and verify the result.
760 void __init setup_boot_APIC_clock(void)
763 * The local apic timer can be disabled via the kernel
764 * commandline or from the CPU detection code. Register the lapic
765 * timer as a dummy clock event source on SMP systems, so the
766 * broadcast mechanism is used. On UP systems simply ignore it.
768 if (disable_apic_timer) {
769 pr_info("Disabling APIC timer\n");
770 /* No broadcast on UP ! */
771 if (num_possible_cpus() > 1) {
772 lapic_clockevent.mult = 1;
778 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
779 "calibrating APIC timer ...\n");
781 if (calibrate_APIC_clock()) {
782 /* No broadcast on UP ! */
783 if (num_possible_cpus() > 1)
789 * If nmi_watchdog is set to IO_APIC, we need the
790 * PIT/HPET going. Otherwise register lapic as a dummy
793 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
795 /* Setup the lapic or request the broadcast */
799 void __cpuinit setup_secondary_APIC_clock(void)
805 * The guts of the apic timer interrupt
807 static void local_apic_timer_interrupt(void)
809 int cpu = smp_processor_id();
810 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
813 * Normally we should not be here till LAPIC has been initialized but
814 * in some cases like kdump, its possible that there is a pending LAPIC
815 * timer interrupt from previous kernel's context and is delivered in
816 * new kernel the moment interrupts are enabled.
818 * Interrupts are enabled early and LAPIC is setup much later, hence
819 * its possible that when we get here evt->event_handler is NULL.
820 * Check for event_handler being NULL and discard the interrupt as
823 if (!evt->event_handler) {
824 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
826 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
831 * the NMI deadlock-detector uses this.
833 inc_irq_stat(apic_timer_irqs);
835 evt->event_handler(evt);
839 * Local APIC timer interrupt. This is the most natural way for doing
840 * local interrupts, but local timer interrupts can be emulated by
841 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
843 * [ if a single-CPU system runs an SMP kernel then we call the local
844 * interrupt as well. Thus we cannot inline the local irq ... ]
846 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
848 struct pt_regs *old_regs = set_irq_regs(regs);
851 * NOTE! We'd better ACK the irq immediately,
852 * because timer handling can be slow.
856 * update_process_times() expects us to have done irq_enter().
857 * Besides, if we don't timer interrupts ignore the global
858 * interrupt lock, which is the WrongThing (tm) to do.
862 local_apic_timer_interrupt();
865 set_irq_regs(old_regs);
868 int setup_profiling_timer(unsigned int multiplier)
874 * Local APIC start and shutdown
878 * clear_local_APIC - shutdown the local APIC
880 * This is called, when a CPU is disabled and before rebooting, so the state of
881 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
882 * leftovers during boot.
884 void clear_local_APIC(void)
889 /* APIC hasn't been mapped yet */
890 if (!x2apic_mode && !apic_phys)
893 maxlvt = lapic_get_maxlvt();
895 * Masking an LVT entry can trigger a local APIC error
896 * if the vector is zero. Mask LVTERR first to prevent this.
899 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
900 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
903 * Careful: we have to set masks only first to deassert
904 * any level-triggered sources.
906 v = apic_read(APIC_LVTT);
907 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
908 v = apic_read(APIC_LVT0);
909 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
910 v = apic_read(APIC_LVT1);
911 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
913 v = apic_read(APIC_LVTPC);
914 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
917 /* lets not touch this if we didn't frob it */
918 #ifdef CONFIG_X86_THERMAL_VECTOR
920 v = apic_read(APIC_LVTTHMR);
921 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
924 #ifdef CONFIG_X86_MCE_INTEL
926 v = apic_read(APIC_LVTCMCI);
927 if (!(v & APIC_LVT_MASKED))
928 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
933 * Clean APIC state for other OSs:
935 apic_write(APIC_LVTT, APIC_LVT_MASKED);
936 apic_write(APIC_LVT0, APIC_LVT_MASKED);
937 apic_write(APIC_LVT1, APIC_LVT_MASKED);
939 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
941 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
943 /* Integrated APIC (!82489DX) ? */
944 if (lapic_is_integrated()) {
946 /* Clear ESR due to Pentium errata 3AP and 11AP */
947 apic_write(APIC_ESR, 0);
953 * disable_local_APIC - clear and disable the local APIC
955 void disable_local_APIC(void)
959 /* APIC hasn't been mapped yet */
960 if (!x2apic_mode && !apic_phys)
966 * Disable APIC (implies clearing of registers
969 value = apic_read(APIC_SPIV);
970 value &= ~APIC_SPIV_APIC_ENABLED;
971 apic_write(APIC_SPIV, value);
975 * When LAPIC was disabled by the BIOS and enabled by the kernel,
976 * restore the disabled state.
978 if (enabled_via_apicbase) {
981 rdmsr(MSR_IA32_APICBASE, l, h);
982 l &= ~MSR_IA32_APICBASE_ENABLE;
983 wrmsr(MSR_IA32_APICBASE, l, h);
989 * If Linux enabled the LAPIC against the BIOS default disable it down before
990 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
991 * not power-off. Additionally clear all LVT entries before disable_local_APIC
992 * for the case where Linux didn't enable the LAPIC.
994 void lapic_shutdown(void)
998 if (!cpu_has_apic && !apic_from_smp_config())
1001 local_irq_save(flags);
1003 #ifdef CONFIG_X86_32
1004 if (!enabled_via_apicbase)
1008 disable_local_APIC();
1011 local_irq_restore(flags);
1015 * This is to verify that we're looking at a real local APIC.
1016 * Check these against your board if the CPUs aren't getting
1017 * started for no apparent reason.
1019 int __init verify_local_APIC(void)
1021 unsigned int reg0, reg1;
1024 * The version register is read-only in a real APIC.
1026 reg0 = apic_read(APIC_LVR);
1027 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1028 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1029 reg1 = apic_read(APIC_LVR);
1030 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1033 * The two version reads above should print the same
1034 * numbers. If the second one is different, then we
1035 * poke at a non-APIC.
1041 * Check if the version looks reasonably.
1043 reg1 = GET_APIC_VERSION(reg0);
1044 if (reg1 == 0x00 || reg1 == 0xff)
1046 reg1 = lapic_get_maxlvt();
1047 if (reg1 < 0x02 || reg1 == 0xff)
1051 * The ID register is read/write in a real APIC.
1053 reg0 = apic_read(APIC_ID);
1054 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1055 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1056 reg1 = apic_read(APIC_ID);
1057 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1058 apic_write(APIC_ID, reg0);
1059 if (reg1 != (reg0 ^ apic->apic_id_mask))
1063 * The next two are just to see if we have sane values.
1064 * They're only really relevant if we're in Virtual Wire
1065 * compatibility mode, but most boxes are anymore.
1067 reg0 = apic_read(APIC_LVT0);
1068 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1069 reg1 = apic_read(APIC_LVT1);
1070 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1076 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1078 void __init sync_Arb_IDs(void)
1081 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1084 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1090 apic_wait_icr_idle();
1092 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1093 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1094 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1098 * An initial setup of the virtual wire mode.
1100 void __init init_bsp_APIC(void)
1105 * Don't do the setup now if we have a SMP BIOS as the
1106 * through-I/O-APIC virtual wire mode might be active.
1108 if (smp_found_config || !cpu_has_apic)
1112 * Do not trust the local APIC being empty at bootup.
1119 value = apic_read(APIC_SPIV);
1120 value &= ~APIC_VECTOR_MASK;
1121 value |= APIC_SPIV_APIC_ENABLED;
1123 #ifdef CONFIG_X86_32
1124 /* This bit is reserved on P4/Xeon and should be cleared */
1125 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1126 (boot_cpu_data.x86 == 15))
1127 value &= ~APIC_SPIV_FOCUS_DISABLED;
1130 value |= APIC_SPIV_FOCUS_DISABLED;
1131 value |= SPURIOUS_APIC_VECTOR;
1132 apic_write(APIC_SPIV, value);
1135 * Set up the virtual wire mode.
1137 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1138 value = APIC_DM_NMI;
1139 if (!lapic_is_integrated()) /* 82489DX */
1140 value |= APIC_LVT_LEVEL_TRIGGER;
1141 apic_write(APIC_LVT1, value);
1144 static void __cpuinit lapic_setup_esr(void)
1146 unsigned int oldvalue, value, maxlvt;
1148 if (!lapic_is_integrated()) {
1149 pr_info("No ESR for 82489DX.\n");
1153 if (apic->disable_esr) {
1155 * Something untraceable is creating bad interrupts on
1156 * secondary quads ... for the moment, just leave the
1157 * ESR disabled - we can't do anything useful with the
1158 * errors anyway - mbligh
1160 pr_info("Leaving ESR disabled.\n");
1164 maxlvt = lapic_get_maxlvt();
1165 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1166 apic_write(APIC_ESR, 0);
1167 oldvalue = apic_read(APIC_ESR);
1169 /* enables sending errors */
1170 value = ERROR_APIC_VECTOR;
1171 apic_write(APIC_LVTERR, value);
1174 * spec says clear errors after enabling vector.
1177 apic_write(APIC_ESR, 0);
1178 value = apic_read(APIC_ESR);
1179 if (value != oldvalue)
1180 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1181 "vector: 0x%08x after: 0x%08x\n",
1186 * setup_local_APIC - setup the local APIC
1188 * Used to setup local APIC while initializing BSP or bringin up APs.
1189 * Always called with preemption disabled.
1191 void __cpuinit setup_local_APIC(void)
1193 int cpu = smp_processor_id();
1194 unsigned int value, queued;
1195 int i, j, acked = 0;
1196 unsigned long long tsc = 0, ntsc;
1197 long long max_loops = cpu_khz;
1203 disable_ioapic_support();
1207 #ifdef CONFIG_X86_32
1208 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1209 if (lapic_is_integrated() && apic->disable_esr) {
1210 apic_write(APIC_ESR, 0);
1211 apic_write(APIC_ESR, 0);
1212 apic_write(APIC_ESR, 0);
1213 apic_write(APIC_ESR, 0);
1216 perf_events_lapic_init();
1219 * Double-check whether this APIC is really registered.
1220 * This is meaningless in clustered apic mode, so we skip it.
1222 BUG_ON(!apic->apic_id_registered());
1225 * Intel recommends to set DFR, LDR and TPR before enabling
1226 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1227 * document number 292116). So here it goes...
1229 apic->init_apic_ldr();
1231 #ifdef CONFIG_X86_32
1233 * APIC LDR is initialized. If logical_apicid mapping was
1234 * initialized during get_smp_config(), make sure it matches the
1237 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1238 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1239 /* always use the value from LDR */
1240 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1241 logical_smp_processor_id();
1244 * Some NUMA implementations (NUMAQ) don't initialize apicid to
1245 * node mapping during NUMA init. Now that logical apicid is
1246 * guaranteed to be known, give it another chance. This is already
1247 * a bit too late - percpu allocation has already happened without
1248 * proper NUMA affinity.
1250 if (apic->x86_32_numa_cpu_node)
1251 set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu),
1252 apic->x86_32_numa_cpu_node(cpu));
1256 * Set Task Priority to 'accept all'. We never change this
1259 value = apic_read(APIC_TASKPRI);
1260 value &= ~APIC_TPRI_MASK;
1261 apic_write(APIC_TASKPRI, value);
1264 * After a crash, we no longer service the interrupts and a pending
1265 * interrupt from previous kernel might still have ISR bit set.
1267 * Most probably by now CPU has serviced that pending interrupt and
1268 * it might not have done the ack_APIC_irq() because it thought,
1269 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1270 * does not clear the ISR bit and cpu thinks it has already serivced
1271 * the interrupt. Hence a vector might get locked. It was noticed
1272 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1276 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1277 queued |= apic_read(APIC_IRR + i*0x10);
1279 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1280 value = apic_read(APIC_ISR + i*0x10);
1281 for (j = 31; j >= 0; j--) {
1282 if (value & (1<<j)) {
1289 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1295 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1298 } while (queued && max_loops > 0);
1299 WARN_ON(max_loops <= 0);
1302 * Now that we are all set up, enable the APIC
1304 value = apic_read(APIC_SPIV);
1305 value &= ~APIC_VECTOR_MASK;
1309 value |= APIC_SPIV_APIC_ENABLED;
1311 #ifdef CONFIG_X86_32
1313 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1314 * certain networking cards. If high frequency interrupts are
1315 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1316 * entry is masked/unmasked at a high rate as well then sooner or
1317 * later IOAPIC line gets 'stuck', no more interrupts are received
1318 * from the device. If focus CPU is disabled then the hang goes
1321 * [ This bug can be reproduced easily with a level-triggered
1322 * PCI Ne2000 networking cards and PII/PIII processors, dual
1326 * Actually disabling the focus CPU check just makes the hang less
1327 * frequent as it makes the interrupt distributon model be more
1328 * like LRU than MRU (the short-term load is more even across CPUs).
1329 * See also the comment in end_level_ioapic_irq(). --macro
1333 * - enable focus processor (bit==0)
1334 * - 64bit mode always use processor focus
1335 * so no need to set it
1337 value &= ~APIC_SPIV_FOCUS_DISABLED;
1341 * Set spurious IRQ vector
1343 value |= SPURIOUS_APIC_VECTOR;
1344 apic_write(APIC_SPIV, value);
1347 * Set up LVT0, LVT1:
1349 * set up through-local-APIC on the BP's LINT0. This is not
1350 * strictly necessary in pure symmetric-IO mode, but sometimes
1351 * we delegate interrupts to the 8259A.
1354 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1356 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1357 if (!cpu && (pic_mode || !value)) {
1358 value = APIC_DM_EXTINT;
1359 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1361 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1362 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1364 apic_write(APIC_LVT0, value);
1367 * only the BP should see the LINT1 NMI signal, obviously.
1370 value = APIC_DM_NMI;
1372 value = APIC_DM_NMI | APIC_LVT_MASKED;
1373 if (!lapic_is_integrated()) /* 82489DX */
1374 value |= APIC_LVT_LEVEL_TRIGGER;
1375 apic_write(APIC_LVT1, value);
1377 #ifdef CONFIG_X86_MCE_INTEL
1378 /* Recheck CMCI information after local APIC is up on CPU #0 */
1384 void __cpuinit end_local_APIC_setup(void)
1388 #ifdef CONFIG_X86_32
1391 /* Disable the local apic timer */
1392 value = apic_read(APIC_LVTT);
1393 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1394 apic_write(APIC_LVTT, value);
1401 void __init bsp_end_local_APIC_setup(void)
1403 end_local_APIC_setup();
1406 * Now that local APIC setup is completed for BP, configure the fault
1407 * handling for interrupt remapping.
1409 if (intr_remapping_enabled)
1410 enable_drhd_fault_handling();
1414 #ifdef CONFIG_X86_X2APIC
1415 void check_x2apic(void)
1417 if (x2apic_enabled()) {
1418 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1419 x2apic_preenabled = x2apic_mode = 1;
1423 void enable_x2apic(void)
1430 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1431 if (!(msr & X2APIC_ENABLE)) {
1432 printk_once(KERN_INFO "Enabling x2apic\n");
1433 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
1436 #endif /* CONFIG_X86_X2APIC */
1438 int __init enable_IR(void)
1440 #ifdef CONFIG_IRQ_REMAP
1441 if (!intr_remapping_supported()) {
1442 pr_debug("intr-remapping not supported\n");
1446 if (!x2apic_preenabled && skip_ioapic_setup) {
1447 pr_info("Skipped enabling intr-remap because of skipping "
1452 return enable_intr_remapping();
1457 void __init enable_IR_x2apic(void)
1459 unsigned long flags;
1460 int ret, x2apic_enabled = 0;
1461 int dmar_table_init_ret;
1463 dmar_table_init_ret = dmar_table_init();
1464 if (dmar_table_init_ret && !x2apic_supported())
1467 ret = save_ioapic_entries();
1469 pr_info("Saving IO-APIC state failed: %d\n", ret);
1473 local_irq_save(flags);
1474 legacy_pic->mask_all();
1475 mask_ioapic_entries();
1477 if (dmar_table_init_ret)
1483 /* IR is required if there is APIC ID > 255 even when running
1486 if (max_physical_apicid > 255 ||
1487 !hypervisor_x2apic_available())
1490 * without IR all CPUs can be addressed by IOAPIC/MSI
1491 * only in physical mode
1493 x2apic_force_phys();
1496 if (ret == IRQ_REMAP_XAPIC_MODE)
1501 if (x2apic_supported() && !x2apic_mode) {
1504 pr_info("Enabled x2apic\n");
1508 if (ret < 0) /* IR enabling failed */
1509 restore_ioapic_entries();
1510 legacy_pic->restore_mask();
1511 local_irq_restore(flags);
1514 if (x2apic_enabled || !x2apic_supported())
1517 if (x2apic_preenabled)
1518 panic("x2apic: enabled by BIOS but kernel init failed.");
1519 else if (ret == IRQ_REMAP_XAPIC_MODE)
1520 pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n");
1522 pr_info("x2apic not enabled, IRQ remapping init failed\n");
1525 #ifdef CONFIG_X86_64
1527 * Detect and enable local APICs on non-SMP boards.
1528 * Original code written by Keir Fraser.
1529 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1530 * not correctly set up (usually the APIC timer won't work etc.)
1532 static int __init detect_init_APIC(void)
1534 if (!cpu_has_apic) {
1535 pr_info("No local APIC present\n");
1539 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1544 static int __init apic_verify(void)
1549 * The APIC feature bit should now be enabled
1552 features = cpuid_edx(1);
1553 if (!(features & (1 << X86_FEATURE_APIC))) {
1554 pr_warning("Could not enable APIC!\n");
1557 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1558 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1560 /* The BIOS may have set up the APIC at some other address */
1561 rdmsr(MSR_IA32_APICBASE, l, h);
1562 if (l & MSR_IA32_APICBASE_ENABLE)
1563 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1565 pr_info("Found and enabled local APIC!\n");
1569 int __init apic_force_enable(unsigned long addr)
1577 * Some BIOSes disable the local APIC in the APIC_BASE
1578 * MSR. This can only be done in software for Intel P6 or later
1579 * and AMD K7 (Model > 1) or later.
1581 rdmsr(MSR_IA32_APICBASE, l, h);
1582 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1583 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1584 l &= ~MSR_IA32_APICBASE_BASE;
1585 l |= MSR_IA32_APICBASE_ENABLE | addr;
1586 wrmsr(MSR_IA32_APICBASE, l, h);
1587 enabled_via_apicbase = 1;
1589 return apic_verify();
1593 * Detect and initialize APIC
1595 static int __init detect_init_APIC(void)
1597 /* Disabled by kernel option? */
1601 switch (boot_cpu_data.x86_vendor) {
1602 case X86_VENDOR_AMD:
1603 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1604 (boot_cpu_data.x86 >= 15))
1607 case X86_VENDOR_INTEL:
1608 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1609 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1616 if (!cpu_has_apic) {
1618 * Over-ride BIOS and try to enable the local APIC only if
1619 * "lapic" specified.
1621 if (!force_enable_local_apic) {
1622 pr_info("Local APIC disabled by BIOS -- "
1623 "you can enable it with \"lapic\"\n");
1626 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1638 pr_info("No local APIC present or hardware disabled\n");
1644 * init_apic_mappings - initialize APIC mappings
1646 void __init init_apic_mappings(void)
1648 unsigned int new_apicid;
1651 boot_cpu_physical_apicid = read_apic_id();
1655 /* If no local APIC can be found return early */
1656 if (!smp_found_config && detect_init_APIC()) {
1657 /* lets NOP'ify apic operations */
1658 pr_info("APIC: disable apic facility\n");
1661 apic_phys = mp_lapic_addr;
1664 * acpi lapic path already maps that address in
1665 * acpi_register_lapic_address()
1667 if (!acpi_lapic && !smp_found_config)
1668 register_lapic_address(apic_phys);
1672 * Fetch the APIC ID of the BSP in case we have a
1673 * default configuration (or the MP table is broken).
1675 new_apicid = read_apic_id();
1676 if (boot_cpu_physical_apicid != new_apicid) {
1677 boot_cpu_physical_apicid = new_apicid;
1679 * yeah -- we lie about apic_version
1680 * in case if apic was disabled via boot option
1681 * but it's not a problem for SMP compiled kernel
1682 * since smp_sanity_check is prepared for such a case
1683 * and disable smp mode
1685 apic_version[new_apicid] =
1686 GET_APIC_VERSION(apic_read(APIC_LVR));
1690 void __init register_lapic_address(unsigned long address)
1692 mp_lapic_addr = address;
1695 set_fixmap_nocache(FIX_APIC_BASE, address);
1696 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1697 APIC_BASE, mp_lapic_addr);
1699 if (boot_cpu_physical_apicid == -1U) {
1700 boot_cpu_physical_apicid = read_apic_id();
1701 apic_version[boot_cpu_physical_apicid] =
1702 GET_APIC_VERSION(apic_read(APIC_LVR));
1707 * This initializes the IO-APIC and APIC hardware if this is
1710 int apic_version[MAX_LOCAL_APIC];
1712 int __init APIC_init_uniprocessor(void)
1715 pr_info("Apic disabled\n");
1718 #ifdef CONFIG_X86_64
1719 if (!cpu_has_apic) {
1721 pr_info("Apic disabled by BIOS\n");
1725 if (!smp_found_config && !cpu_has_apic)
1729 * Complain if the BIOS pretends there is one.
1731 if (!cpu_has_apic &&
1732 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1733 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1734 boot_cpu_physical_apicid);
1739 default_setup_apic_routing();
1741 verify_local_APIC();
1744 #ifdef CONFIG_X86_64
1745 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1748 * Hack: In case of kdump, after a crash, kernel might be booting
1749 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1750 * might be zero if read from MP tables. Get it from LAPIC.
1752 # ifdef CONFIG_CRASH_DUMP
1753 boot_cpu_physical_apicid = read_apic_id();
1756 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1759 #ifdef CONFIG_X86_IO_APIC
1761 * Now enable IO-APICs, actually call clear_IO_APIC
1762 * We need clear_IO_APIC before enabling error vector
1764 if (!skip_ioapic_setup && nr_ioapics)
1768 bsp_end_local_APIC_setup();
1770 #ifdef CONFIG_X86_IO_APIC
1771 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1778 x86_init.timers.setup_percpu_clockev();
1783 * Local APIC interrupts
1787 * This interrupt should _never_ happen with our APIC/SMP architecture
1789 void smp_spurious_interrupt(struct pt_regs *regs)
1796 * Check if this really is a spurious interrupt and ACK it
1797 * if it is a vectored one. Just in case...
1798 * Spurious interrupts should not be ACKed.
1800 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1801 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1804 inc_irq_stat(irq_spurious_count);
1806 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1807 pr_info("spurious APIC interrupt on CPU#%d, "
1808 "should never happen.\n", smp_processor_id());
1813 * This interrupt should never happen with our APIC/SMP architecture
1815 void smp_error_interrupt(struct pt_regs *regs)
1819 static const char * const error_interrupt_reason[] = {
1820 "Send CS error", /* APIC Error Bit 0 */
1821 "Receive CS error", /* APIC Error Bit 1 */
1822 "Send accept error", /* APIC Error Bit 2 */
1823 "Receive accept error", /* APIC Error Bit 3 */
1824 "Redirectable IPI", /* APIC Error Bit 4 */
1825 "Send illegal vector", /* APIC Error Bit 5 */
1826 "Received illegal vector", /* APIC Error Bit 6 */
1827 "Illegal register address", /* APIC Error Bit 7 */
1832 /* First tickle the hardware, only then report what went on. -- REW */
1833 v0 = apic_read(APIC_ESR);
1834 apic_write(APIC_ESR, 0);
1835 v1 = apic_read(APIC_ESR);
1837 atomic_inc(&irq_err_count);
1839 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)",
1840 smp_processor_id(), v0 , v1);
1845 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1850 apic_printk(APIC_DEBUG, KERN_CONT "\n");
1856 * connect_bsp_APIC - attach the APIC to the interrupt system
1858 void __init connect_bsp_APIC(void)
1860 #ifdef CONFIG_X86_32
1863 * Do not trust the local APIC being empty at bootup.
1867 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1868 * local APIC to INT and NMI lines.
1870 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1871 "enabling APIC mode.\n");
1875 if (apic->enable_apic_mode)
1876 apic->enable_apic_mode();
1880 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1881 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1883 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1886 void disconnect_bsp_APIC(int virt_wire_setup)
1890 #ifdef CONFIG_X86_32
1893 * Put the board back into PIC mode (has an effect only on
1894 * certain older boards). Note that APIC interrupts, including
1895 * IPIs, won't work beyond this point! The only exception are
1898 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1899 "entering PIC mode.\n");
1905 /* Go back to Virtual Wire compatibility mode */
1907 /* For the spurious interrupt use vector F, and enable it */
1908 value = apic_read(APIC_SPIV);
1909 value &= ~APIC_VECTOR_MASK;
1910 value |= APIC_SPIV_APIC_ENABLED;
1912 apic_write(APIC_SPIV, value);
1914 if (!virt_wire_setup) {
1916 * For LVT0 make it edge triggered, active high,
1917 * external and enabled
1919 value = apic_read(APIC_LVT0);
1920 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1921 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1922 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1923 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1924 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1925 apic_write(APIC_LVT0, value);
1928 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1932 * For LVT1 make it edge triggered, active high,
1935 value = apic_read(APIC_LVT1);
1936 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1937 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1938 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1939 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1940 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1941 apic_write(APIC_LVT1, value);
1944 void __cpuinit generic_processor_info(int apicid, int version)
1946 int cpu, max = nr_cpu_ids;
1947 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
1948 phys_cpu_present_map);
1951 * If boot cpu has not been detected yet, then only allow upto
1952 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
1954 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
1955 apicid != boot_cpu_physical_apicid) {
1956 int thiscpu = max + disabled_cpus - 1;
1959 "ACPI: NR_CPUS/possible_cpus limit of %i almost"
1960 " reached. Keeping one slot for boot cpu."
1961 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1967 if (num_processors >= nr_cpu_ids) {
1968 int thiscpu = max + disabled_cpus;
1971 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1972 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1979 if (apicid == boot_cpu_physical_apicid) {
1981 * x86_bios_cpu_apicid is required to have processors listed
1982 * in same order as logical cpu numbers. Hence the first
1983 * entry is BSP, and so on.
1984 * boot_cpu_init() already hold bit 0 in cpu_present_mask
1989 cpu = cpumask_next_zero(-1, cpu_present_mask);
1994 if (version == 0x0) {
1995 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
1999 apic_version[apicid] = version;
2001 if (version != apic_version[boot_cpu_physical_apicid]) {
2002 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2003 apic_version[boot_cpu_physical_apicid], cpu, version);
2006 physid_set(apicid, phys_cpu_present_map);
2007 if (apicid > max_physical_apicid)
2008 max_physical_apicid = apicid;
2010 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2011 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2012 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2014 #ifdef CONFIG_X86_32
2015 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2016 apic->x86_32_early_logical_apicid(cpu);
2018 set_cpu_possible(cpu, true);
2019 set_cpu_present(cpu, true);
2022 int hard_smp_processor_id(void)
2024 return read_apic_id();
2027 void default_init_apic_ldr(void)
2031 apic_write(APIC_DFR, APIC_DFR_VALUE);
2032 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2033 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2034 apic_write(APIC_LDR, val);
2044 * 'active' is true if the local APIC was enabled by us and
2045 * not the BIOS; this signifies that we are also responsible
2046 * for disabling it before entering apm/acpi suspend
2049 /* r/w apic fields */
2050 unsigned int apic_id;
2051 unsigned int apic_taskpri;
2052 unsigned int apic_ldr;
2053 unsigned int apic_dfr;
2054 unsigned int apic_spiv;
2055 unsigned int apic_lvtt;
2056 unsigned int apic_lvtpc;
2057 unsigned int apic_lvt0;
2058 unsigned int apic_lvt1;
2059 unsigned int apic_lvterr;
2060 unsigned int apic_tmict;
2061 unsigned int apic_tdcr;
2062 unsigned int apic_thmr;
2065 static int lapic_suspend(void)
2067 unsigned long flags;
2070 if (!apic_pm_state.active)
2073 maxlvt = lapic_get_maxlvt();
2075 apic_pm_state.apic_id = apic_read(APIC_ID);
2076 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2077 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2078 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2079 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2080 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2082 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2083 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2084 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2085 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2086 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2087 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2088 #ifdef CONFIG_X86_THERMAL_VECTOR
2090 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2093 local_irq_save(flags);
2094 disable_local_APIC();
2096 if (intr_remapping_enabled)
2097 disable_intr_remapping();
2099 local_irq_restore(flags);
2103 static void lapic_resume(void)
2106 unsigned long flags;
2109 if (!apic_pm_state.active)
2112 local_irq_save(flags);
2113 if (intr_remapping_enabled) {
2115 * IO-APIC and PIC have their own resume routines.
2116 * We just mask them here to make sure the interrupt
2117 * subsystem is completely quiet while we enable x2apic
2118 * and interrupt-remapping.
2120 mask_ioapic_entries();
2121 legacy_pic->mask_all();
2128 * Make sure the APICBASE points to the right address
2130 * FIXME! This will be wrong if we ever support suspend on
2131 * SMP! We'll need to do this as part of the CPU restore!
2133 rdmsr(MSR_IA32_APICBASE, l, h);
2134 l &= ~MSR_IA32_APICBASE_BASE;
2135 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2136 wrmsr(MSR_IA32_APICBASE, l, h);
2139 maxlvt = lapic_get_maxlvt();
2140 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2141 apic_write(APIC_ID, apic_pm_state.apic_id);
2142 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2143 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2144 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2145 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2146 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2147 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2148 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2150 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2153 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2154 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2155 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2156 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2157 apic_write(APIC_ESR, 0);
2158 apic_read(APIC_ESR);
2159 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2160 apic_write(APIC_ESR, 0);
2161 apic_read(APIC_ESR);
2163 if (intr_remapping_enabled)
2164 reenable_intr_remapping(x2apic_mode);
2166 local_irq_restore(flags);
2170 * This device has no shutdown method - fully functioning local APICs
2171 * are needed on every CPU up until machine_halt/restart/poweroff.
2174 static struct syscore_ops lapic_syscore_ops = {
2175 .resume = lapic_resume,
2176 .suspend = lapic_suspend,
2179 static void __cpuinit apic_pm_activate(void)
2181 apic_pm_state.active = 1;
2184 static int __init init_lapic_sysfs(void)
2186 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2188 register_syscore_ops(&lapic_syscore_ops);
2193 /* local apic needs to resume before other devices access its registers. */
2194 core_initcall(init_lapic_sysfs);
2196 #else /* CONFIG_PM */
2198 static void apic_pm_activate(void) { }
2200 #endif /* CONFIG_PM */
2202 #ifdef CONFIG_X86_64
2204 static int __cpuinit apic_cluster_num(void)
2206 int i, clusters, zeros;
2208 u16 *bios_cpu_apicid;
2209 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2211 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2212 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2214 for (i = 0; i < nr_cpu_ids; i++) {
2215 /* are we being called early in kernel startup? */
2216 if (bios_cpu_apicid) {
2217 id = bios_cpu_apicid[i];
2218 } else if (i < nr_cpu_ids) {
2220 id = per_cpu(x86_bios_cpu_apicid, i);
2226 if (id != BAD_APICID)
2227 __set_bit(APIC_CLUSTERID(id), clustermap);
2230 /* Problem: Partially populated chassis may not have CPUs in some of
2231 * the APIC clusters they have been allocated. Only present CPUs have
2232 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2233 * Since clusters are allocated sequentially, count zeros only if
2234 * they are bounded by ones.
2238 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2239 if (test_bit(i, clustermap)) {
2240 clusters += 1 + zeros;
2249 static int __cpuinitdata multi_checked;
2250 static int __cpuinitdata multi;
2252 static int __cpuinit set_multi(const struct dmi_system_id *d)
2256 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2261 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
2263 .callback = set_multi,
2264 .ident = "IBM System Summit2",
2266 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2267 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2273 static void __cpuinit dmi_check_multi(void)
2278 dmi_check_system(multi_dmi_table);
2283 * apic_is_clustered_box() -- Check if we can expect good TSC
2285 * Thus far, the major user of this is IBM's Summit2 series:
2286 * Clustered boxes may have unsynced TSC problems if they are
2288 * Use DMI to check them
2290 __cpuinit int apic_is_clustered_box(void)
2300 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2301 * not guaranteed to be synced between boards
2303 if (apic_cluster_num() > 1)
2311 * APIC command line parameters
2313 static int __init setup_disableapic(char *arg)
2316 setup_clear_cpu_cap(X86_FEATURE_APIC);
2319 early_param("disableapic", setup_disableapic);
2321 /* same as disableapic, for compatibility */
2322 static int __init setup_nolapic(char *arg)
2324 return setup_disableapic(arg);
2326 early_param("nolapic", setup_nolapic);
2328 static int __init parse_lapic_timer_c2_ok(char *arg)
2330 local_apic_timer_c2_ok = 1;
2333 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2335 static int __init parse_disable_apic_timer(char *arg)
2337 disable_apic_timer = 1;
2340 early_param("noapictimer", parse_disable_apic_timer);
2342 static int __init parse_nolapic_timer(char *arg)
2344 disable_apic_timer = 1;
2347 early_param("nolapic_timer", parse_nolapic_timer);
2349 static int __init apic_set_verbosity(char *arg)
2352 #ifdef CONFIG_X86_64
2353 skip_ioapic_setup = 0;
2359 if (strcmp("debug", arg) == 0)
2360 apic_verbosity = APIC_DEBUG;
2361 else if (strcmp("verbose", arg) == 0)
2362 apic_verbosity = APIC_VERBOSE;
2364 pr_warning("APIC Verbosity level %s not recognised"
2365 " use apic=verbose or apic=debug\n", arg);
2371 early_param("apic", apic_set_verbosity);
2373 static int __init lapic_insert_resource(void)
2378 /* Put local APIC into the resource map. */
2379 lapic_resource.start = apic_phys;
2380 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2381 insert_resource(&iomem_resource, &lapic_resource);
2387 * need call insert after e820_reserve_resources()
2388 * that is using request_resource
2390 late_initcall(lapic_insert_resource);