1 // SPDX-License-Identifier: GPL-2.0-only
3 * Local APIC handling, local APIC timers
5 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
8 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
9 * thanks to Eric Gilmore
11 * for testing these extensively.
12 * Maciej W. Rozycki : Various updates and fixes.
13 * Mikael Pettersson : Power Management for UP-APIC.
15 * Mikael Pettersson : PM converted to driver model.
18 #include <linux/perf_event.h>
19 #include <linux/kernel_stat.h>
20 #include <linux/mc146818rtc.h>
21 #include <linux/acpi_pmtmr.h>
22 #include <linux/clockchips.h>
23 #include <linux/interrupt.h>
24 #include <linux/memblock.h>
25 #include <linux/ftrace.h>
26 #include <linux/ioport.h>
27 #include <linux/export.h>
28 #include <linux/syscore_ops.h>
29 #include <linux/delay.h>
30 #include <linux/timex.h>
31 #include <linux/i8253.h>
32 #include <linux/dmar.h>
33 #include <linux/init.h>
34 #include <linux/cpu.h>
35 #include <linux/dmi.h>
36 #include <linux/smp.h>
39 #include <asm/trace/irq_vectors.h>
40 #include <asm/irq_remapping.h>
41 #include <asm/perf_event.h>
42 #include <asm/x86_init.h>
43 #include <asm/pgalloc.h>
44 #include <linux/atomic.h>
45 #include <asm/mpspec.h>
46 #include <asm/i8259.h>
47 #include <asm/proto.h>
48 #include <asm/traps.h>
50 #include <asm/io_apic.h>
58 #include <asm/hypervisor.h>
59 #include <asm/cpu_device_id.h>
60 #include <asm/intel-family.h>
61 #include <asm/irq_regs.h>
63 unsigned int num_processors;
65 unsigned disabled_cpus;
67 /* Processor that is doing the boot up */
68 unsigned int boot_cpu_physical_apicid __ro_after_init = -1U;
69 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
71 u8 boot_cpu_apic_version __ro_after_init;
74 * The highest APIC ID seen during enumeration.
76 static unsigned int max_physical_apicid;
79 * Bitmask of physically existing CPUs:
81 physid_mask_t phys_cpu_present_map;
84 * Processor to be disabled specified by kernel parameter
85 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
86 * avoid undefined behaviour caused by sending INIT from AP to BSP.
88 static unsigned int disabled_cpu_apicid __ro_after_init = BAD_APICID;
91 * This variable controls which CPUs receive external NMIs. By default,
92 * external NMIs are delivered only to the BSP.
94 static int apic_extnmi __ro_after_init = APIC_EXTNMI_BSP;
97 * Map cpu index to physical APIC ID
99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
101 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
104 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
109 * On x86_32, the mapping between cpu and logical apicid may vary
110 * depending on apic in use. The following early percpu variable is
111 * used for the mapping. This is where the behaviors of x86_64 and 32
112 * actually diverge. Let's keep it ugly for now.
114 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
116 /* Local APIC was disabled by the BIOS and enabled by the kernel */
117 static int enabled_via_apicbase __ro_after_init;
120 * Handle interrupt mode configuration register (IMCR).
121 * This register controls whether the interrupt signals
122 * that reach the BSP come from the master PIC or from the
123 * local APIC. Before entering Symmetric I/O Mode, either
124 * the BIOS or the operating system must switch out of
125 * PIC Mode by changing the IMCR.
127 static inline void imcr_pic_to_apic(void)
129 /* select IMCR register */
131 /* NMI and 8259 INTR go through APIC */
135 static inline void imcr_apic_to_pic(void)
137 /* select IMCR register */
139 /* NMI and 8259 INTR go directly to BSP */
145 * Knob to control our willingness to enable the local APIC.
149 static int force_enable_local_apic __initdata;
152 * APIC command line parameters
154 static int __init parse_lapic(char *arg)
156 if (IS_ENABLED(CONFIG_X86_32) && !arg)
157 force_enable_local_apic = 1;
158 else if (arg && !strncmp(arg, "notscdeadline", 13))
159 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
162 early_param("lapic", parse_lapic);
165 static int apic_calibrate_pmtmr __initdata;
166 static __init int setup_apicpmtimer(char *s)
168 apic_calibrate_pmtmr = 1;
172 __setup("apicpmtimer", setup_apicpmtimer);
175 unsigned long mp_lapic_addr __ro_after_init;
176 int disable_apic __ro_after_init;
177 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
178 static int disable_apic_timer __initdata;
179 /* Local APIC timer works in C2 */
180 int local_apic_timer_c2_ok __ro_after_init;
181 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
184 * Debug level, exported for io_apic.c
186 int apic_verbosity __ro_after_init;
188 int pic_mode __ro_after_init;
190 /* Have we found an MP table */
191 int smp_found_config __ro_after_init;
193 static struct resource lapic_resource = {
194 .name = "Local APIC",
195 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
198 unsigned int lapic_timer_period = 0;
200 static void apic_pm_activate(void);
202 static unsigned long apic_phys __ro_after_init;
205 * Get the LAPIC version
207 static inline int lapic_get_version(void)
209 return GET_APIC_VERSION(apic_read(APIC_LVR));
213 * Check, if the APIC is integrated or a separate chip
215 static inline int lapic_is_integrated(void)
217 return APIC_INTEGRATED(lapic_get_version());
221 * Check, whether this is a modern or a first generation APIC
223 static int modern_apic(void)
225 /* AMD systems use old APIC versions, so check the CPU */
226 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
227 boot_cpu_data.x86 >= 0xf)
230 /* Hygon systems use modern APIC */
231 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
234 return lapic_get_version() >= 0x14;
238 * right after this call apic become NOOP driven
239 * so apic->write/read doesn't do anything
241 static void __init apic_disable(void)
243 pr_info("APIC: switched to apic NOOP\n");
247 void native_apic_wait_icr_idle(void)
249 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
253 u32 native_safe_apic_wait_icr_idle(void)
260 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
263 inc_irq_stat(icr_read_retry_count);
265 } while (timeout++ < 1000);
270 void native_apic_icr_write(u32 low, u32 id)
274 local_irq_save(flags);
275 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
276 apic_write(APIC_ICR, low);
277 local_irq_restore(flags);
280 u64 native_apic_icr_read(void)
284 icr2 = apic_read(APIC_ICR2);
285 icr1 = apic_read(APIC_ICR);
287 return icr1 | ((u64)icr2 << 32);
292 * get_physical_broadcast - Get number of physical broadcast IDs
294 int get_physical_broadcast(void)
296 return modern_apic() ? 0xff : 0xf;
301 * lapic_get_maxlvt - get the maximum number of local vector table entries
303 int lapic_get_maxlvt(void)
306 * - we always have APIC integrated on 64bit mode
307 * - 82489DXs do not report # of LVT entries
309 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2;
317 #define APIC_DIVISOR 16
318 #define TSC_DIVISOR 8
321 * This function sets up the local APIC timer, with a timeout of
322 * 'clocks' APIC bus clock. During calibration we actually call
323 * this function twice on the boot CPU, once with a bogus timeout
324 * value, second time for real. The other (noncalibrating) CPUs
325 * call this function only once, with the real, calibrated value.
327 * We do reads before writes even if unnecessary, to get around the
328 * P5 APIC double write bug.
330 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
332 unsigned int lvtt_value, tmp_value;
334 lvtt_value = LOCAL_TIMER_VECTOR;
336 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
337 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
338 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
340 if (!lapic_is_integrated())
341 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
344 lvtt_value |= APIC_LVT_MASKED;
346 apic_write(APIC_LVTT, lvtt_value);
348 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
350 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
351 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
352 * According to Intel, MFENCE can do the serialization here.
354 asm volatile("mfence" : : : "memory");
356 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
363 tmp_value = apic_read(APIC_TDCR);
364 apic_write(APIC_TDCR,
365 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
369 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
373 * Setup extended LVT, AMD specific
375 * Software should use the LVT offsets the BIOS provides. The offsets
376 * are determined by the subsystems using it like those for MCE
377 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
378 * are supported. Beginning with family 10h at least 4 offsets are
381 * Since the offsets must be consistent for all cores, we keep track
382 * of the LVT offsets in software and reserve the offset for the same
383 * vector also to be used on other cores. An offset is freed by
384 * setting the entry to APIC_EILVT_MASKED.
386 * If the BIOS is right, there should be no conflicts. Otherwise a
387 * "[Firmware Bug]: ..." error message is generated. However, if
388 * software does not properly determines the offsets, it is not
389 * necessarily a BIOS bug.
392 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
394 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
396 return (old & APIC_EILVT_MASKED)
397 || (new == APIC_EILVT_MASKED)
398 || ((new & ~APIC_EILVT_MASKED) == old);
401 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
403 unsigned int rsvd, vector;
405 if (offset >= APIC_EILVT_NR_MAX)
408 rsvd = atomic_read(&eilvt_offsets[offset]);
410 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
411 if (vector && !eilvt_entry_is_changeable(vector, new))
412 /* may not change if vectors are different */
414 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
415 } while (rsvd != new);
417 rsvd &= ~APIC_EILVT_MASKED;
418 if (rsvd && rsvd != vector)
419 pr_info("LVT offset %d assigned for vector 0x%02x\n",
426 * If mask=1, the LVT entry does not generate interrupts while mask=0
427 * enables the vector. See also the BKDGs. Must be called with
428 * preemption disabled.
431 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
433 unsigned long reg = APIC_EILVTn(offset);
434 unsigned int new, old, reserved;
436 new = (mask << 16) | (msg_type << 8) | vector;
437 old = apic_read(reg);
438 reserved = reserve_eilvt_offset(offset, new);
440 if (reserved != new) {
441 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
442 "vector 0x%x, but the register is already in use for "
443 "vector 0x%x on another cpu\n",
444 smp_processor_id(), reg, offset, new, reserved);
448 if (!eilvt_entry_is_changeable(old, new)) {
449 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
450 "vector 0x%x, but the register is already in use for "
451 "vector 0x%x on this cpu\n",
452 smp_processor_id(), reg, offset, new, old);
456 apic_write(reg, new);
460 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
463 * Program the next event, relative to now
465 static int lapic_next_event(unsigned long delta,
466 struct clock_event_device *evt)
468 apic_write(APIC_TMICT, delta);
472 static int lapic_next_deadline(unsigned long delta,
473 struct clock_event_device *evt)
478 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
482 static int lapic_timer_shutdown(struct clock_event_device *evt)
486 /* Lapic used as dummy for broadcast ? */
487 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
490 v = apic_read(APIC_LVTT);
491 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
492 apic_write(APIC_LVTT, v);
493 apic_write(APIC_TMICT, 0);
498 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
500 /* Lapic used as dummy for broadcast ? */
501 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
504 __setup_APIC_LVTT(lapic_timer_period, oneshot, 1);
508 static int lapic_timer_set_periodic(struct clock_event_device *evt)
510 return lapic_timer_set_periodic_oneshot(evt, false);
513 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
515 return lapic_timer_set_periodic_oneshot(evt, true);
519 * Local APIC timer broadcast function
521 static void lapic_timer_broadcast(const struct cpumask *mask)
524 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
530 * The local apic timer can be used for any function which is CPU local.
532 static struct clock_event_device lapic_clockevent = {
534 .features = CLOCK_EVT_FEAT_PERIODIC |
535 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
536 | CLOCK_EVT_FEAT_DUMMY,
538 .set_state_shutdown = lapic_timer_shutdown,
539 .set_state_periodic = lapic_timer_set_periodic,
540 .set_state_oneshot = lapic_timer_set_oneshot,
541 .set_state_oneshot_stopped = lapic_timer_shutdown,
542 .set_next_event = lapic_next_event,
543 .broadcast = lapic_timer_broadcast,
547 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
549 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \
550 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
552 #define DEADLINE_MODEL_MATCH_REV(model, rev) \
553 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
555 static u32 hsx_deadline_rev(void)
557 switch (boot_cpu_data.x86_stepping) {
558 case 0x02: return 0x3a; /* EP */
559 case 0x04: return 0x0f; /* EX */
565 static u32 bdx_deadline_rev(void)
567 switch (boot_cpu_data.x86_stepping) {
568 case 0x02: return 0x00000011;
569 case 0x03: return 0x0700000e;
570 case 0x04: return 0x0f00000c;
571 case 0x05: return 0x0e000003;
577 static u32 skx_deadline_rev(void)
579 switch (boot_cpu_data.x86_stepping) {
580 case 0x03: return 0x01000136;
581 case 0x04: return 0x02000014;
584 if (boot_cpu_data.x86_stepping > 4)
590 static const struct x86_cpu_id deadline_match[] = {
591 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev),
592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020),
593 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_D, bdx_deadline_rev),
594 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev),
596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL, 0x22),
597 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_L, 0x20),
598 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_G, 0x17),
600 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL, 0x25),
601 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_G, 0x17),
603 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_L, 0xb2),
604 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE, 0xb2),
606 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_L, 0x52),
607 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE, 0x52),
612 static void apic_check_deadline_errata(void)
614 const struct x86_cpu_id *m;
617 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) ||
618 boot_cpu_has(X86_FEATURE_HYPERVISOR))
621 m = x86_match_cpu(deadline_match);
626 * Function pointers will have the MSB set due to address layout,
627 * immediate revisions will not.
629 if ((long)m->driver_data < 0)
630 rev = ((u32 (*)(void))(m->driver_data))();
632 rev = (u32)m->driver_data;
634 if (boot_cpu_data.microcode >= rev)
637 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
638 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
639 "please update microcode to version: 0x%x (or later)\n", rev);
643 * Setup the local APIC timer for this CPU. Copy the initialized values
644 * of the boot CPU and register the clock event in the framework.
646 static void setup_APIC_timer(void)
648 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
650 if (this_cpu_has(X86_FEATURE_ARAT)) {
651 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
652 /* Make LAPIC timer preferrable over percpu HPET */
653 lapic_clockevent.rating = 150;
656 memcpy(levt, &lapic_clockevent, sizeof(*levt));
657 levt->cpumask = cpumask_of(smp_processor_id());
659 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
660 levt->name = "lapic-deadline";
661 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
662 CLOCK_EVT_FEAT_DUMMY);
663 levt->set_next_event = lapic_next_deadline;
664 clockevents_config_and_register(levt,
665 tsc_khz * (1000 / TSC_DIVISOR),
668 clockevents_register_device(levt);
672 * Install the updated TSC frequency from recalibration at the TSC
673 * deadline clockevent devices.
675 static void __lapic_update_tsc_freq(void *info)
677 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
679 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
682 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
685 void lapic_update_tsc_freq(void)
688 * The clockevent device's ->mult and ->shift can both be
689 * changed. In order to avoid races, schedule the frequency
690 * update code on each CPU.
692 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
696 * In this functions we calibrate APIC bus clocks to the external timer.
698 * We want to do the calibration only once since we want to have local timer
699 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
702 * This was previously done by reading the PIT/HPET and waiting for a wrap
703 * around to find out, that a tick has elapsed. I have a box, where the PIT
704 * readout is broken, so it never gets out of the wait loop again. This was
705 * also reported by others.
707 * Monitoring the jiffies value is inaccurate and the clockevents
708 * infrastructure allows us to do a simple substitution of the interrupt
711 * The calibration routine also uses the pm_timer when possible, as the PIT
712 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
713 * back to normal later in the boot process).
716 #define LAPIC_CAL_LOOPS (HZ/10)
718 static __initdata int lapic_cal_loops = -1;
719 static __initdata long lapic_cal_t1, lapic_cal_t2;
720 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
721 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
722 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
725 * Temporary interrupt handler and polled calibration function.
727 static void __init lapic_cal_handler(struct clock_event_device *dev)
729 unsigned long long tsc = 0;
730 long tapic = apic_read(APIC_TMCCT);
731 unsigned long pm = acpi_pm_read_early();
733 if (boot_cpu_has(X86_FEATURE_TSC))
736 switch (lapic_cal_loops++) {
738 lapic_cal_t1 = tapic;
739 lapic_cal_tsc1 = tsc;
741 lapic_cal_j1 = jiffies;
744 case LAPIC_CAL_LOOPS:
745 lapic_cal_t2 = tapic;
746 lapic_cal_tsc2 = tsc;
747 if (pm < lapic_cal_pm1)
748 pm += ACPI_PM_OVRRUN;
750 lapic_cal_j2 = jiffies;
756 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
758 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
759 const long pm_thresh = pm_100ms / 100;
763 #ifndef CONFIG_X86_PM_TIMER
767 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
769 /* Check, if the PM timer is available */
773 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
775 if (deltapm > (pm_100ms - pm_thresh) &&
776 deltapm < (pm_100ms + pm_thresh)) {
777 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
781 res = (((u64)deltapm) * mult) >> 22;
782 do_div(res, 1000000);
783 pr_warning("APIC calibration not consistent "
784 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
786 /* Correct the lapic counter value */
787 res = (((u64)(*delta)) * pm_100ms);
788 do_div(res, deltapm);
789 pr_info("APIC delta adjusted to PM-Timer: "
790 "%lu (%ld)\n", (unsigned long)res, *delta);
793 /* Correct the tsc counter value */
794 if (boot_cpu_has(X86_FEATURE_TSC)) {
795 res = (((u64)(*deltatsc)) * pm_100ms);
796 do_div(res, deltapm);
797 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
798 "PM-Timer: %lu (%ld)\n",
799 (unsigned long)res, *deltatsc);
800 *deltatsc = (long)res;
806 static int __init lapic_init_clockevent(void)
808 if (!lapic_timer_period)
811 /* Calculate the scaled math multiplication factor */
812 lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR,
813 TICK_NSEC, lapic_clockevent.shift);
814 lapic_clockevent.max_delta_ns =
815 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
816 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
817 lapic_clockevent.min_delta_ns =
818 clockevent_delta2ns(0xF, &lapic_clockevent);
819 lapic_clockevent.min_delta_ticks = 0xF;
824 bool __init apic_needs_pit(void)
827 * If the frequencies are not known, PIT is required for both TSC
828 * and apic timer calibration.
830 if (!tsc_khz || !cpu_khz)
833 /* Is there an APIC at all? */
834 if (!boot_cpu_has(X86_FEATURE_APIC))
837 /* Virt guests may lack ARAT, but still have DEADLINE */
838 if (!boot_cpu_has(X86_FEATURE_ARAT))
841 /* Deadline timer is based on TSC so no further PIT action required */
842 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
845 /* APIC timer disabled? */
846 if (disable_apic_timer)
849 * The APIC timer frequency is known already, no PIT calibration
850 * required. If unknown, let the PIT be initialized.
852 return lapic_timer_period == 0;
855 static int __init calibrate_APIC_clock(void)
857 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
858 u64 tsc_perj = 0, tsc_start = 0;
859 unsigned long jif_start;
860 unsigned long deltaj;
861 long delta, deltatsc;
862 int pm_referenced = 0;
864 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
868 * Check if lapic timer has already been calibrated by platform
869 * specific routine, such as tsc calibration code. If so just fill
870 * in the clockevent structure and return.
872 if (!lapic_init_clockevent()) {
873 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
876 * Direct calibration methods must have an always running
877 * local APIC timer, no need for broadcast timer.
879 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
883 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
884 "calibrating APIC timer ...\n");
887 * There are platforms w/o global clockevent devices. Instead of
888 * making the calibration conditional on that, use a polling based
889 * approach everywhere.
894 * Setup the APIC counter to maximum. There is no way the lapic
895 * can underflow in the 100ms detection time frame
897 __setup_APIC_LVTT(0xffffffff, 0, 0);
900 * Methods to terminate the calibration loop:
901 * 1) Global clockevent if available (jiffies)
902 * 2) TSC if available and frequency is known
904 jif_start = READ_ONCE(jiffies);
908 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ);
912 * Enable interrupts so the tick can fire, if a global
913 * clockevent device is available
917 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) {
918 /* Wait for a tick to elapse */
921 u64 tsc_now = rdtsc();
922 if ((tsc_now - tsc_start) >= tsc_perj) {
923 tsc_start += tsc_perj;
927 unsigned long jif_now = READ_ONCE(jiffies);
929 if (time_after(jif_now, jif_start)) {
937 /* Invoke the calibration routine */
939 lapic_cal_handler(NULL);
945 /* Build delta t1-t2 as apic timer counts down */
946 delta = lapic_cal_t1 - lapic_cal_t2;
947 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
949 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
951 /* we trust the PM based calibration if possible */
952 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
955 lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
956 lapic_init_clockevent();
958 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
959 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
960 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
963 if (boot_cpu_has(X86_FEATURE_TSC)) {
964 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
966 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
967 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
970 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
972 lapic_timer_period / (1000000 / HZ),
973 lapic_timer_period % (1000000 / HZ));
976 * Do a sanity check on the APIC calibration result
978 if (lapic_timer_period < (1000000 / HZ)) {
980 pr_warning("APIC frequency too slow, disabling apic timer\n");
984 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
987 * PM timer calibration failed or not turned on so lets try APIC
988 * timer based calibration, if a global clockevent device is
991 if (!pm_referenced && global_clock_event) {
992 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
995 * Setup the apic timer manually
997 levt->event_handler = lapic_cal_handler;
998 lapic_timer_set_periodic(levt);
999 lapic_cal_loops = -1;
1001 /* Let the interrupts run */
1004 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
1007 /* Stop the lapic timer */
1008 local_irq_disable();
1009 lapic_timer_shutdown(levt);
1012 deltaj = lapic_cal_j2 - lapic_cal_j1;
1013 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
1015 /* Check, if the jiffies result is consistent */
1016 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
1017 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
1019 levt->features |= CLOCK_EVT_FEAT_DUMMY;
1023 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
1024 pr_warning("APIC timer disabled due to verification failure\n");
1032 * Setup the boot APIC
1034 * Calibrate and verify the result.
1036 void __init setup_boot_APIC_clock(void)
1039 * The local apic timer can be disabled via the kernel
1040 * commandline or from the CPU detection code. Register the lapic
1041 * timer as a dummy clock event source on SMP systems, so the
1042 * broadcast mechanism is used. On UP systems simply ignore it.
1044 if (disable_apic_timer) {
1045 pr_info("Disabling APIC timer\n");
1046 /* No broadcast on UP ! */
1047 if (num_possible_cpus() > 1) {
1048 lapic_clockevent.mult = 1;
1054 if (calibrate_APIC_clock()) {
1055 /* No broadcast on UP ! */
1056 if (num_possible_cpus() > 1)
1062 * If nmi_watchdog is set to IO_APIC, we need the
1063 * PIT/HPET going. Otherwise register lapic as a dummy
1066 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
1068 /* Setup the lapic or request the broadcast */
1070 amd_e400_c1e_apic_setup();
1073 void setup_secondary_APIC_clock(void)
1076 amd_e400_c1e_apic_setup();
1080 * The guts of the apic timer interrupt
1082 static void local_apic_timer_interrupt(void)
1084 struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1087 * Normally we should not be here till LAPIC has been initialized but
1088 * in some cases like kdump, its possible that there is a pending LAPIC
1089 * timer interrupt from previous kernel's context and is delivered in
1090 * new kernel the moment interrupts are enabled.
1092 * Interrupts are enabled early and LAPIC is setup much later, hence
1093 * its possible that when we get here evt->event_handler is NULL.
1094 * Check for event_handler being NULL and discard the interrupt as
1097 if (!evt->event_handler) {
1098 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n",
1099 smp_processor_id());
1101 lapic_timer_shutdown(evt);
1106 * the NMI deadlock-detector uses this.
1108 inc_irq_stat(apic_timer_irqs);
1110 evt->event_handler(evt);
1114 * Local APIC timer interrupt. This is the most natural way for doing
1115 * local interrupts, but local timer interrupts can be emulated by
1116 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1118 * [ if a single-CPU system runs an SMP kernel then we call the local
1119 * interrupt as well. Thus we cannot inline the local irq ... ]
1121 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
1123 struct pt_regs *old_regs = set_irq_regs(regs);
1126 * NOTE! We'd better ACK the irq immediately,
1127 * because timer handling can be slow.
1129 * update_process_times() expects us to have done irq_enter().
1130 * Besides, if we don't timer interrupts ignore the global
1131 * interrupt lock, which is the WrongThing (tm) to do.
1134 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1135 local_apic_timer_interrupt();
1136 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1139 set_irq_regs(old_regs);
1142 int setup_profiling_timer(unsigned int multiplier)
1148 * Local APIC start and shutdown
1152 * clear_local_APIC - shutdown the local APIC
1154 * This is called, when a CPU is disabled and before rebooting, so the state of
1155 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1156 * leftovers during boot.
1158 void clear_local_APIC(void)
1163 /* APIC hasn't been mapped yet */
1164 if (!x2apic_mode && !apic_phys)
1167 maxlvt = lapic_get_maxlvt();
1169 * Masking an LVT entry can trigger a local APIC error
1170 * if the vector is zero. Mask LVTERR first to prevent this.
1173 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1174 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1177 * Careful: we have to set masks only first to deassert
1178 * any level-triggered sources.
1180 v = apic_read(APIC_LVTT);
1181 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1182 v = apic_read(APIC_LVT0);
1183 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1184 v = apic_read(APIC_LVT1);
1185 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1187 v = apic_read(APIC_LVTPC);
1188 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1191 /* lets not touch this if we didn't frob it */
1192 #ifdef CONFIG_X86_THERMAL_VECTOR
1194 v = apic_read(APIC_LVTTHMR);
1195 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1198 #ifdef CONFIG_X86_MCE_INTEL
1200 v = apic_read(APIC_LVTCMCI);
1201 if (!(v & APIC_LVT_MASKED))
1202 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1207 * Clean APIC state for other OSs:
1209 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1210 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1211 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1213 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1215 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1217 /* Integrated APIC (!82489DX) ? */
1218 if (lapic_is_integrated()) {
1220 /* Clear ESR due to Pentium errata 3AP and 11AP */
1221 apic_write(APIC_ESR, 0);
1222 apic_read(APIC_ESR);
1227 * apic_soft_disable - Clears and software disables the local APIC on hotplug
1229 * Contrary to disable_local_APIC() this does not touch the enable bit in
1230 * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC
1231 * bus would require a hardware reset as the APIC would lose track of bus
1232 * arbitration. On systems with FSB delivery APICBASE could be disabled,
1233 * but it has to be guaranteed that no interrupt is sent to the APIC while
1234 * in that state and it's not clear from the SDM whether it still responds
1235 * to INIT/SIPI messages. Stay on the safe side and use software disable.
1237 void apic_soft_disable(void)
1243 /* Soft disable APIC (implies clearing of registers for 82489DX!). */
1244 value = apic_read(APIC_SPIV);
1245 value &= ~APIC_SPIV_APIC_ENABLED;
1246 apic_write(APIC_SPIV, value);
1250 * disable_local_APIC - clear and disable the local APIC
1252 void disable_local_APIC(void)
1254 /* APIC hasn't been mapped yet */
1255 if (!x2apic_mode && !apic_phys)
1258 apic_soft_disable();
1260 #ifdef CONFIG_X86_32
1262 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1263 * restore the disabled state.
1265 if (enabled_via_apicbase) {
1268 rdmsr(MSR_IA32_APICBASE, l, h);
1269 l &= ~MSR_IA32_APICBASE_ENABLE;
1270 wrmsr(MSR_IA32_APICBASE, l, h);
1276 * If Linux enabled the LAPIC against the BIOS default disable it down before
1277 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1278 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1279 * for the case where Linux didn't enable the LAPIC.
1281 void lapic_shutdown(void)
1283 unsigned long flags;
1285 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1288 local_irq_save(flags);
1290 #ifdef CONFIG_X86_32
1291 if (!enabled_via_apicbase)
1295 disable_local_APIC();
1298 local_irq_restore(flags);
1302 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1304 void __init sync_Arb_IDs(void)
1307 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1310 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1316 apic_wait_icr_idle();
1318 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1319 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1320 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1323 enum apic_intr_mode_id apic_intr_mode __ro_after_init;
1325 static int __init apic_intr_mode_select(void)
1327 /* Check kernel option */
1329 pr_info("APIC disabled via kernel command line\n");
1334 #ifdef CONFIG_X86_64
1335 /* On 64-bit, the APIC must be integrated, Check local APIC only */
1336 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1338 pr_info("APIC disabled by BIOS\n");
1342 /* On 32-bit, the APIC may be integrated APIC or 82489DX */
1344 /* Neither 82489DX nor integrated APIC ? */
1345 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) {
1350 /* If the BIOS pretends there is an integrated APIC ? */
1351 if (!boot_cpu_has(X86_FEATURE_APIC) &&
1352 APIC_INTEGRATED(boot_cpu_apic_version)) {
1354 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n",
1355 boot_cpu_physical_apicid);
1360 /* Check MP table or ACPI MADT configuration */
1361 if (!smp_found_config) {
1362 disable_ioapic_support();
1364 pr_info("APIC: ACPI MADT or MP tables are not detected\n");
1365 return APIC_VIRTUAL_WIRE_NO_CONFIG;
1367 return APIC_VIRTUAL_WIRE;
1371 /* If SMP should be disabled, then really disable it! */
1372 if (!setup_max_cpus) {
1373 pr_info("APIC: SMP mode deactivated\n");
1374 return APIC_SYMMETRIC_IO_NO_ROUTING;
1377 if (read_apic_id() != boot_cpu_physical_apicid) {
1378 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1379 read_apic_id(), boot_cpu_physical_apicid);
1380 /* Or can we switch back to PIC here? */
1384 return APIC_SYMMETRIC_IO;
1388 * An initial setup of the virtual wire mode.
1390 void __init init_bsp_APIC(void)
1395 * Don't do the setup now if we have a SMP BIOS as the
1396 * through-I/O-APIC virtual wire mode might be active.
1398 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1402 * Do not trust the local APIC being empty at bootup.
1409 value = apic_read(APIC_SPIV);
1410 value &= ~APIC_VECTOR_MASK;
1411 value |= APIC_SPIV_APIC_ENABLED;
1413 #ifdef CONFIG_X86_32
1414 /* This bit is reserved on P4/Xeon and should be cleared */
1415 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1416 (boot_cpu_data.x86 == 15))
1417 value &= ~APIC_SPIV_FOCUS_DISABLED;
1420 value |= APIC_SPIV_FOCUS_DISABLED;
1421 value |= SPURIOUS_APIC_VECTOR;
1422 apic_write(APIC_SPIV, value);
1425 * Set up the virtual wire mode.
1427 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1428 value = APIC_DM_NMI;
1429 if (!lapic_is_integrated()) /* 82489DX */
1430 value |= APIC_LVT_LEVEL_TRIGGER;
1431 if (apic_extnmi == APIC_EXTNMI_NONE)
1432 value |= APIC_LVT_MASKED;
1433 apic_write(APIC_LVT1, value);
1436 static void __init apic_bsp_setup(bool upmode);
1438 /* Init the interrupt delivery mode for the BSP */
1439 void __init apic_intr_mode_init(void)
1441 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT);
1443 apic_intr_mode = apic_intr_mode_select();
1445 switch (apic_intr_mode) {
1447 pr_info("APIC: Keep in PIC mode(8259)\n");
1449 case APIC_VIRTUAL_WIRE:
1450 pr_info("APIC: Switch to virtual wire mode setup\n");
1451 default_setup_apic_routing();
1453 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1454 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
1456 default_setup_apic_routing();
1458 case APIC_SYMMETRIC_IO:
1459 pr_info("APIC: Switch to symmetric I/O mode setup\n");
1460 default_setup_apic_routing();
1462 case APIC_SYMMETRIC_IO_NO_ROUTING:
1463 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
1467 apic_bsp_setup(upmode);
1470 static void lapic_setup_esr(void)
1472 unsigned int oldvalue, value, maxlvt;
1474 if (!lapic_is_integrated()) {
1475 pr_info("No ESR for 82489DX.\n");
1479 if (apic->disable_esr) {
1481 * Something untraceable is creating bad interrupts on
1482 * secondary quads ... for the moment, just leave the
1483 * ESR disabled - we can't do anything useful with the
1484 * errors anyway - mbligh
1486 pr_info("Leaving ESR disabled.\n");
1490 maxlvt = lapic_get_maxlvt();
1491 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1492 apic_write(APIC_ESR, 0);
1493 oldvalue = apic_read(APIC_ESR);
1495 /* enables sending errors */
1496 value = ERROR_APIC_VECTOR;
1497 apic_write(APIC_LVTERR, value);
1500 * spec says clear errors after enabling vector.
1503 apic_write(APIC_ESR, 0);
1504 value = apic_read(APIC_ESR);
1505 if (value != oldvalue)
1506 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1507 "vector: 0x%08x after: 0x%08x\n",
1511 #define APIC_IR_REGS APIC_ISR_NR
1512 #define APIC_IR_BITS (APIC_IR_REGS * 32)
1513 #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG)
1516 unsigned long map[APIC_IR_MAPSIZE];
1517 u32 regs[APIC_IR_REGS];
1520 static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr)
1525 for (i = 0; i < APIC_IR_REGS; i++)
1526 irr->regs[i] = apic_read(APIC_IRR + i * 0x10);
1529 for (i = 0; i < APIC_IR_REGS; i++)
1530 isr->regs[i] = apic_read(APIC_ISR + i * 0x10);
1533 * If the ISR map is not empty. ACK the APIC and run another round
1534 * to verify whether a pending IRR has been unblocked and turned
1537 if (!bitmap_empty(isr->map, APIC_IR_BITS)) {
1539 * There can be multiple ISR bits set when a high priority
1540 * interrupt preempted a lower priority one. Issue an ACK
1543 for_each_set_bit(bit, isr->map, APIC_IR_BITS)
1548 return !bitmap_empty(irr->map, APIC_IR_BITS);
1552 * After a crash, we no longer service the interrupts and a pending
1553 * interrupt from previous kernel might still have ISR bit set.
1555 * Most probably by now the CPU has serviced that pending interrupt and it
1556 * might not have done the ack_APIC_irq() because it thought, interrupt
1557 * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear
1558 * the ISR bit and cpu thinks it has already serivced the interrupt. Hence
1559 * a vector might get locked. It was noticed for timer irq (vector
1560 * 0x31). Issue an extra EOI to clear ISR.
1562 * If there are pending IRR bits they turn into ISR bits after a higher
1563 * priority ISR bit has been acked.
1565 static void apic_pending_intr_clear(void)
1567 union apic_ir irr, isr;
1570 /* 512 loops are way oversized and give the APIC a chance to obey. */
1571 for (i = 0; i < 512; i++) {
1572 if (!apic_check_and_ack(&irr, &isr))
1575 /* Dump the IRR/ISR content if that failed */
1576 pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map);
1580 * setup_local_APIC - setup the local APIC
1582 * Used to setup local APIC while initializing BSP or bringing up APs.
1583 * Always called with preemption disabled.
1585 static void setup_local_APIC(void)
1587 int cpu = smp_processor_id();
1589 #ifdef CONFIG_X86_32
1590 int logical_apicid, ldr_apicid;
1594 disable_ioapic_support();
1599 * If this comes from kexec/kcrash the APIC might be enabled in
1600 * SPIV. Soft disable it before doing further initialization.
1602 value = apic_read(APIC_SPIV);
1603 value &= ~APIC_SPIV_APIC_ENABLED;
1604 apic_write(APIC_SPIV, value);
1606 #ifdef CONFIG_X86_32
1607 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1608 if (lapic_is_integrated() && apic->disable_esr) {
1609 apic_write(APIC_ESR, 0);
1610 apic_write(APIC_ESR, 0);
1611 apic_write(APIC_ESR, 0);
1612 apic_write(APIC_ESR, 0);
1616 * Double-check whether this APIC is really registered.
1617 * This is meaningless in clustered apic mode, so we skip it.
1619 BUG_ON(!apic->apic_id_registered());
1622 * Intel recommends to set DFR, LDR and TPR before enabling
1623 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1624 * document number 292116). So here it goes...
1626 apic->init_apic_ldr();
1628 #ifdef CONFIG_X86_32
1630 * APIC LDR is initialized. If logical_apicid mapping was
1631 * initialized during get_smp_config(), make sure it matches the
1634 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1635 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1636 WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid);
1637 /* always use the value from LDR */
1638 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1642 * Set Task Priority to 'accept all except vectors 0-31'. An APIC
1643 * vector in the 16-31 range could be delivered if TPR == 0, but we
1644 * would think it's an exception and terrible things will happen. We
1645 * never change this later on.
1647 value = apic_read(APIC_TASKPRI);
1648 value &= ~APIC_TPRI_MASK;
1650 apic_write(APIC_TASKPRI, value);
1652 /* Clear eventually stale ISR/IRR bits */
1653 apic_pending_intr_clear();
1656 * Now that we are all set up, enable the APIC
1658 value = apic_read(APIC_SPIV);
1659 value &= ~APIC_VECTOR_MASK;
1663 value |= APIC_SPIV_APIC_ENABLED;
1665 #ifdef CONFIG_X86_32
1667 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1668 * certain networking cards. If high frequency interrupts are
1669 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1670 * entry is masked/unmasked at a high rate as well then sooner or
1671 * later IOAPIC line gets 'stuck', no more interrupts are received
1672 * from the device. If focus CPU is disabled then the hang goes
1675 * [ This bug can be reproduced easily with a level-triggered
1676 * PCI Ne2000 networking cards and PII/PIII processors, dual
1680 * Actually disabling the focus CPU check just makes the hang less
1681 * frequent as it makes the interrupt distributon model be more
1682 * like LRU than MRU (the short-term load is more even across CPUs).
1686 * - enable focus processor (bit==0)
1687 * - 64bit mode always use processor focus
1688 * so no need to set it
1690 value &= ~APIC_SPIV_FOCUS_DISABLED;
1694 * Set spurious IRQ vector
1696 value |= SPURIOUS_APIC_VECTOR;
1697 apic_write(APIC_SPIV, value);
1699 perf_events_lapic_init();
1702 * Set up LVT0, LVT1:
1704 * set up through-local-APIC on the boot CPU's LINT0. This is not
1705 * strictly necessary in pure symmetric-IO mode, but sometimes
1706 * we delegate interrupts to the 8259A.
1709 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1711 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1712 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1713 value = APIC_DM_EXTINT;
1714 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1716 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1717 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1719 apic_write(APIC_LVT0, value);
1722 * Only the BSP sees the LINT1 NMI signal by default. This can be
1723 * modified by apic_extnmi= boot option.
1725 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1726 apic_extnmi == APIC_EXTNMI_ALL)
1727 value = APIC_DM_NMI;
1729 value = APIC_DM_NMI | APIC_LVT_MASKED;
1732 if (!lapic_is_integrated())
1733 value |= APIC_LVT_LEVEL_TRIGGER;
1734 apic_write(APIC_LVT1, value);
1736 #ifdef CONFIG_X86_MCE_INTEL
1737 /* Recheck CMCI information after local APIC is up on CPU #0 */
1743 static void end_local_APIC_setup(void)
1747 #ifdef CONFIG_X86_32
1750 /* Disable the local apic timer */
1751 value = apic_read(APIC_LVTT);
1752 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1753 apic_write(APIC_LVTT, value);
1761 * APIC setup function for application processors. Called from smpboot.c
1763 void apic_ap_setup(void)
1766 end_local_APIC_setup();
1769 #ifdef CONFIG_X86_X2APIC
1777 static int x2apic_state;
1779 static void __x2apic_disable(void)
1783 if (!boot_cpu_has(X86_FEATURE_APIC))
1786 rdmsrl(MSR_IA32_APICBASE, msr);
1787 if (!(msr & X2APIC_ENABLE))
1789 /* Disable xapic and x2apic first and then reenable xapic mode */
1790 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1791 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1792 printk_once(KERN_INFO "x2apic disabled\n");
1795 static void __x2apic_enable(void)
1799 rdmsrl(MSR_IA32_APICBASE, msr);
1800 if (msr & X2APIC_ENABLE)
1802 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1803 printk_once(KERN_INFO "x2apic enabled\n");
1806 static int __init setup_nox2apic(char *str)
1808 if (x2apic_enabled()) {
1809 int apicid = native_apic_msr_read(APIC_ID);
1811 if (apicid >= 255) {
1812 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1816 pr_warning("x2apic already enabled.\n");
1819 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1820 x2apic_state = X2APIC_DISABLED;
1824 early_param("nox2apic", setup_nox2apic);
1826 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1827 void x2apic_setup(void)
1830 * If x2apic is not in ON state, disable it if already enabled
1833 if (x2apic_state != X2APIC_ON) {
1840 static __init void x2apic_disable(void)
1842 u32 x2apic_id, state = x2apic_state;
1845 x2apic_state = X2APIC_DISABLED;
1847 if (state != X2APIC_ON)
1850 x2apic_id = read_apic_id();
1851 if (x2apic_id >= 255)
1852 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1855 register_lapic_address(mp_lapic_addr);
1858 static __init void x2apic_enable(void)
1860 if (x2apic_state != X2APIC_OFF)
1864 x2apic_state = X2APIC_ON;
1868 static __init void try_to_enable_x2apic(int remap_mode)
1870 if (x2apic_state == X2APIC_DISABLED)
1873 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1874 /* IR is required if there is APIC ID > 255 even when running
1877 if (max_physical_apicid > 255 ||
1878 !x86_init.hyper.x2apic_available()) {
1879 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1885 * without IR all CPUs can be addressed by IOAPIC/MSI
1886 * only in physical mode
1893 void __init check_x2apic(void)
1895 if (x2apic_enabled()) {
1896 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1898 x2apic_state = X2APIC_ON;
1899 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1900 x2apic_state = X2APIC_DISABLED;
1903 #else /* CONFIG_X86_X2APIC */
1904 static int __init validate_x2apic(void)
1906 if (!apic_is_x2apic_enabled())
1909 * Checkme: Can we simply turn off x2apic here instead of panic?
1911 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1913 early_initcall(validate_x2apic);
1915 static inline void try_to_enable_x2apic(int remap_mode) { }
1916 static inline void __x2apic_enable(void) { }
1917 #endif /* !CONFIG_X86_X2APIC */
1919 void __init enable_IR_x2apic(void)
1921 unsigned long flags;
1924 if (skip_ioapic_setup) {
1925 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1929 ir_stat = irq_remapping_prepare();
1930 if (ir_stat < 0 && !x2apic_supported())
1933 ret = save_ioapic_entries();
1935 pr_info("Saving IO-APIC state failed: %d\n", ret);
1939 local_irq_save(flags);
1940 legacy_pic->mask_all();
1941 mask_ioapic_entries();
1943 /* If irq_remapping_prepare() succeeded, try to enable it */
1945 ir_stat = irq_remapping_enable();
1946 /* ir_stat contains the remap mode or an error code */
1947 try_to_enable_x2apic(ir_stat);
1950 restore_ioapic_entries();
1951 legacy_pic->restore_mask();
1952 local_irq_restore(flags);
1955 #ifdef CONFIG_X86_64
1957 * Detect and enable local APICs on non-SMP boards.
1958 * Original code written by Keir Fraser.
1959 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1960 * not correctly set up (usually the APIC timer won't work etc.)
1962 static int __init detect_init_APIC(void)
1964 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1965 pr_info("No local APIC present\n");
1969 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1974 static int __init apic_verify(void)
1979 * The APIC feature bit should now be enabled
1982 features = cpuid_edx(1);
1983 if (!(features & (1 << X86_FEATURE_APIC))) {
1984 pr_warning("Could not enable APIC!\n");
1987 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1988 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1990 /* The BIOS may have set up the APIC at some other address */
1991 if (boot_cpu_data.x86 >= 6) {
1992 rdmsr(MSR_IA32_APICBASE, l, h);
1993 if (l & MSR_IA32_APICBASE_ENABLE)
1994 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1997 pr_info("Found and enabled local APIC!\n");
2001 int __init apic_force_enable(unsigned long addr)
2009 * Some BIOSes disable the local APIC in the APIC_BASE
2010 * MSR. This can only be done in software for Intel P6 or later
2011 * and AMD K7 (Model > 1) or later.
2013 if (boot_cpu_data.x86 >= 6) {
2014 rdmsr(MSR_IA32_APICBASE, l, h);
2015 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
2016 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
2017 l &= ~MSR_IA32_APICBASE_BASE;
2018 l |= MSR_IA32_APICBASE_ENABLE | addr;
2019 wrmsr(MSR_IA32_APICBASE, l, h);
2020 enabled_via_apicbase = 1;
2023 return apic_verify();
2027 * Detect and initialize APIC
2029 static int __init detect_init_APIC(void)
2031 /* Disabled by kernel option? */
2035 switch (boot_cpu_data.x86_vendor) {
2036 case X86_VENDOR_AMD:
2037 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
2038 (boot_cpu_data.x86 >= 15))
2041 case X86_VENDOR_HYGON:
2043 case X86_VENDOR_INTEL:
2044 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
2045 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
2052 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2054 * Over-ride BIOS and try to enable the local APIC only if
2055 * "lapic" specified.
2057 if (!force_enable_local_apic) {
2058 pr_info("Local APIC disabled by BIOS -- "
2059 "you can enable it with \"lapic\"\n");
2062 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
2074 pr_info("No local APIC present or hardware disabled\n");
2080 * init_apic_mappings - initialize APIC mappings
2082 void __init init_apic_mappings(void)
2084 unsigned int new_apicid;
2086 apic_check_deadline_errata();
2089 boot_cpu_physical_apicid = read_apic_id();
2093 /* If no local APIC can be found return early */
2094 if (!smp_found_config && detect_init_APIC()) {
2095 /* lets NOP'ify apic operations */
2096 pr_info("APIC: disable apic facility\n");
2099 apic_phys = mp_lapic_addr;
2102 * If the system has ACPI MADT tables or MP info, the LAPIC
2103 * address is already registered.
2105 if (!acpi_lapic && !smp_found_config)
2106 register_lapic_address(apic_phys);
2110 * Fetch the APIC ID of the BSP in case we have a
2111 * default configuration (or the MP table is broken).
2113 new_apicid = read_apic_id();
2114 if (boot_cpu_physical_apicid != new_apicid) {
2115 boot_cpu_physical_apicid = new_apicid;
2117 * yeah -- we lie about apic_version
2118 * in case if apic was disabled via boot option
2119 * but it's not a problem for SMP compiled kernel
2120 * since apic_intr_mode_select is prepared for such
2121 * a case and disable smp mode
2123 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2127 void __init register_lapic_address(unsigned long address)
2129 mp_lapic_addr = address;
2132 set_fixmap_nocache(FIX_APIC_BASE, address);
2133 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
2134 APIC_BASE, address);
2136 if (boot_cpu_physical_apicid == -1U) {
2137 boot_cpu_physical_apicid = read_apic_id();
2138 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2143 * Local APIC interrupts
2147 * This interrupt should _never_ happen with our APIC/SMP architecture
2149 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
2151 u8 vector = ~regs->orig_ax;
2155 trace_spurious_apic_entry(vector);
2157 inc_irq_stat(irq_spurious_count);
2160 * If this is a spurious interrupt then do not acknowledge
2162 if (vector == SPURIOUS_APIC_VECTOR) {
2164 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n",
2165 smp_processor_id());
2170 * If it is a vectored one, verify it's set in the ISR. If set,
2173 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
2174 if (v & (1 << (vector & 0x1f))) {
2175 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n",
2176 vector, smp_processor_id());
2179 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n",
2180 vector, smp_processor_id());
2183 trace_spurious_apic_exit(vector);
2188 * This interrupt should never happen with our APIC/SMP architecture
2190 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
2192 static const char * const error_interrupt_reason[] = {
2193 "Send CS error", /* APIC Error Bit 0 */
2194 "Receive CS error", /* APIC Error Bit 1 */
2195 "Send accept error", /* APIC Error Bit 2 */
2196 "Receive accept error", /* APIC Error Bit 3 */
2197 "Redirectable IPI", /* APIC Error Bit 4 */
2198 "Send illegal vector", /* APIC Error Bit 5 */
2199 "Received illegal vector", /* APIC Error Bit 6 */
2200 "Illegal register address", /* APIC Error Bit 7 */
2205 trace_error_apic_entry(ERROR_APIC_VECTOR);
2207 /* First tickle the hardware, only then report what went on. -- REW */
2208 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
2209 apic_write(APIC_ESR, 0);
2210 v = apic_read(APIC_ESR);
2212 atomic_inc(&irq_err_count);
2214 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2215 smp_processor_id(), v);
2220 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2225 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2227 trace_error_apic_exit(ERROR_APIC_VECTOR);
2232 * connect_bsp_APIC - attach the APIC to the interrupt system
2234 static void __init connect_bsp_APIC(void)
2236 #ifdef CONFIG_X86_32
2239 * Do not trust the local APIC being empty at bootup.
2243 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2244 * local APIC to INT and NMI lines.
2246 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2247 "enabling APIC mode.\n");
2254 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2255 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2257 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2260 void disconnect_bsp_APIC(int virt_wire_setup)
2264 #ifdef CONFIG_X86_32
2267 * Put the board back into PIC mode (has an effect only on
2268 * certain older boards). Note that APIC interrupts, including
2269 * IPIs, won't work beyond this point! The only exception are
2272 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2273 "entering PIC mode.\n");
2279 /* Go back to Virtual Wire compatibility mode */
2281 /* For the spurious interrupt use vector F, and enable it */
2282 value = apic_read(APIC_SPIV);
2283 value &= ~APIC_VECTOR_MASK;
2284 value |= APIC_SPIV_APIC_ENABLED;
2286 apic_write(APIC_SPIV, value);
2288 if (!virt_wire_setup) {
2290 * For LVT0 make it edge triggered, active high,
2291 * external and enabled
2293 value = apic_read(APIC_LVT0);
2294 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2295 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2296 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2297 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2298 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2299 apic_write(APIC_LVT0, value);
2302 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2306 * For LVT1 make it edge triggered, active high,
2309 value = apic_read(APIC_LVT1);
2310 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2311 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2312 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2313 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2314 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2315 apic_write(APIC_LVT1, value);
2319 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2320 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2321 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2322 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2324 * NOTE: Reserve 0 for BSP.
2326 static int nr_logical_cpuids = 1;
2329 * Used to store mapping between logical CPU IDs and APIC IDs.
2331 static int cpuid_to_apicid[] = {
2332 [0 ... NR_CPUS - 1] = -1,
2337 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
2338 * @id: APIC ID to check
2340 bool apic_id_is_primary_thread(unsigned int apicid)
2344 if (smp_num_siblings == 1)
2346 /* Isolate the SMT bit(s) in the APICID and check for 0 */
2347 mask = (1U << (fls(smp_num_siblings) - 1)) - 1;
2348 return !(apicid & mask);
2353 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2354 * and cpuid_to_apicid[] synchronized.
2356 static int allocate_logical_cpuid(int apicid)
2361 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2362 * check if the kernel has allocated a cpuid for it.
2364 for (i = 0; i < nr_logical_cpuids; i++) {
2365 if (cpuid_to_apicid[i] == apicid)
2369 /* Allocate a new cpuid. */
2370 if (nr_logical_cpuids >= nr_cpu_ids) {
2371 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2372 "Processor %d/0x%x and the rest are ignored.\n",
2373 nr_cpu_ids, nr_logical_cpuids, apicid);
2377 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2378 return nr_logical_cpuids++;
2381 int generic_processor_info(int apicid, int version)
2383 int cpu, max = nr_cpu_ids;
2384 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2385 phys_cpu_present_map);
2388 * boot_cpu_physical_apicid is designed to have the apicid
2389 * returned by read_apic_id(), i.e, the apicid of the
2390 * currently booting-up processor. However, on some platforms,
2391 * it is temporarily modified by the apicid reported as BSP
2392 * through MP table. Concretely:
2394 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2395 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2397 * This function is executed with the modified
2398 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2399 * parameter doesn't work to disable APs on kdump 2nd kernel.
2401 * Since fixing handling of boot_cpu_physical_apicid requires
2402 * another discussion and tests on each platform, we leave it
2403 * for now and here we use read_apic_id() directly in this
2404 * function, generic_processor_info().
2406 if (disabled_cpu_apicid != BAD_APICID &&
2407 disabled_cpu_apicid != read_apic_id() &&
2408 disabled_cpu_apicid == apicid) {
2409 int thiscpu = num_processors + disabled_cpus;
2411 pr_warning("APIC: Disabling requested cpu."
2412 " Processor %d/0x%x ignored.\n",
2420 * If boot cpu has not been detected yet, then only allow upto
2421 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2423 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2424 apicid != boot_cpu_physical_apicid) {
2425 int thiscpu = max + disabled_cpus - 1;
2428 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2429 " reached. Keeping one slot for boot cpu."
2430 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2436 if (num_processors >= nr_cpu_ids) {
2437 int thiscpu = max + disabled_cpus;
2439 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2440 "reached. Processor %d/0x%x ignored.\n",
2441 max, thiscpu, apicid);
2447 if (apicid == boot_cpu_physical_apicid) {
2449 * x86_bios_cpu_apicid is required to have processors listed
2450 * in same order as logical cpu numbers. Hence the first
2451 * entry is BSP, and so on.
2452 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2457 /* Logical cpuid 0 is reserved for BSP. */
2458 cpuid_to_apicid[0] = apicid;
2460 cpu = allocate_logical_cpuid(apicid);
2470 if (version == 0x0) {
2471 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2476 if (version != boot_cpu_apic_version) {
2477 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2478 boot_cpu_apic_version, cpu, version);
2481 if (apicid > max_physical_apicid)
2482 max_physical_apicid = apicid;
2484 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2485 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2486 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2488 #ifdef CONFIG_X86_32
2489 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2490 apic->x86_32_early_logical_apicid(cpu);
2492 set_cpu_possible(cpu, true);
2493 physid_set(apicid, phys_cpu_present_map);
2494 set_cpu_present(cpu, true);
2500 int hard_smp_processor_id(void)
2502 return read_apic_id();
2506 * Override the generic EOI implementation with an optimized version.
2507 * Only called during early boot when only one CPU is active and with
2508 * interrupts disabled, so we know this does not race with actual APIC driver
2511 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2515 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2516 /* Should happen once for each apic */
2517 WARN_ON((*drv)->eoi_write == eoi_write);
2518 (*drv)->native_eoi_write = (*drv)->eoi_write;
2519 (*drv)->eoi_write = eoi_write;
2523 static void __init apic_bsp_up_setup(void)
2525 #ifdef CONFIG_X86_64
2526 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2529 * Hack: In case of kdump, after a crash, kernel might be booting
2530 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2531 * might be zero if read from MP tables. Get it from LAPIC.
2533 # ifdef CONFIG_CRASH_DUMP
2534 boot_cpu_physical_apicid = read_apic_id();
2537 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2541 * apic_bsp_setup - Setup function for local apic and io-apic
2542 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2544 static void __init apic_bsp_setup(bool upmode)
2548 apic_bsp_up_setup();
2552 end_local_APIC_setup();
2553 irq_remap_enable_fault_handling();
2557 #ifdef CONFIG_UP_LATE_INIT
2558 void __init up_late_init(void)
2560 if (apic_intr_mode == APIC_PIC)
2563 /* Setup local timer */
2564 x86_init.timers.setup_percpu_clockev();
2575 * 'active' is true if the local APIC was enabled by us and
2576 * not the BIOS; this signifies that we are also responsible
2577 * for disabling it before entering apm/acpi suspend
2580 /* r/w apic fields */
2581 unsigned int apic_id;
2582 unsigned int apic_taskpri;
2583 unsigned int apic_ldr;
2584 unsigned int apic_dfr;
2585 unsigned int apic_spiv;
2586 unsigned int apic_lvtt;
2587 unsigned int apic_lvtpc;
2588 unsigned int apic_lvt0;
2589 unsigned int apic_lvt1;
2590 unsigned int apic_lvterr;
2591 unsigned int apic_tmict;
2592 unsigned int apic_tdcr;
2593 unsigned int apic_thmr;
2594 unsigned int apic_cmci;
2597 static int lapic_suspend(void)
2599 unsigned long flags;
2602 if (!apic_pm_state.active)
2605 maxlvt = lapic_get_maxlvt();
2607 apic_pm_state.apic_id = apic_read(APIC_ID);
2608 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2609 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2610 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2611 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2612 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2614 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2615 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2616 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2617 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2618 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2619 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2620 #ifdef CONFIG_X86_THERMAL_VECTOR
2622 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2624 #ifdef CONFIG_X86_MCE_INTEL
2626 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2629 local_irq_save(flags);
2630 disable_local_APIC();
2632 irq_remapping_disable();
2634 local_irq_restore(flags);
2638 static void lapic_resume(void)
2641 unsigned long flags;
2644 if (!apic_pm_state.active)
2647 local_irq_save(flags);
2650 * IO-APIC and PIC have their own resume routines.
2651 * We just mask them here to make sure the interrupt
2652 * subsystem is completely quiet while we enable x2apic
2653 * and interrupt-remapping.
2655 mask_ioapic_entries();
2656 legacy_pic->mask_all();
2662 * Make sure the APICBASE points to the right address
2664 * FIXME! This will be wrong if we ever support suspend on
2665 * SMP! We'll need to do this as part of the CPU restore!
2667 if (boot_cpu_data.x86 >= 6) {
2668 rdmsr(MSR_IA32_APICBASE, l, h);
2669 l &= ~MSR_IA32_APICBASE_BASE;
2670 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2671 wrmsr(MSR_IA32_APICBASE, l, h);
2675 maxlvt = lapic_get_maxlvt();
2676 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2677 apic_write(APIC_ID, apic_pm_state.apic_id);
2678 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2679 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2680 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2681 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2682 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2683 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2684 #ifdef CONFIG_X86_THERMAL_VECTOR
2686 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2688 #ifdef CONFIG_X86_MCE_INTEL
2690 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2693 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2694 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2695 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2696 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2697 apic_write(APIC_ESR, 0);
2698 apic_read(APIC_ESR);
2699 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2700 apic_write(APIC_ESR, 0);
2701 apic_read(APIC_ESR);
2703 irq_remapping_reenable(x2apic_mode);
2705 local_irq_restore(flags);
2709 * This device has no shutdown method - fully functioning local APICs
2710 * are needed on every CPU up until machine_halt/restart/poweroff.
2713 static struct syscore_ops lapic_syscore_ops = {
2714 .resume = lapic_resume,
2715 .suspend = lapic_suspend,
2718 static void apic_pm_activate(void)
2720 apic_pm_state.active = 1;
2723 static int __init init_lapic_sysfs(void)
2725 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2726 if (boot_cpu_has(X86_FEATURE_APIC))
2727 register_syscore_ops(&lapic_syscore_ops);
2732 /* local apic needs to resume before other devices access its registers. */
2733 core_initcall(init_lapic_sysfs);
2735 #else /* CONFIG_PM */
2737 static void apic_pm_activate(void) { }
2739 #endif /* CONFIG_PM */
2741 #ifdef CONFIG_X86_64
2743 static int multi_checked;
2746 static int set_multi(const struct dmi_system_id *d)
2750 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2755 static const struct dmi_system_id multi_dmi_table[] = {
2757 .callback = set_multi,
2758 .ident = "IBM System Summit2",
2760 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2761 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2767 static void dmi_check_multi(void)
2772 dmi_check_system(multi_dmi_table);
2777 * apic_is_clustered_box() -- Check if we can expect good TSC
2779 * Thus far, the major user of this is IBM's Summit2 series:
2780 * Clustered boxes may have unsynced TSC problems if they are
2782 * Use DMI to check them
2784 int apic_is_clustered_box(void)
2792 * APIC command line parameters
2794 static int __init setup_disableapic(char *arg)
2797 setup_clear_cpu_cap(X86_FEATURE_APIC);
2800 early_param("disableapic", setup_disableapic);
2802 /* same as disableapic, for compatibility */
2803 static int __init setup_nolapic(char *arg)
2805 return setup_disableapic(arg);
2807 early_param("nolapic", setup_nolapic);
2809 static int __init parse_lapic_timer_c2_ok(char *arg)
2811 local_apic_timer_c2_ok = 1;
2814 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2816 static int __init parse_disable_apic_timer(char *arg)
2818 disable_apic_timer = 1;
2821 early_param("noapictimer", parse_disable_apic_timer);
2823 static int __init parse_nolapic_timer(char *arg)
2825 disable_apic_timer = 1;
2828 early_param("nolapic_timer", parse_nolapic_timer);
2830 static int __init apic_set_verbosity(char *arg)
2833 #ifdef CONFIG_X86_64
2834 skip_ioapic_setup = 0;
2840 if (strcmp("debug", arg) == 0)
2841 apic_verbosity = APIC_DEBUG;
2842 else if (strcmp("verbose", arg) == 0)
2843 apic_verbosity = APIC_VERBOSE;
2844 #ifdef CONFIG_X86_64
2846 pr_warning("APIC Verbosity level %s not recognised"
2847 " use apic=verbose or apic=debug\n", arg);
2854 early_param("apic", apic_set_verbosity);
2856 static int __init lapic_insert_resource(void)
2861 /* Put local APIC into the resource map. */
2862 lapic_resource.start = apic_phys;
2863 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2864 insert_resource(&iomem_resource, &lapic_resource);
2870 * need call insert after e820__reserve_resources()
2871 * that is using request_resource
2873 late_initcall(lapic_insert_resource);
2875 static int __init apic_set_disabled_cpu_apicid(char *arg)
2877 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2882 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2884 static int __init apic_set_extnmi(char *arg)
2889 if (!strncmp("all", arg, 3))
2890 apic_extnmi = APIC_EXTNMI_ALL;
2891 else if (!strncmp("none", arg, 4))
2892 apic_extnmi = APIC_EXTNMI_NONE;
2893 else if (!strncmp("bsp", arg, 3))
2894 apic_extnmi = APIC_EXTNMI_BSP;
2896 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2902 early_param("apic_extnmi", apic_set_extnmi);