1 // SPDX-License-Identifier: GPL-2.0-only
3 * Local APIC handling, local APIC timers
5 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
8 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
9 * thanks to Eric Gilmore
11 * for testing these extensively.
12 * Maciej W. Rozycki : Various updates and fixes.
13 * Mikael Pettersson : Power Management for UP-APIC.
15 * Mikael Pettersson : PM converted to driver model.
18 #include <linux/perf_event.h>
19 #include <linux/kernel_stat.h>
20 #include <linux/mc146818rtc.h>
21 #include <linux/acpi_pmtmr.h>
22 #include <linux/bitmap.h>
23 #include <linux/clockchips.h>
24 #include <linux/interrupt.h>
25 #include <linux/memblock.h>
26 #include <linux/ftrace.h>
27 #include <linux/ioport.h>
28 #include <linux/export.h>
29 #include <linux/syscore_ops.h>
30 #include <linux/delay.h>
31 #include <linux/timex.h>
32 #include <linux/i8253.h>
33 #include <linux/dmar.h>
34 #include <linux/init.h>
35 #include <linux/cpu.h>
36 #include <linux/dmi.h>
37 #include <linux/smp.h>
42 #include <asm/trace/irq_vectors.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/pc-conf-reg.h>
45 #include <asm/perf_event.h>
46 #include <asm/x86_init.h>
47 #include <linux/atomic.h>
48 #include <asm/barrier.h>
49 #include <asm/mpspec.h>
50 #include <asm/i8259.h>
51 #include <asm/proto.h>
52 #include <asm/traps.h>
55 #include <asm/io_apic.h>
63 #include <asm/hypervisor.h>
64 #include <asm/cpu_device_id.h>
65 #include <asm/intel-family.h>
66 #include <asm/irq_regs.h>
71 /* Processor that is doing the boot up */
72 u32 boot_cpu_physical_apicid __ro_after_init = BAD_APICID;
73 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
75 u8 boot_cpu_apic_version __ro_after_init;
78 * This variable controls which CPUs receive external NMIs. By default,
79 * external NMIs are delivered only to the BSP.
81 static int apic_extnmi __ro_after_init = APIC_EXTNMI_BSP;
84 * Hypervisor supports 15 bits of APIC ID in MSI Extended Destination ID
86 static bool virt_ext_dest_id __ro_after_init;
88 /* For parallel bootup. */
89 unsigned long apic_mmio_base __ro_after_init;
91 static inline bool apic_accessible(void)
93 return x2apic_mode || apic_mmio_base;
97 /* Local APIC was disabled by the BIOS and enabled by the kernel */
98 static int enabled_via_apicbase __ro_after_init;
101 * Handle interrupt mode configuration register (IMCR).
102 * This register controls whether the interrupt signals
103 * that reach the BSP come from the master PIC or from the
104 * local APIC. Before entering Symmetric I/O Mode, either
105 * the BIOS or the operating system must switch out of
106 * PIC Mode by changing the IMCR.
108 static inline void imcr_pic_to_apic(void)
110 /* NMI and 8259 INTR go through APIC */
111 pc_conf_set(PC_CONF_MPS_IMCR, 0x01);
114 static inline void imcr_apic_to_pic(void)
116 /* NMI and 8259 INTR go directly to BSP */
117 pc_conf_set(PC_CONF_MPS_IMCR, 0x00);
122 * Knob to control our willingness to enable the local APIC.
126 static int force_enable_local_apic __initdata;
129 * APIC command line parameters
131 static int __init parse_lapic(char *arg)
133 if (IS_ENABLED(CONFIG_X86_32) && !arg)
134 force_enable_local_apic = 1;
135 else if (arg && !strncmp(arg, "notscdeadline", 13))
136 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
139 early_param("lapic", parse_lapic);
142 static int apic_calibrate_pmtmr __initdata;
143 static __init int setup_apicpmtimer(char *s)
145 apic_calibrate_pmtmr = 1;
149 __setup("apicpmtimer", setup_apicpmtimer);
152 static unsigned long mp_lapic_addr __ro_after_init;
153 bool apic_is_disabled __ro_after_init;
154 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
155 static int disable_apic_timer __initdata;
156 /* Local APIC timer works in C2 */
157 int local_apic_timer_c2_ok __ro_after_init;
158 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
161 * Debug level, exported for io_apic.c
163 int apic_verbosity __ro_after_init;
165 int pic_mode __ro_after_init;
167 /* Have we found an MP table */
168 int smp_found_config __ro_after_init;
170 static struct resource lapic_resource = {
171 .name = "Local APIC",
172 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
175 unsigned int lapic_timer_period = 0;
177 static void apic_pm_activate(void);
180 * Get the LAPIC version
182 static inline int lapic_get_version(void)
184 return GET_APIC_VERSION(apic_read(APIC_LVR));
188 * Check, if the APIC is integrated or a separate chip
190 static inline int lapic_is_integrated(void)
192 return APIC_INTEGRATED(lapic_get_version());
196 * Check, whether this is a modern or a first generation APIC
198 static int modern_apic(void)
200 /* AMD systems use old APIC versions, so check the CPU */
201 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
202 boot_cpu_data.x86 >= 0xf)
205 /* Hygon systems use modern APIC */
206 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
209 return lapic_get_version() >= 0x14;
213 * right after this call apic become NOOP driven
214 * so apic->write/read doesn't do anything
216 static void __init apic_disable(void)
218 apic_install_driver(&apic_noop);
221 void native_apic_icr_write(u32 low, u32 id)
225 local_irq_save(flags);
226 apic_write(APIC_ICR2, SET_XAPIC_DEST_FIELD(id));
227 apic_write(APIC_ICR, low);
228 local_irq_restore(flags);
231 u64 native_apic_icr_read(void)
235 icr2 = apic_read(APIC_ICR2);
236 icr1 = apic_read(APIC_ICR);
238 return icr1 | ((u64)icr2 << 32);
242 * lapic_get_maxlvt - get the maximum number of local vector table entries
244 int lapic_get_maxlvt(void)
247 * - we always have APIC integrated on 64bit mode
248 * - 82489DXs do not report # of LVT entries
250 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2;
258 #define APIC_DIVISOR 16
259 #define TSC_DIVISOR 8
261 /* i82489DX specific */
262 #define I82489DX_BASE_DIVIDER (((0x2) << 18))
265 * This function sets up the local APIC timer, with a timeout of
266 * 'clocks' APIC bus clock. During calibration we actually call
267 * this function twice on the boot CPU, once with a bogus timeout
268 * value, second time for real. The other (noncalibrating) CPUs
269 * call this function only once, with the real, calibrated value.
271 * We do reads before writes even if unnecessary, to get around the
272 * P5 APIC double write bug.
274 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
276 unsigned int lvtt_value, tmp_value;
278 lvtt_value = LOCAL_TIMER_VECTOR;
280 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
281 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
282 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
285 * The i82489DX APIC uses bit 18 and 19 for the base divider. This
286 * overlaps with bit 18 on integrated APICs, but is not documented
287 * in the SDM. No problem though. i82489DX equipped systems do not
288 * have TSC deadline timer.
290 if (!lapic_is_integrated())
291 lvtt_value |= I82489DX_BASE_DIVIDER;
294 lvtt_value |= APIC_LVT_MASKED;
296 apic_write(APIC_LVTT, lvtt_value);
298 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
300 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
301 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
302 * According to Intel, MFENCE can do the serialization here.
304 asm volatile("mfence" : : : "memory");
311 tmp_value = apic_read(APIC_TDCR);
312 apic_write(APIC_TDCR,
313 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
317 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
321 * Setup extended LVT, AMD specific
323 * Software should use the LVT offsets the BIOS provides. The offsets
324 * are determined by the subsystems using it like those for MCE
325 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
326 * are supported. Beginning with family 10h at least 4 offsets are
329 * Since the offsets must be consistent for all cores, we keep track
330 * of the LVT offsets in software and reserve the offset for the same
331 * vector also to be used on other cores. An offset is freed by
332 * setting the entry to APIC_EILVT_MASKED.
334 * If the BIOS is right, there should be no conflicts. Otherwise a
335 * "[Firmware Bug]: ..." error message is generated. However, if
336 * software does not properly determines the offsets, it is not
337 * necessarily a BIOS bug.
340 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
342 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
344 return (old & APIC_EILVT_MASKED)
345 || (new == APIC_EILVT_MASKED)
346 || ((new & ~APIC_EILVT_MASKED) == old);
349 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
351 unsigned int rsvd, vector;
353 if (offset >= APIC_EILVT_NR_MAX)
356 rsvd = atomic_read(&eilvt_offsets[offset]);
358 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
359 if (vector && !eilvt_entry_is_changeable(vector, new))
360 /* may not change if vectors are different */
362 } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new));
364 rsvd = new & ~APIC_EILVT_MASKED;
365 if (rsvd && rsvd != vector)
366 pr_info("LVT offset %d assigned for vector 0x%02x\n",
373 * If mask=1, the LVT entry does not generate interrupts while mask=0
374 * enables the vector. See also the BKDGs. Must be called with
375 * preemption disabled.
378 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
380 unsigned long reg = APIC_EILVTn(offset);
381 unsigned int new, old, reserved;
383 new = (mask << 16) | (msg_type << 8) | vector;
384 old = apic_read(reg);
385 reserved = reserve_eilvt_offset(offset, new);
387 if (reserved != new) {
388 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
389 "vector 0x%x, but the register is already in use for "
390 "vector 0x%x on another cpu\n",
391 smp_processor_id(), reg, offset, new, reserved);
395 if (!eilvt_entry_is_changeable(old, new)) {
396 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
397 "vector 0x%x, but the register is already in use for "
398 "vector 0x%x on this cpu\n",
399 smp_processor_id(), reg, offset, new, old);
403 apic_write(reg, new);
407 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
410 * Program the next event, relative to now
412 static int lapic_next_event(unsigned long delta,
413 struct clock_event_device *evt)
415 apic_write(APIC_TMICT, delta);
419 static int lapic_next_deadline(unsigned long delta,
420 struct clock_event_device *evt)
424 /* This MSR is special and need a special fence: */
428 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
432 static int lapic_timer_shutdown(struct clock_event_device *evt)
436 /* Lapic used as dummy for broadcast ? */
437 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
440 v = apic_read(APIC_LVTT);
441 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
442 apic_write(APIC_LVTT, v);
443 apic_write(APIC_TMICT, 0);
448 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
450 /* Lapic used as dummy for broadcast ? */
451 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
454 __setup_APIC_LVTT(lapic_timer_period, oneshot, 1);
458 static int lapic_timer_set_periodic(struct clock_event_device *evt)
460 return lapic_timer_set_periodic_oneshot(evt, false);
463 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
465 return lapic_timer_set_periodic_oneshot(evt, true);
469 * Local APIC timer broadcast function
471 static void lapic_timer_broadcast(const struct cpumask *mask)
474 __apic_send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
480 * The local apic timer can be used for any function which is CPU local.
482 static struct clock_event_device lapic_clockevent = {
484 .features = CLOCK_EVT_FEAT_PERIODIC |
485 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
486 | CLOCK_EVT_FEAT_DUMMY,
488 .set_state_shutdown = lapic_timer_shutdown,
489 .set_state_periodic = lapic_timer_set_periodic,
490 .set_state_oneshot = lapic_timer_set_oneshot,
491 .set_state_oneshot_stopped = lapic_timer_shutdown,
492 .set_next_event = lapic_next_event,
493 .broadcast = lapic_timer_broadcast,
497 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
499 static const struct x86_cpu_id deadline_match[] __initconst = {
500 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x2, 0x2), 0x3a), /* EP */
501 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x4, 0x4), 0x0f), /* EX */
503 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_X, 0x0b000020),
505 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x2, 0x2), 0x00000011),
506 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x3, 0x3), 0x0700000e),
507 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x4, 0x4), 0x0f00000c),
508 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x5, 0x5), 0x0e000003),
510 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x3, 0x3), 0x01000136),
511 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x4, 0x4), 0x02000014),
512 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x5, 0xf), 0),
514 X86_MATCH_INTEL_FAM6_MODEL( HASWELL, 0x22),
515 X86_MATCH_INTEL_FAM6_MODEL( HASWELL_L, 0x20),
516 X86_MATCH_INTEL_FAM6_MODEL( HASWELL_G, 0x17),
518 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL, 0x25),
519 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_G, 0x17),
521 X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE_L, 0xb2),
522 X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE, 0xb2),
524 X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE_L, 0x52),
525 X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE, 0x52),
530 static __init bool apic_validate_deadline_timer(void)
532 const struct x86_cpu_id *m;
535 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
537 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
540 m = x86_match_cpu(deadline_match);
544 rev = (u32)m->driver_data;
546 if (boot_cpu_data.microcode >= rev)
549 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
550 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
551 "please update microcode to version: 0x%x (or later)\n", rev);
556 * Setup the local APIC timer for this CPU. Copy the initialized values
557 * of the boot CPU and register the clock event in the framework.
559 static void setup_APIC_timer(void)
561 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
563 if (this_cpu_has(X86_FEATURE_ARAT)) {
564 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
565 /* Make LAPIC timer preferable over percpu HPET */
566 lapic_clockevent.rating = 150;
569 memcpy(levt, &lapic_clockevent, sizeof(*levt));
570 levt->cpumask = cpumask_of(smp_processor_id());
572 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
573 levt->name = "lapic-deadline";
574 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
575 CLOCK_EVT_FEAT_DUMMY);
576 levt->set_next_event = lapic_next_deadline;
577 clockevents_config_and_register(levt,
578 tsc_khz * (1000 / TSC_DIVISOR),
581 clockevents_register_device(levt);
585 * Install the updated TSC frequency from recalibration at the TSC
586 * deadline clockevent devices.
588 static void __lapic_update_tsc_freq(void *info)
590 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
592 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
595 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
598 void lapic_update_tsc_freq(void)
601 * The clockevent device's ->mult and ->shift can both be
602 * changed. In order to avoid races, schedule the frequency
603 * update code on each CPU.
605 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
609 * In this functions we calibrate APIC bus clocks to the external timer.
611 * We want to do the calibration only once since we want to have local timer
612 * irqs synchronous. CPUs connected by the same APIC bus have the very same bus
615 * This was previously done by reading the PIT/HPET and waiting for a wrap
616 * around to find out, that a tick has elapsed. I have a box, where the PIT
617 * readout is broken, so it never gets out of the wait loop again. This was
618 * also reported by others.
620 * Monitoring the jiffies value is inaccurate and the clockevents
621 * infrastructure allows us to do a simple substitution of the interrupt
624 * The calibration routine also uses the pm_timer when possible, as the PIT
625 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
626 * back to normal later in the boot process).
629 #define LAPIC_CAL_LOOPS (HZ/10)
631 static __initdata int lapic_cal_loops = -1;
632 static __initdata long lapic_cal_t1, lapic_cal_t2;
633 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
634 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
635 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
638 * Temporary interrupt handler and polled calibration function.
640 static void __init lapic_cal_handler(struct clock_event_device *dev)
642 unsigned long long tsc = 0;
643 long tapic = apic_read(APIC_TMCCT);
644 unsigned long pm = acpi_pm_read_early();
646 if (boot_cpu_has(X86_FEATURE_TSC))
649 switch (lapic_cal_loops++) {
651 lapic_cal_t1 = tapic;
652 lapic_cal_tsc1 = tsc;
654 lapic_cal_j1 = jiffies;
657 case LAPIC_CAL_LOOPS:
658 lapic_cal_t2 = tapic;
659 lapic_cal_tsc2 = tsc;
660 if (pm < lapic_cal_pm1)
661 pm += ACPI_PM_OVRRUN;
663 lapic_cal_j2 = jiffies;
669 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
671 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
672 const long pm_thresh = pm_100ms / 100;
676 #ifndef CONFIG_X86_PM_TIMER
680 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
682 /* Check, if the PM timer is available */
686 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
688 if (deltapm > (pm_100ms - pm_thresh) &&
689 deltapm < (pm_100ms + pm_thresh)) {
690 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
694 res = (((u64)deltapm) * mult) >> 22;
695 do_div(res, 1000000);
696 pr_warn("APIC calibration not consistent "
697 "with PM-Timer: %ldms instead of 100ms\n", (long)res);
699 /* Correct the lapic counter value */
700 res = (((u64)(*delta)) * pm_100ms);
701 do_div(res, deltapm);
702 pr_info("APIC delta adjusted to PM-Timer: "
703 "%lu (%ld)\n", (unsigned long)res, *delta);
706 /* Correct the tsc counter value */
707 if (boot_cpu_has(X86_FEATURE_TSC)) {
708 res = (((u64)(*deltatsc)) * pm_100ms);
709 do_div(res, deltapm);
710 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
711 "PM-Timer: %lu (%ld)\n",
712 (unsigned long)res, *deltatsc);
713 *deltatsc = (long)res;
719 static int __init lapic_init_clockevent(void)
721 if (!lapic_timer_period)
724 /* Calculate the scaled math multiplication factor */
725 lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR,
726 TICK_NSEC, lapic_clockevent.shift);
727 lapic_clockevent.max_delta_ns =
728 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
729 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
730 lapic_clockevent.min_delta_ns =
731 clockevent_delta2ns(0xF, &lapic_clockevent);
732 lapic_clockevent.min_delta_ticks = 0xF;
737 bool __init apic_needs_pit(void)
740 * If the frequencies are not known, PIT is required for both TSC
741 * and apic timer calibration.
743 if (!tsc_khz || !cpu_khz)
746 /* Is there an APIC at all or is it disabled? */
747 if (!boot_cpu_has(X86_FEATURE_APIC) || apic_is_disabled)
751 * If interrupt delivery mode is legacy PIC or virtual wire without
752 * configuration, the local APIC timer won't be set up. Make sure
753 * that the PIT is initialized.
755 if (apic_intr_mode == APIC_PIC ||
756 apic_intr_mode == APIC_VIRTUAL_WIRE_NO_CONFIG)
759 /* Virt guests may lack ARAT, but still have DEADLINE */
760 if (!boot_cpu_has(X86_FEATURE_ARAT))
763 /* Deadline timer is based on TSC so no further PIT action required */
764 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
767 /* APIC timer disabled? */
768 if (disable_apic_timer)
771 * The APIC timer frequency is known already, no PIT calibration
772 * required. If unknown, let the PIT be initialized.
774 return lapic_timer_period == 0;
777 static int __init calibrate_APIC_clock(void)
779 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
780 u64 tsc_perj = 0, tsc_start = 0;
781 unsigned long jif_start;
782 unsigned long deltaj;
783 long delta, deltatsc;
784 int pm_referenced = 0;
786 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
790 * Check if lapic timer has already been calibrated by platform
791 * specific routine, such as tsc calibration code. If so just fill
792 * in the clockevent structure and return.
794 if (!lapic_init_clockevent()) {
795 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
798 * Direct calibration methods must have an always running
799 * local APIC timer, no need for broadcast timer.
801 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
805 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
806 "calibrating APIC timer ...\n");
809 * There are platforms w/o global clockevent devices. Instead of
810 * making the calibration conditional on that, use a polling based
811 * approach everywhere.
816 * Setup the APIC counter to maximum. There is no way the lapic
817 * can underflow in the 100ms detection time frame
819 __setup_APIC_LVTT(0xffffffff, 0, 0);
822 * Methods to terminate the calibration loop:
823 * 1) Global clockevent if available (jiffies)
824 * 2) TSC if available and frequency is known
826 jif_start = READ_ONCE(jiffies);
830 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ);
834 * Enable interrupts so the tick can fire, if a global
835 * clockevent device is available
839 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) {
840 /* Wait for a tick to elapse */
843 u64 tsc_now = rdtsc();
844 if ((tsc_now - tsc_start) >= tsc_perj) {
845 tsc_start += tsc_perj;
849 unsigned long jif_now = READ_ONCE(jiffies);
851 if (time_after(jif_now, jif_start)) {
859 /* Invoke the calibration routine */
861 lapic_cal_handler(NULL);
867 /* Build delta t1-t2 as apic timer counts down */
868 delta = lapic_cal_t1 - lapic_cal_t2;
869 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
871 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
873 /* we trust the PM based calibration if possible */
874 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
877 lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
878 lapic_init_clockevent();
880 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
881 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
882 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
885 if (boot_cpu_has(X86_FEATURE_TSC)) {
886 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
888 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
889 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
892 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
894 lapic_timer_period / (1000000 / HZ),
895 lapic_timer_period % (1000000 / HZ));
898 * Do a sanity check on the APIC calibration result
900 if (lapic_timer_period < (1000000 / HZ)) {
902 pr_warn("APIC frequency too slow, disabling apic timer\n");
906 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
909 * PM timer calibration failed or not turned on so lets try APIC
910 * timer based calibration, if a global clockevent device is
913 if (!pm_referenced && global_clock_event) {
914 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
917 * Setup the apic timer manually
919 levt->event_handler = lapic_cal_handler;
920 lapic_timer_set_periodic(levt);
921 lapic_cal_loops = -1;
923 /* Let the interrupts run */
926 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
929 /* Stop the lapic timer */
931 lapic_timer_shutdown(levt);
934 deltaj = lapic_cal_j2 - lapic_cal_j1;
935 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
937 /* Check, if the jiffies result is consistent */
938 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
939 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
941 levt->features |= CLOCK_EVT_FEAT_DUMMY;
945 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
946 pr_warn("APIC timer disabled due to verification failure\n");
954 * Setup the boot APIC
956 * Calibrate and verify the result.
958 void __init setup_boot_APIC_clock(void)
961 * The local apic timer can be disabled via the kernel
962 * commandline or from the CPU detection code. Register the lapic
963 * timer as a dummy clock event source on SMP systems, so the
964 * broadcast mechanism is used. On UP systems simply ignore it.
966 if (disable_apic_timer) {
967 pr_info("Disabling APIC timer\n");
968 /* No broadcast on UP ! */
969 if (num_possible_cpus() > 1) {
970 lapic_clockevent.mult = 1;
976 if (calibrate_APIC_clock()) {
977 /* No broadcast on UP ! */
978 if (num_possible_cpus() > 1)
984 * If nmi_watchdog is set to IO_APIC, we need the
985 * PIT/HPET going. Otherwise register lapic as a dummy
988 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
990 /* Setup the lapic or request the broadcast */
992 amd_e400_c1e_apic_setup();
995 void setup_secondary_APIC_clock(void)
998 amd_e400_c1e_apic_setup();
1002 * The guts of the apic timer interrupt
1004 static void local_apic_timer_interrupt(void)
1006 struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1009 * Normally we should not be here till LAPIC has been initialized but
1010 * in some cases like kdump, its possible that there is a pending LAPIC
1011 * timer interrupt from previous kernel's context and is delivered in
1012 * new kernel the moment interrupts are enabled.
1014 * Interrupts are enabled early and LAPIC is setup much later, hence
1015 * its possible that when we get here evt->event_handler is NULL.
1016 * Check for event_handler being NULL and discard the interrupt as
1019 if (!evt->event_handler) {
1020 pr_warn("Spurious LAPIC timer interrupt on cpu %d\n",
1021 smp_processor_id());
1023 lapic_timer_shutdown(evt);
1028 * the NMI deadlock-detector uses this.
1030 inc_irq_stat(apic_timer_irqs);
1032 evt->event_handler(evt);
1036 * Local APIC timer interrupt. This is the most natural way for doing
1037 * local interrupts, but local timer interrupts can be emulated by
1038 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1040 * [ if a single-CPU system runs an SMP kernel then we call the local
1041 * interrupt as well. Thus we cannot inline the local irq ... ]
1043 DEFINE_IDTENTRY_SYSVEC(sysvec_apic_timer_interrupt)
1045 struct pt_regs *old_regs = set_irq_regs(regs);
1048 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1049 local_apic_timer_interrupt();
1050 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1052 set_irq_regs(old_regs);
1056 * Local APIC start and shutdown
1060 * clear_local_APIC - shutdown the local APIC
1062 * This is called, when a CPU is disabled and before rebooting, so the state of
1063 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1064 * leftovers during boot.
1066 void clear_local_APIC(void)
1071 if (!apic_accessible())
1074 maxlvt = lapic_get_maxlvt();
1076 * Masking an LVT entry can trigger a local APIC error
1077 * if the vector is zero. Mask LVTERR first to prevent this.
1080 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1081 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1084 * Careful: we have to set masks only first to deassert
1085 * any level-triggered sources.
1087 v = apic_read(APIC_LVTT);
1088 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1089 v = apic_read(APIC_LVT0);
1090 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1091 v = apic_read(APIC_LVT1);
1092 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1094 v = apic_read(APIC_LVTPC);
1095 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1098 /* lets not touch this if we didn't frob it */
1099 #ifdef CONFIG_X86_THERMAL_VECTOR
1101 v = apic_read(APIC_LVTTHMR);
1102 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1105 #ifdef CONFIG_X86_MCE_INTEL
1107 v = apic_read(APIC_LVTCMCI);
1108 if (!(v & APIC_LVT_MASKED))
1109 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1114 * Clean APIC state for other OSs:
1116 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1117 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1118 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1120 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1122 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1124 /* Integrated APIC (!82489DX) ? */
1125 if (lapic_is_integrated()) {
1127 /* Clear ESR due to Pentium errata 3AP and 11AP */
1128 apic_write(APIC_ESR, 0);
1129 apic_read(APIC_ESR);
1134 * apic_soft_disable - Clears and software disables the local APIC on hotplug
1136 * Contrary to disable_local_APIC() this does not touch the enable bit in
1137 * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC
1138 * bus would require a hardware reset as the APIC would lose track of bus
1139 * arbitration. On systems with FSB delivery APICBASE could be disabled,
1140 * but it has to be guaranteed that no interrupt is sent to the APIC while
1141 * in that state and it's not clear from the SDM whether it still responds
1142 * to INIT/SIPI messages. Stay on the safe side and use software disable.
1144 void apic_soft_disable(void)
1150 /* Soft disable APIC (implies clearing of registers for 82489DX!). */
1151 value = apic_read(APIC_SPIV);
1152 value &= ~APIC_SPIV_APIC_ENABLED;
1153 apic_write(APIC_SPIV, value);
1157 * disable_local_APIC - clear and disable the local APIC
1159 void disable_local_APIC(void)
1161 if (!apic_accessible())
1164 apic_soft_disable();
1166 #ifdef CONFIG_X86_32
1168 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1169 * restore the disabled state.
1171 if (enabled_via_apicbase) {
1174 rdmsr(MSR_IA32_APICBASE, l, h);
1175 l &= ~MSR_IA32_APICBASE_ENABLE;
1176 wrmsr(MSR_IA32_APICBASE, l, h);
1182 * If Linux enabled the LAPIC against the BIOS default disable it down before
1183 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1184 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1185 * for the case where Linux didn't enable the LAPIC.
1187 void lapic_shutdown(void)
1189 unsigned long flags;
1191 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1194 local_irq_save(flags);
1196 #ifdef CONFIG_X86_32
1197 if (!enabled_via_apicbase)
1201 disable_local_APIC();
1204 local_irq_restore(flags);
1208 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1210 void __init sync_Arb_IDs(void)
1213 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1216 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1222 apic_wait_icr_idle();
1224 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1225 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1226 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1229 enum apic_intr_mode_id apic_intr_mode __ro_after_init;
1231 static int __init __apic_intr_mode_select(void)
1233 /* Check kernel option */
1234 if (apic_is_disabled) {
1235 pr_info("APIC disabled via kernel command line\n");
1240 #ifdef CONFIG_X86_64
1241 /* On 64-bit, the APIC must be integrated, Check local APIC only */
1242 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1243 apic_is_disabled = true;
1244 pr_info("APIC disabled by BIOS\n");
1248 /* On 32-bit, the APIC may be integrated APIC or 82489DX */
1250 /* Neither 82489DX nor integrated APIC ? */
1251 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) {
1252 apic_is_disabled = true;
1256 /* If the BIOS pretends there is an integrated APIC ? */
1257 if (!boot_cpu_has(X86_FEATURE_APIC) &&
1258 APIC_INTEGRATED(boot_cpu_apic_version)) {
1259 apic_is_disabled = true;
1260 pr_err(FW_BUG "Local APIC not detected, force emulation\n");
1265 /* Check MP table or ACPI MADT configuration */
1266 if (!smp_found_config) {
1267 disable_ioapic_support();
1269 pr_info("APIC: ACPI MADT or MP tables are not detected\n");
1270 return APIC_VIRTUAL_WIRE_NO_CONFIG;
1272 return APIC_VIRTUAL_WIRE;
1276 /* If SMP should be disabled, then really disable it! */
1277 if (!setup_max_cpus) {
1278 pr_info("APIC: SMP mode deactivated\n");
1279 return APIC_SYMMETRIC_IO_NO_ROUTING;
1283 return APIC_SYMMETRIC_IO;
1286 /* Select the interrupt delivery mode for the BSP */
1287 void __init apic_intr_mode_select(void)
1289 apic_intr_mode = __apic_intr_mode_select();
1293 * An initial setup of the virtual wire mode.
1295 void __init init_bsp_APIC(void)
1300 * Don't do the setup now if we have a SMP BIOS as the
1301 * through-I/O-APIC virtual wire mode might be active.
1303 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1307 * Do not trust the local APIC being empty at bootup.
1314 value = apic_read(APIC_SPIV);
1315 value &= ~APIC_VECTOR_MASK;
1316 value |= APIC_SPIV_APIC_ENABLED;
1318 #ifdef CONFIG_X86_32
1319 /* This bit is reserved on P4/Xeon and should be cleared */
1320 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1321 (boot_cpu_data.x86 == 15))
1322 value &= ~APIC_SPIV_FOCUS_DISABLED;
1325 value |= APIC_SPIV_FOCUS_DISABLED;
1326 value |= SPURIOUS_APIC_VECTOR;
1327 apic_write(APIC_SPIV, value);
1330 * Set up the virtual wire mode.
1332 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1333 value = APIC_DM_NMI;
1334 if (!lapic_is_integrated()) /* 82489DX */
1335 value |= APIC_LVT_LEVEL_TRIGGER;
1336 if (apic_extnmi == APIC_EXTNMI_NONE)
1337 value |= APIC_LVT_MASKED;
1338 apic_write(APIC_LVT1, value);
1341 static void __init apic_bsp_setup(bool upmode);
1343 /* Init the interrupt delivery mode for the BSP */
1344 void __init apic_intr_mode_init(void)
1346 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT);
1348 switch (apic_intr_mode) {
1350 pr_info("APIC: Keep in PIC mode(8259)\n");
1352 case APIC_VIRTUAL_WIRE:
1353 pr_info("APIC: Switch to virtual wire mode setup\n");
1355 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1356 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
1359 case APIC_SYMMETRIC_IO:
1360 pr_info("APIC: Switch to symmetric I/O mode setup\n");
1362 case APIC_SYMMETRIC_IO_NO_ROUTING:
1363 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
1367 x86_64_probe_apic();
1369 x86_32_install_bigsmp();
1371 if (x86_platform.apic_post_init)
1372 x86_platform.apic_post_init();
1374 apic_bsp_setup(upmode);
1377 static void lapic_setup_esr(void)
1379 unsigned int oldvalue, value, maxlvt;
1381 if (!lapic_is_integrated()) {
1382 pr_info("No ESR for 82489DX.\n");
1386 if (apic->disable_esr) {
1388 * Something untraceable is creating bad interrupts on
1389 * secondary quads ... for the moment, just leave the
1390 * ESR disabled - we can't do anything useful with the
1391 * errors anyway - mbligh
1393 pr_info("Leaving ESR disabled.\n");
1397 maxlvt = lapic_get_maxlvt();
1398 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1399 apic_write(APIC_ESR, 0);
1400 oldvalue = apic_read(APIC_ESR);
1402 /* enables sending errors */
1403 value = ERROR_APIC_VECTOR;
1404 apic_write(APIC_LVTERR, value);
1407 * spec says clear errors after enabling vector.
1410 apic_write(APIC_ESR, 0);
1411 value = apic_read(APIC_ESR);
1412 if (value != oldvalue)
1413 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1414 "vector: 0x%08x after: 0x%08x\n",
1418 #define APIC_IR_REGS APIC_ISR_NR
1419 #define APIC_IR_BITS (APIC_IR_REGS * 32)
1420 #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG)
1423 unsigned long map[APIC_IR_MAPSIZE];
1424 u32 regs[APIC_IR_REGS];
1427 static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr)
1432 for (i = 0; i < APIC_IR_REGS; i++)
1433 irr->regs[i] = apic_read(APIC_IRR + i * 0x10);
1436 for (i = 0; i < APIC_IR_REGS; i++)
1437 isr->regs[i] = apic_read(APIC_ISR + i * 0x10);
1440 * If the ISR map is not empty. ACK the APIC and run another round
1441 * to verify whether a pending IRR has been unblocked and turned
1444 if (!bitmap_empty(isr->map, APIC_IR_BITS)) {
1446 * There can be multiple ISR bits set when a high priority
1447 * interrupt preempted a lower priority one. Issue an ACK
1450 for_each_set_bit(bit, isr->map, APIC_IR_BITS)
1455 return !bitmap_empty(irr->map, APIC_IR_BITS);
1459 * After a crash, we no longer service the interrupts and a pending
1460 * interrupt from previous kernel might still have ISR bit set.
1462 * Most probably by now the CPU has serviced that pending interrupt and it
1463 * might not have done the apic_eoi() because it thought, interrupt
1464 * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear
1465 * the ISR bit and cpu thinks it has already serviced the interrupt. Hence
1466 * a vector might get locked. It was noticed for timer irq (vector
1467 * 0x31). Issue an extra EOI to clear ISR.
1469 * If there are pending IRR bits they turn into ISR bits after a higher
1470 * priority ISR bit has been acked.
1472 static void apic_pending_intr_clear(void)
1474 union apic_ir irr, isr;
1477 /* 512 loops are way oversized and give the APIC a chance to obey. */
1478 for (i = 0; i < 512; i++) {
1479 if (!apic_check_and_ack(&irr, &isr))
1482 /* Dump the IRR/ISR content if that failed */
1483 pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map);
1487 * setup_local_APIC - setup the local APIC
1489 * Used to setup local APIC while initializing BSP or bringing up APs.
1490 * Always called with preemption disabled.
1492 static void setup_local_APIC(void)
1494 int cpu = smp_processor_id();
1497 if (apic_is_disabled) {
1498 disable_ioapic_support();
1503 * If this comes from kexec/kcrash the APIC might be enabled in
1504 * SPIV. Soft disable it before doing further initialization.
1506 value = apic_read(APIC_SPIV);
1507 value &= ~APIC_SPIV_APIC_ENABLED;
1508 apic_write(APIC_SPIV, value);
1510 #ifdef CONFIG_X86_32
1511 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1512 if (lapic_is_integrated() && apic->disable_esr) {
1513 apic_write(APIC_ESR, 0);
1514 apic_write(APIC_ESR, 0);
1515 apic_write(APIC_ESR, 0);
1516 apic_write(APIC_ESR, 0);
1520 * Intel recommends to set DFR, LDR and TPR before enabling
1521 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1522 * document number 292116).
1524 * Except for APICs which operate in physical destination mode.
1526 if (apic->init_apic_ldr)
1527 apic->init_apic_ldr();
1530 * Set Task Priority to 'accept all except vectors 0-31'. An APIC
1531 * vector in the 16-31 range could be delivered if TPR == 0, but we
1532 * would think it's an exception and terrible things will happen. We
1533 * never change this later on.
1535 value = apic_read(APIC_TASKPRI);
1536 value &= ~APIC_TPRI_MASK;
1538 apic_write(APIC_TASKPRI, value);
1540 /* Clear eventually stale ISR/IRR bits */
1541 apic_pending_intr_clear();
1544 * Now that we are all set up, enable the APIC
1546 value = apic_read(APIC_SPIV);
1547 value &= ~APIC_VECTOR_MASK;
1551 value |= APIC_SPIV_APIC_ENABLED;
1553 #ifdef CONFIG_X86_32
1555 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1556 * certain networking cards. If high frequency interrupts are
1557 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1558 * entry is masked/unmasked at a high rate as well then sooner or
1559 * later IOAPIC line gets 'stuck', no more interrupts are received
1560 * from the device. If focus CPU is disabled then the hang goes
1563 * [ This bug can be reproduced easily with a level-triggered
1564 * PCI Ne2000 networking cards and PII/PIII processors, dual
1568 * Actually disabling the focus CPU check just makes the hang less
1569 * frequent as it makes the interrupt distribution model be more
1570 * like LRU than MRU (the short-term load is more even across CPUs).
1574 * - enable focus processor (bit==0)
1575 * - 64bit mode always use processor focus
1576 * so no need to set it
1578 value &= ~APIC_SPIV_FOCUS_DISABLED;
1582 * Set spurious IRQ vector
1584 value |= SPURIOUS_APIC_VECTOR;
1585 apic_write(APIC_SPIV, value);
1587 perf_events_lapic_init();
1590 * Set up LVT0, LVT1:
1592 * set up through-local-APIC on the boot CPU's LINT0. This is not
1593 * strictly necessary in pure symmetric-IO mode, but sometimes
1594 * we delegate interrupts to the 8259A.
1597 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1599 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1600 if (!cpu && (pic_mode || !value || ioapic_is_disabled)) {
1601 value = APIC_DM_EXTINT;
1602 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1604 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1605 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1607 apic_write(APIC_LVT0, value);
1610 * Only the BSP sees the LINT1 NMI signal by default. This can be
1611 * modified by apic_extnmi= boot option.
1613 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1614 apic_extnmi == APIC_EXTNMI_ALL)
1615 value = APIC_DM_NMI;
1617 value = APIC_DM_NMI | APIC_LVT_MASKED;
1620 if (!lapic_is_integrated())
1621 value |= APIC_LVT_LEVEL_TRIGGER;
1622 apic_write(APIC_LVT1, value);
1624 #ifdef CONFIG_X86_MCE_INTEL
1625 /* Recheck CMCI information after local APIC is up on CPU #0 */
1631 static void end_local_APIC_setup(void)
1635 #ifdef CONFIG_X86_32
1638 /* Disable the local apic timer */
1639 value = apic_read(APIC_LVTT);
1640 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1641 apic_write(APIC_LVTT, value);
1649 * APIC setup function for application processors. Called from smpboot.c
1651 void apic_ap_setup(void)
1654 end_local_APIC_setup();
1657 static __init void apic_read_boot_cpu_id(bool x2apic)
1660 * This can be invoked from check_x2apic() before the APIC has been
1661 * selected. But that code knows for sure that the BIOS enabled
1665 boot_cpu_physical_apicid = native_apic_msr_read(APIC_ID);
1666 boot_cpu_apic_version = GET_APIC_VERSION(native_apic_msr_read(APIC_LVR));
1668 boot_cpu_physical_apicid = read_apic_id();
1669 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1671 topology_register_boot_apic(boot_cpu_physical_apicid);
1672 x86_32_probe_bigsmp_early();
1675 #ifdef CONFIG_X86_X2APIC
1677 EXPORT_SYMBOL_GPL(x2apic_mode);
1682 /* All states below here have X2APIC enabled */
1686 static int x2apic_state;
1688 static bool x2apic_hw_locked(void)
1690 u64 x86_arch_cap_msr;
1693 x86_arch_cap_msr = x86_read_arch_cap_msr();
1694 if (x86_arch_cap_msr & ARCH_CAP_XAPIC_DISABLE) {
1695 rdmsrl(MSR_IA32_XAPIC_DISABLE_STATUS, msr);
1696 return (msr & LEGACY_XAPIC_DISABLED);
1701 static void __x2apic_disable(void)
1705 if (!boot_cpu_has(X86_FEATURE_APIC))
1708 rdmsrl(MSR_IA32_APICBASE, msr);
1709 if (!(msr & X2APIC_ENABLE))
1711 /* Disable xapic and x2apic first and then reenable xapic mode */
1712 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1713 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1714 printk_once(KERN_INFO "x2apic disabled\n");
1717 static void __x2apic_enable(void)
1721 rdmsrl(MSR_IA32_APICBASE, msr);
1722 if (msr & X2APIC_ENABLE)
1724 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1725 printk_once(KERN_INFO "x2apic enabled\n");
1728 static int __init setup_nox2apic(char *str)
1730 if (x2apic_enabled()) {
1731 u32 apicid = native_apic_msr_read(APIC_ID);
1733 if (apicid >= 255) {
1734 pr_warn("Apicid: %08x, cannot enforce nox2apic\n",
1738 if (x2apic_hw_locked()) {
1739 pr_warn("APIC locked in x2apic mode, can't disable\n");
1742 pr_warn("x2apic already enabled.\n");
1745 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1746 x2apic_state = X2APIC_DISABLED;
1750 early_param("nox2apic", setup_nox2apic);
1752 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1753 void x2apic_setup(void)
1756 * Try to make the AP's APIC state match that of the BSP, but if the
1757 * BSP is unlocked and the AP is locked then there is a state mismatch.
1758 * Warn about the mismatch in case a GP fault occurs due to a locked AP
1759 * trying to be turned off.
1761 if (x2apic_state != X2APIC_ON_LOCKED && x2apic_hw_locked())
1762 pr_warn("x2apic lock mismatch between BSP and AP.\n");
1764 * If x2apic is not in ON or LOCKED state, disable it if already enabled
1767 if (x2apic_state < X2APIC_ON) {
1774 static __init void apic_set_fixmap(bool read_apic);
1776 static __init void x2apic_disable(void)
1778 u32 x2apic_id, state = x2apic_state;
1781 x2apic_state = X2APIC_DISABLED;
1783 if (state != X2APIC_ON)
1786 x2apic_id = read_apic_id();
1787 if (x2apic_id >= 255)
1788 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1790 if (x2apic_hw_locked()) {
1791 pr_warn("Cannot disable locked x2apic, id: %08x\n", x2apic_id);
1797 * Don't reread the APIC ID as it was already done from
1798 * check_x2apic() and the APIC driver still is a x2APIC variant,
1799 * which fails to do the read after x2APIC was disabled.
1801 apic_set_fixmap(false);
1804 static __init void x2apic_enable(void)
1806 if (x2apic_state != X2APIC_OFF)
1810 x2apic_state = X2APIC_ON;
1814 static __init void try_to_enable_x2apic(int remap_mode)
1816 if (x2apic_state == X2APIC_DISABLED)
1819 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1820 u32 apic_limit = 255;
1823 * Using X2APIC without IR is not architecturally supported
1824 * on bare metal but may be supported in guests.
1826 if (!x86_init.hyper.x2apic_available()) {
1827 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1833 * If the hypervisor supports extended destination ID in
1834 * MSI, that increases the maximum APIC ID that can be
1835 * used for non-remapped IRQ domains.
1837 if (x86_init.hyper.msi_ext_dest_id()) {
1838 virt_ext_dest_id = 1;
1843 * Without IR, all CPUs can be addressed by IOAPIC/MSI only
1844 * in physical mode, and CPUs with an APIC ID that cannot
1845 * be addressed must not be brought online.
1847 x2apic_set_max_apicid(apic_limit);
1853 void __init check_x2apic(void)
1855 if (x2apic_enabled()) {
1856 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1858 if (x2apic_hw_locked())
1859 x2apic_state = X2APIC_ON_LOCKED;
1861 x2apic_state = X2APIC_ON;
1862 apic_read_boot_cpu_id(true);
1863 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1864 x2apic_state = X2APIC_DISABLED;
1867 #else /* CONFIG_X86_X2APIC */
1868 void __init check_x2apic(void)
1870 if (!apic_is_x2apic_enabled())
1873 * Checkme: Can we simply turn off x2APIC here instead of disabling the APIC?
1875 pr_err("Kernel does not support x2APIC, please recompile with CONFIG_X86_X2APIC.\n");
1876 pr_err("Disabling APIC, expect reduced performance and functionality.\n");
1878 apic_is_disabled = true;
1879 setup_clear_cpu_cap(X86_FEATURE_APIC);
1882 static inline void try_to_enable_x2apic(int remap_mode) { }
1883 static inline void __x2apic_enable(void) { }
1884 #endif /* !CONFIG_X86_X2APIC */
1886 void __init enable_IR_x2apic(void)
1888 unsigned long flags;
1891 if (ioapic_is_disabled) {
1892 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1896 ir_stat = irq_remapping_prepare();
1897 if (ir_stat < 0 && !x2apic_supported())
1900 ret = save_ioapic_entries();
1902 pr_info("Saving IO-APIC state failed: %d\n", ret);
1906 local_irq_save(flags);
1907 legacy_pic->mask_all();
1908 mask_ioapic_entries();
1910 /* If irq_remapping_prepare() succeeded, try to enable it */
1912 ir_stat = irq_remapping_enable();
1913 /* ir_stat contains the remap mode or an error code */
1914 try_to_enable_x2apic(ir_stat);
1917 restore_ioapic_entries();
1918 legacy_pic->restore_mask();
1919 local_irq_restore(flags);
1922 #ifdef CONFIG_X86_64
1924 * Detect and enable local APICs on non-SMP boards.
1925 * Original code written by Keir Fraser.
1926 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1927 * not correctly set up (usually the APIC timer won't work etc.)
1929 static bool __init detect_init_APIC(void)
1931 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1932 pr_info("No local APIC present\n");
1936 register_lapic_address(APIC_DEFAULT_PHYS_BASE);
1941 static bool __init apic_verify(unsigned long addr)
1946 * The APIC feature bit should now be enabled
1949 features = cpuid_edx(1);
1950 if (!(features & (1 << X86_FEATURE_APIC))) {
1951 pr_warn("Could not enable APIC!\n");
1954 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1956 /* The BIOS may have set up the APIC at some other address */
1957 if (boot_cpu_data.x86 >= 6) {
1958 rdmsr(MSR_IA32_APICBASE, l, h);
1959 if (l & MSR_IA32_APICBASE_ENABLE)
1960 addr = l & MSR_IA32_APICBASE_BASE;
1963 register_lapic_address(addr);
1964 pr_info("Found and enabled local APIC!\n");
1968 bool __init apic_force_enable(unsigned long addr)
1972 if (apic_is_disabled)
1976 * Some BIOSes disable the local APIC in the APIC_BASE
1977 * MSR. This can only be done in software for Intel P6 or later
1978 * and AMD K7 (Model > 1) or later.
1980 if (boot_cpu_data.x86 >= 6) {
1981 rdmsr(MSR_IA32_APICBASE, l, h);
1982 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1983 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1984 l &= ~MSR_IA32_APICBASE_BASE;
1985 l |= MSR_IA32_APICBASE_ENABLE | addr;
1986 wrmsr(MSR_IA32_APICBASE, l, h);
1987 enabled_via_apicbase = 1;
1990 return apic_verify(addr);
1994 * Detect and initialize APIC
1996 static bool __init detect_init_APIC(void)
1998 /* Disabled by kernel option? */
1999 if (apic_is_disabled)
2002 switch (boot_cpu_data.x86_vendor) {
2003 case X86_VENDOR_AMD:
2004 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
2005 (boot_cpu_data.x86 >= 15))
2008 case X86_VENDOR_HYGON:
2010 case X86_VENDOR_INTEL:
2011 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
2012 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
2019 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2021 * Over-ride BIOS and try to enable the local APIC only if
2022 * "lapic" specified.
2024 if (!force_enable_local_apic) {
2025 pr_info("Local APIC disabled by BIOS -- "
2026 "you can enable it with \"lapic\"\n");
2029 if (!apic_force_enable(APIC_DEFAULT_PHYS_BASE))
2032 if (!apic_verify(APIC_DEFAULT_PHYS_BASE))
2041 pr_info("No local APIC present or hardware disabled\n");
2047 * init_apic_mappings - initialize APIC mappings
2049 void __init init_apic_mappings(void)
2051 if (apic_validate_deadline_timer())
2052 pr_info("TSC deadline timer available\n");
2057 if (!smp_found_config) {
2058 if (!detect_init_APIC()) {
2059 pr_info("APIC: disable apic facility\n");
2065 static __init void apic_set_fixmap(bool read_apic)
2067 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
2068 apic_mmio_base = APIC_BASE;
2069 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
2070 apic_mmio_base, mp_lapic_addr);
2072 apic_read_boot_cpu_id(false);
2075 void __init register_lapic_address(unsigned long address)
2077 /* This should only happen once */
2078 WARN_ON_ONCE(mp_lapic_addr);
2079 mp_lapic_addr = address;
2082 apic_set_fixmap(true);
2086 * Local APIC interrupts
2090 * Common handling code for spurious_interrupt and spurious_vector entry
2091 * points below. No point in allowing the compiler to inline it twice.
2093 static noinline void handle_spurious_interrupt(u8 vector)
2097 trace_spurious_apic_entry(vector);
2099 inc_irq_stat(irq_spurious_count);
2102 * If this is a spurious interrupt then do not acknowledge
2104 if (vector == SPURIOUS_APIC_VECTOR) {
2106 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n",
2107 smp_processor_id());
2112 * If it is a vectored one, verify it's set in the ISR. If set,
2115 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
2116 if (v & (1 << (vector & 0x1f))) {
2117 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n",
2118 vector, smp_processor_id());
2121 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n",
2122 vector, smp_processor_id());
2125 trace_spurious_apic_exit(vector);
2129 * spurious_interrupt - Catch all for interrupts raised on unused vectors
2130 * @regs: Pointer to pt_regs on stack
2131 * @vector: The vector number
2133 * This is invoked from ASM entry code to catch all interrupts which
2134 * trigger on an entry which is routed to the common_spurious idtentry
2137 DEFINE_IDTENTRY_IRQ(spurious_interrupt)
2139 handle_spurious_interrupt(vector);
2142 DEFINE_IDTENTRY_SYSVEC(sysvec_spurious_apic_interrupt)
2144 handle_spurious_interrupt(SPURIOUS_APIC_VECTOR);
2148 * This interrupt should never happen with our APIC/SMP architecture
2150 DEFINE_IDTENTRY_SYSVEC(sysvec_error_interrupt)
2152 static const char * const error_interrupt_reason[] = {
2153 "Send CS error", /* APIC Error Bit 0 */
2154 "Receive CS error", /* APIC Error Bit 1 */
2155 "Send accept error", /* APIC Error Bit 2 */
2156 "Receive accept error", /* APIC Error Bit 3 */
2157 "Redirectable IPI", /* APIC Error Bit 4 */
2158 "Send illegal vector", /* APIC Error Bit 5 */
2159 "Received illegal vector", /* APIC Error Bit 6 */
2160 "Illegal register address", /* APIC Error Bit 7 */
2164 trace_error_apic_entry(ERROR_APIC_VECTOR);
2166 /* First tickle the hardware, only then report what went on. -- REW */
2167 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
2168 apic_write(APIC_ESR, 0);
2169 v = apic_read(APIC_ESR);
2171 atomic_inc(&irq_err_count);
2173 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2174 smp_processor_id(), v);
2179 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2184 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2186 trace_error_apic_exit(ERROR_APIC_VECTOR);
2190 * connect_bsp_APIC - attach the APIC to the interrupt system
2192 static void __init connect_bsp_APIC(void)
2194 #ifdef CONFIG_X86_32
2197 * Do not trust the local APIC being empty at bootup.
2201 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2202 * local APIC to INT and NMI lines.
2204 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2205 "enabling APIC mode.\n");
2212 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2213 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2215 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2218 void disconnect_bsp_APIC(int virt_wire_setup)
2222 #ifdef CONFIG_X86_32
2225 * Put the board back into PIC mode (has an effect only on
2226 * certain older boards). Note that APIC interrupts, including
2227 * IPIs, won't work beyond this point! The only exception are
2230 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2231 "entering PIC mode.\n");
2237 /* Go back to Virtual Wire compatibility mode */
2239 /* For the spurious interrupt use vector F, and enable it */
2240 value = apic_read(APIC_SPIV);
2241 value &= ~APIC_VECTOR_MASK;
2242 value |= APIC_SPIV_APIC_ENABLED;
2244 apic_write(APIC_SPIV, value);
2246 if (!virt_wire_setup) {
2248 * For LVT0 make it edge triggered, active high,
2249 * external and enabled
2251 value = apic_read(APIC_LVT0);
2252 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2253 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2254 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2255 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2256 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2257 apic_write(APIC_LVT0, value);
2260 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2264 * For LVT1 make it edge triggered, active high,
2267 value = apic_read(APIC_LVT1);
2268 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2269 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2270 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2271 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2272 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2273 apic_write(APIC_LVT1, value);
2276 void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
2279 memset(msg, 0, sizeof(*msg));
2281 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;
2282 msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical;
2283 msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF;
2285 msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED;
2286 msg->arch_data.vector = cfg->vector;
2288 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
2290 * Only the IOMMU itself can use the trick of putting destination
2291 * APIC ID into the high bits of the address. Anything else would
2292 * just be writing to memory if it tried that, and needs IR to
2293 * address APICs which can't be addressed in the normal 32-bit
2294 * address range at 0xFFExxxxx. That is typically just 8 bits, but
2295 * some hypervisors allow the extended destination ID field in bits
2296 * 5-11 to be used, giving support for 15 bits of APIC IDs in total.
2299 msg->arch_addr_hi.destid_8_31 = cfg->dest_apicid >> 8;
2300 else if (virt_ext_dest_id && cfg->dest_apicid < 0x8000)
2301 msg->arch_addr_lo.virt_destid_8_14 = cfg->dest_apicid >> 8;
2303 WARN_ON_ONCE(cfg->dest_apicid > 0xFF);
2306 u32 x86_msi_msg_get_destid(struct msi_msg *msg, bool extid)
2308 u32 dest = msg->arch_addr_lo.destid_0_7;
2311 dest |= msg->arch_addr_hi.destid_8_31 << 8;
2314 EXPORT_SYMBOL_GPL(x86_msi_msg_get_destid);
2316 static void __init apic_bsp_up_setup(void)
2318 reset_phys_cpu_present_map(boot_cpu_physical_apicid);
2322 * apic_bsp_setup - Setup function for local apic and io-apic
2323 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2325 static void __init apic_bsp_setup(bool upmode)
2329 apic_bsp_up_setup();
2333 end_local_APIC_setup();
2334 irq_remap_enable_fault_handling();
2336 lapic_update_legacy_vectors();
2339 #ifdef CONFIG_UP_LATE_INIT
2340 void __init up_late_init(void)
2342 if (apic_intr_mode == APIC_PIC)
2345 /* Setup local timer */
2346 x86_init.timers.setup_percpu_clockev();
2357 * 'active' is true if the local APIC was enabled by us and
2358 * not the BIOS; this signifies that we are also responsible
2359 * for disabling it before entering apm/acpi suspend
2362 /* r/w apic fields */
2364 unsigned int apic_taskpri;
2365 unsigned int apic_ldr;
2366 unsigned int apic_dfr;
2367 unsigned int apic_spiv;
2368 unsigned int apic_lvtt;
2369 unsigned int apic_lvtpc;
2370 unsigned int apic_lvt0;
2371 unsigned int apic_lvt1;
2372 unsigned int apic_lvterr;
2373 unsigned int apic_tmict;
2374 unsigned int apic_tdcr;
2375 unsigned int apic_thmr;
2376 unsigned int apic_cmci;
2379 static int lapic_suspend(void)
2381 unsigned long flags;
2384 if (!apic_pm_state.active)
2387 maxlvt = lapic_get_maxlvt();
2389 apic_pm_state.apic_id = apic_read(APIC_ID);
2390 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2391 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2392 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2393 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2394 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2396 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2397 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2398 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2399 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2400 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2401 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2402 #ifdef CONFIG_X86_THERMAL_VECTOR
2404 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2406 #ifdef CONFIG_X86_MCE_INTEL
2408 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2411 local_irq_save(flags);
2414 * Mask IOAPIC before disabling the local APIC to prevent stale IRR
2415 * entries on some implementations.
2417 mask_ioapic_entries();
2419 disable_local_APIC();
2421 irq_remapping_disable();
2423 local_irq_restore(flags);
2427 static void lapic_resume(void)
2430 unsigned long flags;
2433 if (!apic_pm_state.active)
2436 local_irq_save(flags);
2439 * IO-APIC and PIC have their own resume routines.
2440 * We just mask them here to make sure the interrupt
2441 * subsystem is completely quiet while we enable x2apic
2442 * and interrupt-remapping.
2444 mask_ioapic_entries();
2445 legacy_pic->mask_all();
2451 * Make sure the APICBASE points to the right address
2453 * FIXME! This will be wrong if we ever support suspend on
2454 * SMP! We'll need to do this as part of the CPU restore!
2456 if (boot_cpu_data.x86 >= 6) {
2457 rdmsr(MSR_IA32_APICBASE, l, h);
2458 l &= ~MSR_IA32_APICBASE_BASE;
2459 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2460 wrmsr(MSR_IA32_APICBASE, l, h);
2464 maxlvt = lapic_get_maxlvt();
2465 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2466 apic_write(APIC_ID, apic_pm_state.apic_id);
2467 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2468 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2469 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2470 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2471 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2472 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2473 #ifdef CONFIG_X86_THERMAL_VECTOR
2475 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2477 #ifdef CONFIG_X86_MCE_INTEL
2479 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2482 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2483 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2484 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2485 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2486 apic_write(APIC_ESR, 0);
2487 apic_read(APIC_ESR);
2488 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2489 apic_write(APIC_ESR, 0);
2490 apic_read(APIC_ESR);
2492 irq_remapping_reenable(x2apic_mode);
2494 local_irq_restore(flags);
2498 * This device has no shutdown method - fully functioning local APICs
2499 * are needed on every CPU up until machine_halt/restart/poweroff.
2502 static struct syscore_ops lapic_syscore_ops = {
2503 .resume = lapic_resume,
2504 .suspend = lapic_suspend,
2507 static void apic_pm_activate(void)
2509 apic_pm_state.active = 1;
2512 static int __init init_lapic_sysfs(void)
2514 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2515 if (boot_cpu_has(X86_FEATURE_APIC))
2516 register_syscore_ops(&lapic_syscore_ops);
2521 /* local apic needs to resume before other devices access its registers. */
2522 core_initcall(init_lapic_sysfs);
2524 #else /* CONFIG_PM */
2526 static void apic_pm_activate(void) { }
2528 #endif /* CONFIG_PM */
2530 #ifdef CONFIG_X86_64
2532 static int multi_checked;
2535 static int set_multi(const struct dmi_system_id *d)
2539 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2544 static const struct dmi_system_id multi_dmi_table[] = {
2546 .callback = set_multi,
2547 .ident = "IBM System Summit2",
2549 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2550 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2556 static void dmi_check_multi(void)
2561 dmi_check_system(multi_dmi_table);
2566 * apic_is_clustered_box() -- Check if we can expect good TSC
2568 * Thus far, the major user of this is IBM's Summit2 series:
2569 * Clustered boxes may have unsynced TSC problems if they are
2571 * Use DMI to check them
2573 int apic_is_clustered_box(void)
2581 * APIC command line parameters
2583 static int __init setup_disableapic(char *arg)
2585 apic_is_disabled = true;
2586 setup_clear_cpu_cap(X86_FEATURE_APIC);
2589 early_param("disableapic", setup_disableapic);
2591 /* same as disableapic, for compatibility */
2592 static int __init setup_nolapic(char *arg)
2594 return setup_disableapic(arg);
2596 early_param("nolapic", setup_nolapic);
2598 static int __init parse_lapic_timer_c2_ok(char *arg)
2600 local_apic_timer_c2_ok = 1;
2603 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2605 static int __init parse_disable_apic_timer(char *arg)
2607 disable_apic_timer = 1;
2610 early_param("noapictimer", parse_disable_apic_timer);
2612 static int __init parse_nolapic_timer(char *arg)
2614 disable_apic_timer = 1;
2617 early_param("nolapic_timer", parse_nolapic_timer);
2619 static int __init apic_set_verbosity(char *arg)
2622 if (IS_ENABLED(CONFIG_X86_32))
2625 ioapic_is_disabled = false;
2629 if (strcmp("debug", arg) == 0)
2630 apic_verbosity = APIC_DEBUG;
2631 else if (strcmp("verbose", arg) == 0)
2632 apic_verbosity = APIC_VERBOSE;
2633 #ifdef CONFIG_X86_64
2635 pr_warn("APIC Verbosity level %s not recognised"
2636 " use apic=verbose or apic=debug\n", arg);
2643 early_param("apic", apic_set_verbosity);
2645 static int __init lapic_insert_resource(void)
2647 if (!apic_mmio_base)
2650 /* Put local APIC into the resource map. */
2651 lapic_resource.start = apic_mmio_base;
2652 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2653 insert_resource(&iomem_resource, &lapic_resource);
2659 * need call insert after e820__reserve_resources()
2660 * that is using request_resource
2662 late_initcall(lapic_insert_resource);
2664 static int __init apic_set_extnmi(char *arg)
2669 if (!strncmp("all", arg, 3))
2670 apic_extnmi = APIC_EXTNMI_ALL;
2671 else if (!strncmp("none", arg, 4))
2672 apic_extnmi = APIC_EXTNMI_NONE;
2673 else if (!strncmp("bsp", arg, 3))
2674 apic_extnmi = APIC_EXTNMI_BSP;
2676 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2682 early_param("apic_extnmi", apic_set_extnmi);