2 * Firmware replacement code.
4 * Work around broken BIOSes that don't set an aperture, only set the
5 * aperture in the AGP bridge, or set too small aperture.
7 * If all fails map the aperture over some low memory. This is cheaper than
8 * doing bounce buffering. The memory is lost. This is done at early boot
9 * because only the bootmem allocator can allocate 32+MB.
11 * Copyright 2002 Andi Kleen, SuSE Labs.
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/init.h>
16 #include <linux/bootmem.h>
17 #include <linux/mmzone.h>
18 #include <linux/pci_ids.h>
19 #include <linux/pci.h>
20 #include <linux/bitops.h>
21 #include <linux/ioport.h>
22 #include <linux/suspend.h>
23 #include <linux/kmemleak.h>
26 #include <asm/iommu.h>
28 #include <asm/pci-direct.h>
31 #include <asm/x86_init.h>
33 int gart_iommu_aperture;
34 EXPORT_SYMBOL_GPL(gart_iommu_aperture);
35 int gart_iommu_aperture_disabled __initdata;
36 int gart_iommu_aperture_allowed __initdata;
38 int fallback_aper_order __initdata = 1; /* 64MB */
39 int fallback_aper_force __initdata;
41 int fix_aperture __initdata = 1;
43 struct bus_dev_range {
49 static struct bus_dev_range bus_dev_ranges[] __initdata = {
55 static struct resource gart_resource = {
57 .flags = IORESOURCE_MEM,
60 static void __init insert_aperture_resource(u32 aper_base, u32 aper_size)
62 gart_resource.start = aper_base;
63 gart_resource.end = aper_base + aper_size - 1;
64 insert_resource(&iomem_resource, &gart_resource);
67 /* This code runs before the PCI subsystem is initialized, so just
68 access the northbridge directly. */
70 static u32 __init allocate_aperture(void)
75 /* aper_size should <= 1G */
76 if (fallback_aper_order > 5)
77 fallback_aper_order = 5;
78 aper_size = (32 * 1024 * 1024) << fallback_aper_order;
81 * Aperture has to be naturally aligned. This means a 2GB aperture
82 * won't have much chance of finding a place in the lower 4GB of
83 * memory. Unfortunately we cannot move it up because that would
84 * make the IOMMU useless.
87 * using 512M as goal, in case kexec will load kernel_big
88 * that will do the on position decompress, and could overlap with
89 * that positon with gart that is used.
92 * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
93 * ==> kernel_small(gart area become e820_reserved)
94 * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
95 * ==> kerne_big (uncompressed size will be big than 64M or 128M)
96 * so don't use 512M below as gart iommu, leave the space for kernel
99 p = __alloc_bootmem_nopanic(aper_size, aper_size, 512ULL<<20);
101 * Kmemleak should not scan this block as it may not be mapped via the
102 * kernel direct mapping.
105 if (!p || __pa(p)+aper_size > 0xffffffff) {
107 "Cannot allocate aperture memory hole (%p,%uK)\n",
110 free_bootmem(__pa(p), aper_size);
113 printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n",
114 aper_size >> 10, __pa(p));
115 insert_aperture_resource((u32)__pa(p), aper_size);
116 register_nosave_region((u32)__pa(p) >> PAGE_SHIFT,
117 (u32)__pa(p+aper_size) >> PAGE_SHIFT);
123 /* Find a PCI capability */
124 static u32 __init find_cap(int bus, int slot, int func, int cap)
129 if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &
130 PCI_STATUS_CAP_LIST))
133 pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
134 for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
138 id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
143 pos = read_pci_config_byte(bus, slot, func,
144 pos+PCI_CAP_LIST_NEXT);
149 /* Read a standard AGPv3 bridge header */
150 static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
155 u32 aper_low, aper_hi;
159 printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", bus, slot, func);
160 apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);
161 if (apsizereg == 0xffffffff) {
162 printk(KERN_ERR "APSIZE in AGP bridge unreadable\n");
166 /* old_order could be the value from NB gart setting */
169 apsize = apsizereg & 0xfff;
170 /* Some BIOS use weird encodings not in the AGPv3 table. */
173 nbits = hweight16(apsize);
175 if ((int)*order < 0) /* < 32MB */
178 aper_low = read_pci_config(bus, slot, func, 0x10);
179 aper_hi = read_pci_config(bus, slot, func, 0x14);
180 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
183 * On some sick chips, APSIZE is 0. It means it wants 4G
184 * so let double check that order, and lets trust AMD NB settings:
186 printk(KERN_INFO "Aperture from AGP @ %Lx old size %u MB\n",
187 aper, 32 << old_order);
188 if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) {
189 printk(KERN_INFO "Aperture size %u MB (APSIZE %x) is not right, using settings from NB\n",
190 32 << *order, apsizereg);
194 printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
195 aper, 32 << *order, apsizereg);
197 if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20))
203 * Look for an AGP bridge. Windows only expects the aperture in the
204 * AGP bridge and some BIOS forget to initialize the Northbridge too.
205 * Work around this here.
207 * Do an PCI bus scan by hand because we're running before the PCI
210 * All K8 AGP bridges are AGPv3 compliant, so we can do this scan
211 * generically. It's probably overkill to always scan all slots because
212 * the AGP bridges should be always an own bus on the HT hierarchy,
213 * but do it here for future safety.
215 static u32 __init search_agp_bridge(u32 *order, int *valid_agp)
219 /* Poor man's PCI discovery */
220 for (bus = 0; bus < 256; bus++) {
221 for (slot = 0; slot < 32; slot++) {
222 for (func = 0; func < 8; func++) {
225 class = read_pci_config(bus, slot, func,
227 if (class == 0xffffffff)
230 switch (class >> 16) {
231 case PCI_CLASS_BRIDGE_HOST:
232 case PCI_CLASS_BRIDGE_OTHER: /* needed? */
234 cap = find_cap(bus, slot, func,
239 return read_agp(bus, slot, func, cap,
243 /* No multi-function device? */
244 type = read_pci_config_byte(bus, slot, func,
251 printk(KERN_INFO "No AGP bridge found\n");
256 static int gart_fix_e820 __initdata = 1;
258 static int __init parse_gart_mem(char *p)
263 if (!strncmp(p, "off", 3))
265 else if (!strncmp(p, "on", 2))
270 early_param("gart_fix_e820", parse_gart_mem);
272 void __init early_gart_iommu_check(void)
275 * in case it is enabled before, esp for kexec/kdump,
276 * previous kernel already enable that. memset called
277 * by allocate_aperture/__alloc_bootmem_nopanic cause restart.
278 * or second kernel have different position for GART hole. and new
279 * kernel could use hole as RAM that is still used by GART set by
281 * or BIOS forget to put that in reserved.
282 * try to update e820 to make that region as reserved.
284 u32 agp_aper_base = 0, agp_aper_order = 0;
285 int i, fix, slot, valid_agp = 0;
287 u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
288 u64 aper_base = 0, last_aper_base = 0;
289 int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0;
291 if (!early_pci_allowed())
294 /* This is mostly duplicate of iommu_hole_init */
295 agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
298 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
300 int dev_base, dev_limit;
302 bus = bus_dev_ranges[i].bus;
303 dev_base = bus_dev_ranges[i].dev_base;
304 dev_limit = bus_dev_ranges[i].dev_limit;
306 for (slot = dev_base; slot < dev_limit; slot++) {
307 if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
310 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
311 aper_enabled = ctl & AMD64_GARTEN;
312 aper_order = (ctl >> 1) & 7;
313 aper_size = (32 * 1024 * 1024) << aper_order;
314 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
318 if ((aper_order != last_aper_order) ||
319 (aper_base != last_aper_base) ||
320 (aper_enabled != last_aper_enabled)) {
326 last_aper_order = aper_order;
327 last_aper_base = aper_base;
328 last_aper_enabled = aper_enabled;
333 if (!fix && !aper_enabled)
336 if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL)
339 if (gart_fix_e820 && !fix && aper_enabled) {
340 if (e820_any_mapped(aper_base, aper_base + aper_size,
342 /* reserve it, so we can reuse it in second kernel */
343 printk(KERN_INFO "update e820 for GART\n");
344 e820_add_region(aper_base, aper_size, E820_RESERVED);
352 /* disable them all at first */
353 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
355 int dev_base, dev_limit;
357 bus = bus_dev_ranges[i].bus;
358 dev_base = bus_dev_ranges[i].dev_base;
359 dev_limit = bus_dev_ranges[i].dev_limit;
361 for (slot = dev_base; slot < dev_limit; slot++) {
362 if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
365 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
366 ctl &= ~AMD64_GARTEN;
367 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
373 static int __initdata printed_gart_size_msg;
375 void __init gart_iommu_hole_init(void)
377 u32 agp_aper_base = 0, agp_aper_order = 0;
378 u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
379 u64 aper_base, last_aper_base = 0;
380 int fix, slot, valid_agp = 0;
383 if (gart_iommu_aperture_disabled || !fix_aperture ||
384 !early_pci_allowed())
387 printk(KERN_INFO "Checking aperture...\n");
389 if (!fallback_aper_force)
390 agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
394 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
396 int dev_base, dev_limit;
398 bus = bus_dev_ranges[i].bus;
399 dev_base = bus_dev_ranges[i].dev_base;
400 dev_limit = bus_dev_ranges[i].dev_limit;
402 for (slot = dev_base; slot < dev_limit; slot++) {
403 if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
407 gart_iommu_aperture = 1;
408 x86_init.iommu.iommu_init = gart_iommu_init;
410 aper_order = (read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL) >> 1) & 7;
411 aper_size = (32 * 1024 * 1024) << aper_order;
412 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
415 printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n",
416 node, aper_base, aper_size >> 20);
419 if (!aperture_valid(aper_base, aper_size, 64<<20)) {
420 if (valid_agp && agp_aper_base &&
421 agp_aper_base == aper_base &&
422 agp_aper_order == aper_order) {
423 /* the same between two setting from NB and agp */
425 max_pfn > MAX_DMA32_PFN &&
426 !printed_gart_size_msg) {
427 printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n");
428 printk(KERN_ERR "please increase GART size in your BIOS setup\n");
429 printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n");
430 printed_gart_size_msg = 1;
438 if ((last_aper_order && aper_order != last_aper_order) ||
439 (last_aper_base && aper_base != last_aper_base)) {
443 last_aper_order = aper_order;
444 last_aper_base = aper_base;
449 if (!fix && !fallback_aper_force) {
450 if (last_aper_base) {
451 unsigned long n = (32 * 1024 * 1024) << last_aper_order;
453 insert_aperture_resource((u32)last_aper_base, n);
458 if (!fallback_aper_force) {
459 aper_alloc = agp_aper_base;
460 aper_order = agp_aper_order;
464 /* Got the aperture from the AGP bridge */
465 } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) ||
468 fallback_aper_force) {
470 "Your BIOS doesn't leave a aperture memory hole\n");
472 "Please enable the IOMMU option in the BIOS setup\n");
474 "This costs you %d MB of RAM\n",
475 32 << fallback_aper_order);
477 aper_order = fallback_aper_order;
478 aper_alloc = allocate_aperture();
481 * Could disable AGP and IOMMU here, but it's
482 * probably not worth it. But the later users
483 * cannot deal with bad apertures and turning
484 * on the aperture over memory causes very
485 * strange problems, so it's better to panic
488 panic("Not enough memory for aperture");
494 /* Fix up the north bridges */
495 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
497 int dev_base, dev_limit;
499 bus = bus_dev_ranges[i].bus;
500 dev_base = bus_dev_ranges[i].dev_base;
501 dev_limit = bus_dev_ranges[i].dev_limit;
502 for (slot = dev_base; slot < dev_limit; slot++) {
503 if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
506 /* Don't enable translation yet. That is done later.
507 Assume this BIOS didn't initialise the GART so
508 just overwrite all previous bits */
509 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, aper_order << 1);
510 write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
514 set_up_gart_resume(aper_order, aper_alloc);