arch/x86/kernel/amd_nb.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Shared support code for AMD K8 northbridges and derivatives.
   4  * Copyright 2006 Andi Kleen, SUSE Labs.
   5  */
   6
   7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   8
   9 #include <linux/types.h>
  10 #include <linux/slab.h>
  11 #include <linux/init.h>
  12 #include <linux/errno.h>
  13 #include <linux/export.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/pci_ids.h>
  16 #include <asm/amd_nb.h>
  17
  18 #define PCI_DEVICE_ID_AMD_17H_ROOT              0x1450
  19 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT         0x15d0
  20 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT         0x1480
  21 #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT         0x1630
  22 #define PCI_DEVICE_ID_AMD_17H_MA0H_ROOT         0x14b5
  23 #define PCI_DEVICE_ID_AMD_19H_M10H_ROOT         0x14a4
  24 #define PCI_DEVICE_ID_AMD_19H_M40H_ROOT         0x14b5
  25 #define PCI_DEVICE_ID_AMD_19H_M60H_ROOT         0x14d8
  26 #define PCI_DEVICE_ID_AMD_19H_M70H_ROOT         0x14e8
  27 #define PCI_DEVICE_ID_AMD_MI200_ROOT            0x14bb
  28
  29 #define PCI_DEVICE_ID_AMD_17H_DF_F4             0x1464
  30 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4        0x15ec
  31 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4        0x1494
  32 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4        0x144c
  33 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4        0x1444
  34 #define PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4        0x1728
  35 #define PCI_DEVICE_ID_AMD_19H_DF_F4             0x1654
  36 #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4        0x14b1
  37 #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4        0x167d
  38 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4        0x166e
  39 #define PCI_DEVICE_ID_AMD_19H_M60H_DF_F4        0x14e4
  40 #define PCI_DEVICE_ID_AMD_19H_M70H_DF_F4        0x14f4
  41 #define PCI_DEVICE_ID_AMD_19H_M78H_DF_F4        0x12fc
  42 #define PCI_DEVICE_ID_AMD_MI200_DF_F4           0x14d4
  43
  44 /* Protect the PCI config register pairs used for SMN. */
  45 static DEFINE_MUTEX(smn_mutex);
  46
  47 static u32 *flush_words;
  48
  49 static const struct pci_device_id amd_root_ids[] = {
  50         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
  51         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
  52         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
  53         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
  54         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_ROOT) },
  55         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_ROOT) },
  56         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) },
  57         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_ROOT) },
  58         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_ROOT) },
  59         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_ROOT) },
  60         {}
  61 };
  62
  63 #define PCI_DEVICE_ID_AMD_CNB17H_F4     0x1704
  64
  65 static const struct pci_device_id amd_nb_misc_ids[] = {
  66         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
  67         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
  68         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
  69         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
  70         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
  71         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
  72         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
  73         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
  74         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
  75         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
  76         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
  77         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
  78         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
  79         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
  80         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
  81         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
  82         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
  83         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
  84         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
  85         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
  86         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
  87         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) },
  88         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F3) },
  89         {}
  90 };
  91
  92 static const struct pci_device_id amd_nb_link_ids[] = {
  93         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
  94         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
  95         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
  96         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
  97         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
  98         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
  99         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
 100         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
 101         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F4) },
 102         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
 103         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4) },
 104         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) },
 105         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F4) },
 106         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F4) },
 107         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F4) },
 108         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
 109         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F4) },
 110         {}
 111 };
 112
 113 static const struct pci_device_id hygon_root_ids[] = {
 114         { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
 115         {}
 116 };
 117
 118 static const struct pci_device_id hygon_nb_misc_ids[] = {
 119         { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
 120         {}
 121 };
 122
 123 static const struct pci_device_id hygon_nb_link_ids[] = {
 124         { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
 125         {}
 126 };
 127
 128 const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
 129         { 0x00, 0x18, 0x20 },
 130         { 0xff, 0x00, 0x20 },
 131         { 0xfe, 0x00, 0x20 },
 132         { }
 133 };
 134
 135 static struct amd_northbridge_info amd_northbridges;
 136
 137 u16 amd_nb_num(void)
 138 {
 139         return amd_northbridges.num;
 140 }
 141 EXPORT_SYMBOL_GPL(amd_nb_num);
 142
 143 bool amd_nb_has_feature(unsigned int feature)
 144 {
 145         return ((amd_northbridges.flags & feature) == feature);
 146 }
 147 EXPORT_SYMBOL_GPL(amd_nb_has_feature);
 148
 149 struct amd_northbridge *node_to_amd_nb(int node)
 150 {
 151         return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
 152 }
 153 EXPORT_SYMBOL_GPL(node_to_amd_nb);
 154
 155 static struct pci_dev *next_northbridge(struct pci_dev *dev,
 156                                         const struct pci_device_id *ids)
 157 {
 158         do {
 159                 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
 160                 if (!dev)
 161                         break;
 162         } while (!pci_match_id(ids, dev));
 163         return dev;
 164 }
 165
 166 static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
 167 {
 168         struct pci_dev *root;
 169         int err = -ENODEV;
 170
 171         if (node >= amd_northbridges.num)
 172                 goto out;
 173
 174         root = node_to_amd_nb(node)->root;
 175         if (!root)
 176                 goto out;
 177
 178         mutex_lock(&smn_mutex);
 179
 180         err = pci_write_config_dword(root, 0x60, address);
 181         if (err) {
 182                 pr_warn("Error programming SMN address 0x%x.\n", address);
 183                 goto out_unlock;
 184         }
 185
 186         err = (write ? pci_write_config_dword(root, 0x64, *value)
 187                      : pci_read_config_dword(root, 0x64, value));
 188         if (err)
 189                 pr_warn("Error %s SMN address 0x%x.\n",
 190                         (write ? "writing to" : "reading from"), address);
 191
 192 out_unlock:
 193         mutex_unlock(&smn_mutex);
 194
 195 out:
 196         return err;
 197 }
 198
 199 int amd_smn_read(u16 node, u32 address, u32 *value)
 200 {
 201         return __amd_smn_rw(node, address, value, false);
 202 }
 203 EXPORT_SYMBOL_GPL(amd_smn_read);
 204
 205 int amd_smn_write(u16 node, u32 address, u32 value)
 206 {
 207         return __amd_smn_rw(node, address, &value, true);
 208 }
 209 EXPORT_SYMBOL_GPL(amd_smn_write);
 210
 211
 212 static int amd_cache_northbridges(void)
 213 {
 214         const struct pci_device_id *misc_ids = amd_nb_misc_ids;
 215         const struct pci_device_id *link_ids = amd_nb_link_ids;
 216         const struct pci_device_id *root_ids = amd_root_ids;
 217         struct pci_dev *root, *misc, *link;
 218         struct amd_northbridge *nb;
 219         u16 roots_per_misc = 0;
 220         u16 misc_count = 0;
 221         u16 root_count = 0;
 222         u16 i, j;
 223
 224         if (amd_northbridges.num)
 225                 return 0;
 226
 227         if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
 228                 root_ids = hygon_root_ids;
 229                 misc_ids = hygon_nb_misc_ids;
 230                 link_ids = hygon_nb_link_ids;
 231         }
 232
 233         misc = NULL;
 234         while ((misc = next_northbridge(misc, misc_ids)))
 235                 misc_count++;
 236
 237         if (!misc_count)
 238                 return -ENODEV;
 239
 240         root = NULL;
 241         while ((root = next_northbridge(root, root_ids)))
 242                 root_count++;
 243
 244         if (root_count) {
 245                 roots_per_misc = root_count / misc_count;
 246
 247                 /*
 248                  * There should be _exactly_ N roots for each DF/SMN
 249                  * interface.
 250                  */
 251                 if (!roots_per_misc || (root_count % roots_per_misc)) {
 252                         pr_info("Unsupported AMD DF/PCI configuration found\n");
 253                         return -ENODEV;
 254                 }
 255         }
 256
 257         nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
 258         if (!nb)
 259                 return -ENOMEM;
 260
 261         amd_northbridges.nb = nb;
 262         amd_northbridges.num = misc_count;
 263
 264         link = misc = root = NULL;
 265         for (i = 0; i < amd_northbridges.num; i++) {
 266                 node_to_amd_nb(i)->root = root =
 267                         next_northbridge(root, root_ids);
 268                 node_to_amd_nb(i)->misc = misc =
 269                         next_northbridge(misc, misc_ids);
 270                 node_to_amd_nb(i)->link = link =
 271                         next_northbridge(link, link_ids);
 272
 273                 /*
 274                  * If there are more PCI root devices than data fabric/
 275                  * system management network interfaces, then the (N)
 276                  * PCI roots per DF/SMN interface are functionally the
 277                  * same (for DF/SMN access) and N-1 are redundant.  N-1
 278                  * PCI roots should be skipped per DF/SMN interface so
 279                  * the following DF/SMN interfaces get mapped to
 280                  * correct PCI roots.
 281                  */
 282                 for (j = 1; j < roots_per_misc; j++)
 283                         root = next_northbridge(root, root_ids);
 284         }
 285
 286         if (amd_gart_present())
 287                 amd_northbridges.flags |= AMD_NB_GART;
 288
 289         /*
 290          * Check for L3 cache presence.
 291          */
 292         if (!cpuid_edx(0x80000006))
 293                 return 0;
 294
 295         /*
 296          * Some CPU families support L3 Cache Index Disable. There are some
 297          * limitations because of E382 and E388 on family 0x10.
 298          */
 299         if (boot_cpu_data.x86 == 0x10 &&
 300             boot_cpu_data.x86_model >= 0x8 &&
 301             (boot_cpu_data.x86_model > 0x9 ||
 302              boot_cpu_data.x86_stepping >= 0x1))
 303                 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
 304
 305         if (boot_cpu_data.x86 == 0x15)
 306                 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
 307
 308         /* L3 cache partitioning is supported on family 0x15 */
 309         if (boot_cpu_data.x86 == 0x15)
 310                 amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
 311
 312         return 0;
 313 }
 314
 315 /*
 316  * Ignores subdevice/subvendor but as far as I can figure out
 317  * they're useless anyways
 318  */
 319 bool __init early_is_amd_nb(u32 device)
 320 {
 321         const struct pci_device_id *misc_ids = amd_nb_misc_ids;
 322         const struct pci_device_id *id;
 323         u32 vendor = device & 0xffff;
 324
 325         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
 326             boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
 327                 return false;
 328
 329         if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
 330                 misc_ids = hygon_nb_misc_ids;
 331
 332         device >>= 16;
 333         for (id = misc_ids; id->vendor; id++)
 334                 if (vendor == id->vendor && device == id->device)
 335                         return true;
 336         return false;
 337 }
 338
 339 struct resource *amd_get_mmconfig_range(struct resource *res)
 340 {
 341         u32 address;
 342         u64 base, msr;
 343         unsigned int segn_busn_bits;
 344
 345         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
 346             boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
 347                 return NULL;
 348
 349         /* assume all cpus from fam10h have mmconfig */
 350         if (boot_cpu_data.x86 < 0x10)
 351                 return NULL;
 352
 353         address = MSR_FAM10H_MMIO_CONF_BASE;
 354         rdmsrl(address, msr);
 355
 356         /* mmconfig is not enabled */
 357         if (!(msr & FAM10H_MMIO_CONF_ENABLE))
 358                 return NULL;
 359
 360         base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
 361
 362         segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
 363                          FAM10H_MMIO_CONF_BUSRANGE_MASK;
 364
 365         res->flags = IORESOURCE_MEM;
 366         res->start = base;
 367         res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
 368         return res;
 369 }
 370
 371 int amd_get_subcaches(int cpu)
 372 {
 373         struct pci_dev *link = node_to_amd_nb(topology_die_id(cpu))->link;
 374         unsigned int mask;
 375
 376         if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
 377                 return 0;
 378
 379         pci_read_config_dword(link, 0x1d4, &mask);
 380
 381         return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
 382 }
 383
 384 int amd_set_subcaches(int cpu, unsigned long mask)
 385 {
 386         static unsigned int reset, ban;
 387         struct amd_northbridge *nb = node_to_amd_nb(topology_die_id(cpu));
 388         unsigned int reg;
 389         int cuid;
 390
 391         if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
 392                 return -EINVAL;
 393
 394         /* if necessary, collect reset state of L3 partitioning and BAN mode */
 395         if (reset == 0) {
 396                 pci_read_config_dword(nb->link, 0x1d4, &reset);
 397                 pci_read_config_dword(nb->misc, 0x1b8, &ban);
 398                 ban &= 0x180000;
 399         }
 400
 401         /* deactivate BAN mode if any subcaches are to be disabled */
 402         if (mask != 0xf) {
 403                 pci_read_config_dword(nb->misc, 0x1b8, &reg);
 404                 pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
 405         }
 406
 407         cuid = cpu_data(cpu).cpu_core_id;
 408         mask <<= 4 * cuid;
 409         mask |= (0xf ^ (1 << cuid)) << 26;
 410
 411         pci_write_config_dword(nb->link, 0x1d4, mask);
 412
 413         /* reset BAN mode if L3 partitioning returned to reset state */
 414         pci_read_config_dword(nb->link, 0x1d4, &reg);
 415         if (reg == reset) {
 416                 pci_read_config_dword(nb->misc, 0x1b8, &reg);
 417                 reg &= ~0x180000;
 418                 pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
 419         }
 420
 421         return 0;
 422 }
 423
 424 static void amd_cache_gart(void)
 425 {
 426         u16 i;
 427
 428         if (!amd_nb_has_feature(AMD_NB_GART))
 429                 return;
 430
 431         flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
 432         if (!flush_words) {
 433                 amd_northbridges.flags &= ~AMD_NB_GART;
 434                 pr_notice("Cannot initialize GART flush words, GART support disabled\n");
 435                 return;
 436         }
 437
 438         for (i = 0; i != amd_northbridges.num; i++)
 439                 pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
 440 }
 441
 442 void amd_flush_garts(void)
 443 {
 444         int flushed, i;
 445         unsigned long flags;
 446         static DEFINE_SPINLOCK(gart_lock);
 447
 448         if (!amd_nb_has_feature(AMD_NB_GART))
 449                 return;
 450
 451         /*
 452          * Avoid races between AGP and IOMMU. In theory it's not needed
 453          * but I'm not sure if the hardware won't lose flush requests
 454          * when another is pending. This whole thing is so expensive anyways
 455          * that it doesn't matter to serialize more. -AK
 456          */
 457         spin_lock_irqsave(&gart_lock, flags);
 458         flushed = 0;
 459         for (i = 0; i < amd_northbridges.num; i++) {
 460                 pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
 461                                        flush_words[i] | 1);
 462                 flushed++;
 463         }
 464         for (i = 0; i < amd_northbridges.num; i++) {
 465                 u32 w;
 466                 /* Make sure the hardware actually executed the flush*/
 467                 for (;;) {
 468                         pci_read_config_dword(node_to_amd_nb(i)->misc,
 469                                               0x9c, &w);
 470                         if (!(w & 1))
 471                                 break;
 472                         cpu_relax();
 473                 }
 474         }
 475         spin_unlock_irqrestore(&gart_lock, flags);
 476         if (!flushed)
 477                 pr_notice("nothing to flush?\n");
 478 }
 479 EXPORT_SYMBOL_GPL(amd_flush_garts);
 480
 481 static void __fix_erratum_688(void *info)
 482 {
 483 #define MSR_AMD64_IC_CFG 0xC0011021
 484
 485         msr_set_bit(MSR_AMD64_IC_CFG, 3);
 486         msr_set_bit(MSR_AMD64_IC_CFG, 14);
 487 }
 488
 489 /* Apply erratum 688 fix so machines without a BIOS fix work. */
 490 static __init void fix_erratum_688(void)
 491 {
 492         struct pci_dev *F4;
 493         u32 val;
 494
 495         if (boot_cpu_data.x86 != 0x14)
 496                 return;
 497
 498         if (!amd_northbridges.num)
 499                 return;
 500
 501         F4 = node_to_amd_nb(0)->link;
 502         if (!F4)
 503                 return;
 504
 505         if (pci_read_config_dword(F4, 0x164, &val))
 506                 return;
 507
 508         if (val & BIT(2))
 509                 return;
 510
 511         on_each_cpu(__fix_erratum_688, NULL, 0);
 512
 513         pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
 514 }
 515
 516 static __init int init_amd_nbs(void)
 517 {
 518         amd_cache_northbridges();
 519         amd_cache_gart();
 520
 521         fix_erratum_688();
 522
 523         return 0;
 524 }
 525
 526 /* This has to go after the PCI subsystem */
 527 fs_initcall(init_amd_nbs);