arch/x86/kernel/amd_nb.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Shared support code for AMD K8 northbridges and derivatives.
   4  * Copyright 2006 Andi Kleen, SUSE Labs.
   5  */
   6
   7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   8
   9 #include <linux/types.h>
  10 #include <linux/slab.h>
  11 #include <linux/init.h>
  12 #include <linux/errno.h>
  13 #include <linux/export.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/pci_ids.h>
  16 #include <asm/amd_nb.h>
  17
  18 #define PCI_DEVICE_ID_AMD_17H_ROOT              0x1450
  19 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT         0x15d0
  20 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT         0x1480
  21 #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT         0x1630
  22 #define PCI_DEVICE_ID_AMD_17H_MA0H_ROOT         0x14b5
  23 #define PCI_DEVICE_ID_AMD_19H_M10H_ROOT         0x14a4
  24 #define PCI_DEVICE_ID_AMD_19H_M40H_ROOT         0x14b5
  25 #define PCI_DEVICE_ID_AMD_19H_M60H_ROOT         0x14d8
  26 #define PCI_DEVICE_ID_AMD_19H_M70H_ROOT         0x14e8
  27 #define PCI_DEVICE_ID_AMD_1AH_M00H_ROOT         0x153a
  28 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT         0x1507
  29 #define PCI_DEVICE_ID_AMD_MI200_ROOT            0x14bb
  30 #define PCI_DEVICE_ID_AMD_MI300_ROOT            0x14f8
  31
  32 #define PCI_DEVICE_ID_AMD_17H_DF_F4             0x1464
  33 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4        0x15ec
  34 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4        0x1494
  35 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4        0x144c
  36 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4        0x1444
  37 #define PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4        0x1728
  38 #define PCI_DEVICE_ID_AMD_19H_DF_F4             0x1654
  39 #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4        0x14b1
  40 #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4        0x167d
  41 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4        0x166e
  42 #define PCI_DEVICE_ID_AMD_19H_M60H_DF_F4        0x14e4
  43 #define PCI_DEVICE_ID_AMD_19H_M70H_DF_F4        0x14f4
  44 #define PCI_DEVICE_ID_AMD_19H_M78H_DF_F4        0x12fc
  45 #define PCI_DEVICE_ID_AMD_1AH_M00H_DF_F4        0x12c4
  46 #define PCI_DEVICE_ID_AMD_MI200_DF_F4           0x14d4
  47 #define PCI_DEVICE_ID_AMD_MI300_DF_F4           0x152c
  48
  49 /* Protect the PCI config register pairs used for SMN. */
  50 static DEFINE_MUTEX(smn_mutex);
  51
  52 static u32 *flush_words;
  53
  54 static const struct pci_device_id amd_root_ids[] = {
  55         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
  56         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
  57         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
  58         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
  59         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_ROOT) },
  60         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_ROOT) },
  61         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) },
  62         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_ROOT) },
  63         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_ROOT) },
  64         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_ROOT) },
  65         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
  66         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_ROOT) },
  67         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI300_ROOT) },
  68         {}
  69 };
  70
  71 #define PCI_DEVICE_ID_AMD_CNB17H_F4     0x1704
  72
  73 static const struct pci_device_id amd_nb_misc_ids[] = {
  74         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
  75         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
  76         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
  77         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
  78         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
  79         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
  80         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
  81         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
  82         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
  83         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
  84         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
  85         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
  86         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
  87         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
  88         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
  89         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
  90         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
  91         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
  92         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
  93         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
  94         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
  95         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) },
  96         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) },
  97         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) },
  98         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M70H_DF_F3) },
  99         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F3) },
 100         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI300_DF_F3) },
 101         {}
 102 };
 103
 104 static const struct pci_device_id amd_nb_link_ids[] = {
 105         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
 106         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
 107         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
 108         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
 109         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
 110         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
 111         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
 112         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
 113         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F4) },
 114         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
 115         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4) },
 116         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) },
 117         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F4) },
 118         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F4) },
 119         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F4) },
 120         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F4) },
 121         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F4) },
 122         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F4) },
 123         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
 124         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F4) },
 125         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F4) },
 126         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI300_DF_F4) },
 127         {}
 128 };
 129
 130 static const struct pci_device_id hygon_root_ids[] = {
 131         { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
 132         {}
 133 };
 134
 135 static const struct pci_device_id hygon_nb_misc_ids[] = {
 136         { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
 137         {}
 138 };
 139
 140 static const struct pci_device_id hygon_nb_link_ids[] = {
 141         { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
 142         {}
 143 };
 144
 145 const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
 146         { 0x00, 0x18, 0x20 },
 147         { 0xff, 0x00, 0x20 },
 148         { 0xfe, 0x00, 0x20 },
 149         { }
 150 };
 151
 152 static struct amd_northbridge_info amd_northbridges;
 153
 154 u16 amd_nb_num(void)
 155 {
 156         return amd_northbridges.num;
 157 }
 158 EXPORT_SYMBOL_GPL(amd_nb_num);
 159
 160 bool amd_nb_has_feature(unsigned int feature)
 161 {
 162         return ((amd_northbridges.flags & feature) == feature);
 163 }
 164 EXPORT_SYMBOL_GPL(amd_nb_has_feature);
 165
 166 struct amd_northbridge *node_to_amd_nb(int node)
 167 {
 168         return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
 169 }
 170 EXPORT_SYMBOL_GPL(node_to_amd_nb);
 171
 172 static struct pci_dev *next_northbridge(struct pci_dev *dev,
 173                                         const struct pci_device_id *ids)
 174 {
 175         do {
 176                 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
 177                 if (!dev)
 178                         break;
 179         } while (!pci_match_id(ids, dev));
 180         return dev;
 181 }
 182
 183 static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
 184 {
 185         struct pci_dev *root;
 186         int err = -ENODEV;
 187
 188         if (node >= amd_northbridges.num)
 189                 goto out;
 190
 191         root = node_to_amd_nb(node)->root;
 192         if (!root)
 193                 goto out;
 194
 195         mutex_lock(&smn_mutex);
 196
 197         err = pci_write_config_dword(root, 0x60, address);
 198         if (err) {
 199                 pr_warn("Error programming SMN address 0x%x.\n", address);
 200                 goto out_unlock;
 201         }
 202
 203         err = (write ? pci_write_config_dword(root, 0x64, *value)
 204                      : pci_read_config_dword(root, 0x64, value));
 205         if (err)
 206                 pr_warn("Error %s SMN address 0x%x.\n",
 207                         (write ? "writing to" : "reading from"), address);
 208
 209 out_unlock:
 210         mutex_unlock(&smn_mutex);
 211
 212 out:
 213         return err;
 214 }
 215
 216 int amd_smn_read(u16 node, u32 address, u32 *value)
 217 {
 218         int err = __amd_smn_rw(node, address, value, false);
 219
 220         if (PCI_POSSIBLE_ERROR(*value)) {
 221                 err = -ENODEV;
 222                 *value = 0;
 223         }
 224
 225         return err;
 226 }
 227 EXPORT_SYMBOL_GPL(amd_smn_read);
 228
 229 int amd_smn_write(u16 node, u32 address, u32 value)
 230 {
 231         return __amd_smn_rw(node, address, &value, true);
 232 }
 233 EXPORT_SYMBOL_GPL(amd_smn_write);
 234
 235
 236 static int amd_cache_northbridges(void)
 237 {
 238         const struct pci_device_id *misc_ids = amd_nb_misc_ids;
 239         const struct pci_device_id *link_ids = amd_nb_link_ids;
 240         const struct pci_device_id *root_ids = amd_root_ids;
 241         struct pci_dev *root, *misc, *link;
 242         struct amd_northbridge *nb;
 243         u16 roots_per_misc = 0;
 244         u16 misc_count = 0;
 245         u16 root_count = 0;
 246         u16 i, j;
 247
 248         if (amd_northbridges.num)
 249                 return 0;
 250
 251         if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
 252                 root_ids = hygon_root_ids;
 253                 misc_ids = hygon_nb_misc_ids;
 254                 link_ids = hygon_nb_link_ids;
 255         }
 256
 257         misc = NULL;
 258         while ((misc = next_northbridge(misc, misc_ids)))
 259                 misc_count++;
 260
 261         if (!misc_count)
 262                 return -ENODEV;
 263
 264         root = NULL;
 265         while ((root = next_northbridge(root, root_ids)))
 266                 root_count++;
 267
 268         if (root_count) {
 269                 roots_per_misc = root_count / misc_count;
 270
 271                 /*
 272                  * There should be _exactly_ N roots for each DF/SMN
 273                  * interface.
 274                  */
 275                 if (!roots_per_misc || (root_count % roots_per_misc)) {
 276                         pr_info("Unsupported AMD DF/PCI configuration found\n");
 277                         return -ENODEV;
 278                 }
 279         }
 280
 281         nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
 282         if (!nb)
 283                 return -ENOMEM;
 284
 285         amd_northbridges.nb = nb;
 286         amd_northbridges.num = misc_count;
 287
 288         link = misc = root = NULL;
 289         for (i = 0; i < amd_northbridges.num; i++) {
 290                 node_to_amd_nb(i)->root = root =
 291                         next_northbridge(root, root_ids);
 292                 node_to_amd_nb(i)->misc = misc =
 293                         next_northbridge(misc, misc_ids);
 294                 node_to_amd_nb(i)->link = link =
 295                         next_northbridge(link, link_ids);
 296
 297                 /*
 298                  * If there are more PCI root devices than data fabric/
 299                  * system management network interfaces, then the (N)
 300                  * PCI roots per DF/SMN interface are functionally the
 301                  * same (for DF/SMN access) and N-1 are redundant.  N-1
 302                  * PCI roots should be skipped per DF/SMN interface so
 303                  * the following DF/SMN interfaces get mapped to
 304                  * correct PCI roots.
 305                  */
 306                 for (j = 1; j < roots_per_misc; j++)
 307                         root = next_northbridge(root, root_ids);
 308         }
 309
 310         if (amd_gart_present())
 311                 amd_northbridges.flags |= AMD_NB_GART;
 312
 313         /*
 314          * Check for L3 cache presence.
 315          */
 316         if (!cpuid_edx(0x80000006))
 317                 return 0;
 318
 319         /*
 320          * Some CPU families support L3 Cache Index Disable. There are some
 321          * limitations because of E382 and E388 on family 0x10.
 322          */
 323         if (boot_cpu_data.x86 == 0x10 &&
 324             boot_cpu_data.x86_model >= 0x8 &&
 325             (boot_cpu_data.x86_model > 0x9 ||
 326              boot_cpu_data.x86_stepping >= 0x1))
 327                 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
 328
 329         if (boot_cpu_data.x86 == 0x15)
 330                 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
 331
 332         /* L3 cache partitioning is supported on family 0x15 */
 333         if (boot_cpu_data.x86 == 0x15)
 334                 amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
 335
 336         return 0;
 337 }
 338
 339 /*
 340  * Ignores subdevice/subvendor but as far as I can figure out
 341  * they're useless anyways
 342  */
 343 bool __init early_is_amd_nb(u32 device)
 344 {
 345         const struct pci_device_id *misc_ids = amd_nb_misc_ids;
 346         const struct pci_device_id *id;
 347         u32 vendor = device & 0xffff;
 348
 349         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
 350             boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
 351                 return false;
 352
 353         if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
 354                 misc_ids = hygon_nb_misc_ids;
 355
 356         device >>= 16;
 357         for (id = misc_ids; id->vendor; id++)
 358                 if (vendor == id->vendor && device == id->device)
 359                         return true;
 360         return false;
 361 }
 362
 363 struct resource *amd_get_mmconfig_range(struct resource *res)
 364 {
 365         u32 address;
 366         u64 base, msr;
 367         unsigned int segn_busn_bits;
 368
 369         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
 370             boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
 371                 return NULL;
 372
 373         /* assume all cpus from fam10h have mmconfig */
 374         if (boot_cpu_data.x86 < 0x10)
 375                 return NULL;
 376
 377         address = MSR_FAM10H_MMIO_CONF_BASE;
 378         rdmsrl(address, msr);
 379
 380         /* mmconfig is not enabled */
 381         if (!(msr & FAM10H_MMIO_CONF_ENABLE))
 382                 return NULL;
 383
 384         base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
 385
 386         segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
 387                          FAM10H_MMIO_CONF_BUSRANGE_MASK;
 388
 389         res->flags = IORESOURCE_MEM;
 390         res->start = base;
 391         res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
 392         return res;
 393 }
 394
 395 int amd_get_subcaches(int cpu)
 396 {
 397         struct pci_dev *link = node_to_amd_nb(topology_amd_node_id(cpu))->link;
 398         unsigned int mask;
 399
 400         if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
 401                 return 0;
 402
 403         pci_read_config_dword(link, 0x1d4, &mask);
 404
 405         return (mask >> (4 * cpu_data(cpu).topo.core_id)) & 0xf;
 406 }
 407
 408 int amd_set_subcaches(int cpu, unsigned long mask)
 409 {
 410         static unsigned int reset, ban;
 411         struct amd_northbridge *nb = node_to_amd_nb(topology_amd_node_id(cpu));
 412         unsigned int reg;
 413         int cuid;
 414
 415         if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
 416                 return -EINVAL;
 417
 418         /* if necessary, collect reset state of L3 partitioning and BAN mode */
 419         if (reset == 0) {
 420                 pci_read_config_dword(nb->link, 0x1d4, &reset);
 421                 pci_read_config_dword(nb->misc, 0x1b8, &ban);
 422                 ban &= 0x180000;
 423         }
 424
 425         /* deactivate BAN mode if any subcaches are to be disabled */
 426         if (mask != 0xf) {
 427                 pci_read_config_dword(nb->misc, 0x1b8, &reg);
 428                 pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
 429         }
 430
 431         cuid = cpu_data(cpu).topo.core_id;
 432         mask <<= 4 * cuid;
 433         mask |= (0xf ^ (1 << cuid)) << 26;
 434
 435         pci_write_config_dword(nb->link, 0x1d4, mask);
 436
 437         /* reset BAN mode if L3 partitioning returned to reset state */
 438         pci_read_config_dword(nb->link, 0x1d4, &reg);
 439         if (reg == reset) {
 440                 pci_read_config_dword(nb->misc, 0x1b8, &reg);
 441                 reg &= ~0x180000;
 442                 pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
 443         }
 444
 445         return 0;
 446 }
 447
 448 static void amd_cache_gart(void)
 449 {
 450         u16 i;
 451
 452         if (!amd_nb_has_feature(AMD_NB_GART))
 453                 return;
 454
 455         flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
 456         if (!flush_words) {
 457                 amd_northbridges.flags &= ~AMD_NB_GART;
 458                 pr_notice("Cannot initialize GART flush words, GART support disabled\n");
 459                 return;
 460         }
 461
 462         for (i = 0; i != amd_northbridges.num; i++)
 463                 pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
 464 }
 465
 466 void amd_flush_garts(void)
 467 {
 468         int flushed, i;
 469         unsigned long flags;
 470         static DEFINE_SPINLOCK(gart_lock);
 471
 472         if (!amd_nb_has_feature(AMD_NB_GART))
 473                 return;
 474
 475         /*
 476          * Avoid races between AGP and IOMMU. In theory it's not needed
 477          * but I'm not sure if the hardware won't lose flush requests
 478          * when another is pending. This whole thing is so expensive anyways
 479          * that it doesn't matter to serialize more. -AK
 480          */
 481         spin_lock_irqsave(&gart_lock, flags);
 482         flushed = 0;
 483         for (i = 0; i < amd_northbridges.num; i++) {
 484                 pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
 485                                        flush_words[i] | 1);
 486                 flushed++;
 487         }
 488         for (i = 0; i < amd_northbridges.num; i++) {
 489                 u32 w;
 490                 /* Make sure the hardware actually executed the flush*/
 491                 for (;;) {
 492                         pci_read_config_dword(node_to_amd_nb(i)->misc,
 493                                               0x9c, &w);
 494                         if (!(w & 1))
 495                                 break;
 496                         cpu_relax();
 497                 }
 498         }
 499         spin_unlock_irqrestore(&gart_lock, flags);
 500         if (!flushed)
 501                 pr_notice("nothing to flush?\n");
 502 }
 503 EXPORT_SYMBOL_GPL(amd_flush_garts);
 504
 505 static void __fix_erratum_688(void *info)
 506 {
 507 #define MSR_AMD64_IC_CFG 0xC0011021
 508
 509         msr_set_bit(MSR_AMD64_IC_CFG, 3);
 510         msr_set_bit(MSR_AMD64_IC_CFG, 14);
 511 }
 512
 513 /* Apply erratum 688 fix so machines without a BIOS fix work. */
 514 static __init void fix_erratum_688(void)
 515 {
 516         struct pci_dev *F4;
 517         u32 val;
 518
 519         if (boot_cpu_data.x86 != 0x14)
 520                 return;
 521
 522         if (!amd_northbridges.num)
 523                 return;
 524
 525         F4 = node_to_amd_nb(0)->link;
 526         if (!F4)
 527                 return;
 528
 529         if (pci_read_config_dword(F4, 0x164, &val))
 530                 return;
 531
 532         if (val & BIT(2))
 533                 return;
 534
 535         on_each_cpu(__fix_erratum_688, NULL, 0);
 536
 537         pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
 538 }
 539
 540 static __init int init_amd_nbs(void)
 541 {
 542         amd_cache_northbridges();
 543         amd_cache_gart();
 544
 545         fix_erratum_688();
 546
 547         return 0;
 548 }
 549
 550 /* This has to go after the PCI subsystem */
 551 fs_initcall(init_amd_nbs);