2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36 #define EXIT_LOOP_COUNT 10000000
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44 #ifdef CONFIG_IOMMU_API
45 static struct iommu_ops amd_iommu_ops;
49 * general struct to manage commands send to an IOMMU
55 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
56 struct unity_map_entry *e);
57 static struct dma_ops_domain *find_protection_domain(u16 devid);
58 static u64* alloc_pte(struct protection_domain *dom,
59 unsigned long address, u64
60 **pte_page, gfp_t gfp);
61 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
62 unsigned long start_page,
65 #ifndef BUS_NOTIFY_UNBOUND_DRIVER
66 #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005
69 #ifdef CONFIG_AMD_IOMMU_STATS
72 * Initialization code for statistics collection
75 DECLARE_STATS_COUNTER(compl_wait);
76 DECLARE_STATS_COUNTER(cnt_map_single);
77 DECLARE_STATS_COUNTER(cnt_unmap_single);
78 DECLARE_STATS_COUNTER(cnt_map_sg);
79 DECLARE_STATS_COUNTER(cnt_unmap_sg);
80 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
81 DECLARE_STATS_COUNTER(cnt_free_coherent);
82 DECLARE_STATS_COUNTER(cross_page);
83 DECLARE_STATS_COUNTER(domain_flush_single);
84 DECLARE_STATS_COUNTER(domain_flush_all);
85 DECLARE_STATS_COUNTER(alloced_io_mem);
86 DECLARE_STATS_COUNTER(total_map_requests);
88 static struct dentry *stats_dir;
89 static struct dentry *de_isolate;
90 static struct dentry *de_fflush;
92 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
94 if (stats_dir == NULL)
97 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
101 static void amd_iommu_stats_init(void)
103 stats_dir = debugfs_create_dir("amd-iommu", NULL);
104 if (stats_dir == NULL)
107 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
108 (u32 *)&amd_iommu_isolate);
110 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
111 (u32 *)&amd_iommu_unmap_flush);
113 amd_iommu_stats_add(&compl_wait);
114 amd_iommu_stats_add(&cnt_map_single);
115 amd_iommu_stats_add(&cnt_unmap_single);
116 amd_iommu_stats_add(&cnt_map_sg);
117 amd_iommu_stats_add(&cnt_unmap_sg);
118 amd_iommu_stats_add(&cnt_alloc_coherent);
119 amd_iommu_stats_add(&cnt_free_coherent);
120 amd_iommu_stats_add(&cross_page);
121 amd_iommu_stats_add(&domain_flush_single);
122 amd_iommu_stats_add(&domain_flush_all);
123 amd_iommu_stats_add(&alloced_io_mem);
124 amd_iommu_stats_add(&total_map_requests);
129 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
130 static int iommu_has_npcache(struct amd_iommu *iommu)
132 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
135 /****************************************************************************
137 * Interrupt handling functions
139 ****************************************************************************/
141 static void dump_dte_entry(u16 devid)
145 for (i = 0; i < 8; ++i)
146 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
147 amd_iommu_dev_table[devid].data[i]);
150 static void dump_command(unsigned long phys_addr)
152 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
155 for (i = 0; i < 4; ++i)
156 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
159 static void iommu_print_event(void *__evt)
162 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
163 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
164 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
165 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
166 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
168 printk(KERN_ERR "AMD IOMMU: Event logged [");
171 case EVENT_TYPE_ILL_DEV:
172 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
173 "address=0x%016llx flags=0x%04x]\n",
174 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
176 dump_dte_entry(devid);
178 case EVENT_TYPE_IO_FAULT:
179 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
180 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
181 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
182 domid, address, flags);
184 case EVENT_TYPE_DEV_TAB_ERR:
185 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
186 "address=0x%016llx flags=0x%04x]\n",
187 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
190 case EVENT_TYPE_PAGE_TAB_ERR:
191 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
192 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
193 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
194 domid, address, flags);
196 case EVENT_TYPE_ILL_CMD:
197 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
198 dump_command(address);
200 case EVENT_TYPE_CMD_HARD_ERR:
201 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
202 "flags=0x%04x]\n", address, flags);
204 case EVENT_TYPE_IOTLB_INV_TO:
205 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
206 "address=0x%016llx]\n",
207 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
210 case EVENT_TYPE_INV_DEV_REQ:
211 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
212 "address=0x%016llx flags=0x%04x]\n",
213 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
217 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
221 static void iommu_poll_events(struct amd_iommu *iommu)
226 spin_lock_irqsave(&iommu->lock, flags);
228 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
229 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
231 while (head != tail) {
232 iommu_print_event(iommu->evt_buf + head);
233 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
236 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
238 spin_unlock_irqrestore(&iommu->lock, flags);
241 irqreturn_t amd_iommu_int_handler(int irq, void *data)
243 struct amd_iommu *iommu;
245 for_each_iommu(iommu)
246 iommu_poll_events(iommu);
251 /****************************************************************************
253 * IOMMU command queuing functions
255 ****************************************************************************/
258 * Writes the command to the IOMMUs command buffer and informs the
259 * hardware about the new command. Must be called with iommu->lock held.
261 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
266 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
267 target = iommu->cmd_buf + tail;
268 memcpy_toio(target, cmd, sizeof(*cmd));
269 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
270 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
273 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
279 * General queuing function for commands. Takes iommu->lock and calls
280 * __iommu_queue_command().
282 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
287 spin_lock_irqsave(&iommu->lock, flags);
288 ret = __iommu_queue_command(iommu, cmd);
290 iommu->need_sync = true;
291 spin_unlock_irqrestore(&iommu->lock, flags);
297 * This function waits until an IOMMU has completed a completion
300 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
306 INC_STATS_COUNTER(compl_wait);
308 while (!ready && (i < EXIT_LOOP_COUNT)) {
310 /* wait for the bit to become one */
311 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
312 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
315 /* set bit back to zero */
316 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
317 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
319 if (unlikely(i == EXIT_LOOP_COUNT))
320 panic("AMD IOMMU: Completion wait loop failed\n");
324 * This function queues a completion wait command into the command
327 static int __iommu_completion_wait(struct amd_iommu *iommu)
329 struct iommu_cmd cmd;
331 memset(&cmd, 0, sizeof(cmd));
332 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
333 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
335 return __iommu_queue_command(iommu, &cmd);
339 * This function is called whenever we need to ensure that the IOMMU has
340 * completed execution of all commands we sent. It sends a
341 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
342 * us about that by writing a value to a physical address we pass with
345 static int iommu_completion_wait(struct amd_iommu *iommu)
350 spin_lock_irqsave(&iommu->lock, flags);
352 if (!iommu->need_sync)
355 ret = __iommu_completion_wait(iommu);
357 iommu->need_sync = false;
362 __iommu_wait_for_completion(iommu);
365 spin_unlock_irqrestore(&iommu->lock, flags);
371 * Command send function for invalidating a device table entry
373 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
375 struct iommu_cmd cmd;
378 BUG_ON(iommu == NULL);
380 memset(&cmd, 0, sizeof(cmd));
381 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
384 ret = iommu_queue_command(iommu, &cmd);
389 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
390 u16 domid, int pde, int s)
392 memset(cmd, 0, sizeof(*cmd));
393 address &= PAGE_MASK;
394 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
395 cmd->data[1] |= domid;
396 cmd->data[2] = lower_32_bits(address);
397 cmd->data[3] = upper_32_bits(address);
398 if (s) /* size bit - we flush more than one 4kb page */
399 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
400 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
401 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
405 * Generic command send function for invalidaing TLB entries
407 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
408 u64 address, u16 domid, int pde, int s)
410 struct iommu_cmd cmd;
413 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
415 ret = iommu_queue_command(iommu, &cmd);
421 * TLB invalidation function which is called from the mapping functions.
422 * It invalidates a single PTE if the range to flush is within a single
423 * page. Otherwise it flushes the whole TLB of the IOMMU.
425 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
426 u64 address, size_t size)
429 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
431 address &= PAGE_MASK;
435 * If we have to flush more than one page, flush all
436 * TLB entries for this domain
438 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
442 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
447 /* Flush the whole IO/TLB for a given protection domain */
448 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
450 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
452 INC_STATS_COUNTER(domain_flush_single);
454 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
457 /* Flush the whole IO/TLB for a given protection domain - including PDE */
458 static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid)
460 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
462 INC_STATS_COUNTER(domain_flush_single);
464 iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1);
468 * This function is used to flush the IO/TLB for a given protection domain
469 * on every IOMMU in the system
471 static void iommu_flush_domain(u16 domid)
474 struct amd_iommu *iommu;
475 struct iommu_cmd cmd;
477 INC_STATS_COUNTER(domain_flush_all);
479 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
482 for_each_iommu(iommu) {
483 spin_lock_irqsave(&iommu->lock, flags);
484 __iommu_queue_command(iommu, &cmd);
485 __iommu_completion_wait(iommu);
486 __iommu_wait_for_completion(iommu);
487 spin_unlock_irqrestore(&iommu->lock, flags);
491 void amd_iommu_flush_all_domains(void)
495 for (i = 1; i < MAX_DOMAIN_ID; ++i) {
496 if (!test_bit(i, amd_iommu_pd_alloc_bitmap))
498 iommu_flush_domain(i);
502 void amd_iommu_flush_all_devices(void)
504 struct amd_iommu *iommu;
507 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
508 if (amd_iommu_pd_table[i] == NULL)
511 iommu = amd_iommu_rlookup_table[i];
515 iommu_queue_inv_dev_entry(iommu, i);
516 iommu_completion_wait(iommu);
520 /****************************************************************************
522 * The functions below are used the create the page table mappings for
523 * unity mapped regions.
525 ****************************************************************************/
528 * Generic mapping functions. It maps a physical address into a DMA
529 * address space. It allocates the page table pages if necessary.
530 * In the future it can be extended to a generic mapping function
531 * supporting all features of AMD IOMMU page tables like level skipping
532 * and full 64 bit address spaces.
534 static int iommu_map_page(struct protection_domain *dom,
535 unsigned long bus_addr,
536 unsigned long phys_addr,
541 bus_addr = PAGE_ALIGN(bus_addr);
542 phys_addr = PAGE_ALIGN(phys_addr);
544 /* only support 512GB address spaces for now */
545 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
548 pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL);
550 if (IOMMU_PTE_PRESENT(*pte))
553 __pte = phys_addr | IOMMU_PTE_P;
554 if (prot & IOMMU_PROT_IR)
555 __pte |= IOMMU_PTE_IR;
556 if (prot & IOMMU_PROT_IW)
557 __pte |= IOMMU_PTE_IW;
564 static void iommu_unmap_page(struct protection_domain *dom,
565 unsigned long bus_addr)
569 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
571 if (!IOMMU_PTE_PRESENT(*pte))
574 pte = IOMMU_PTE_PAGE(*pte);
575 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
577 if (!IOMMU_PTE_PRESENT(*pte))
580 pte = IOMMU_PTE_PAGE(*pte);
581 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
587 * This function checks if a specific unity mapping entry is needed for
588 * this specific IOMMU.
590 static int iommu_for_unity_map(struct amd_iommu *iommu,
591 struct unity_map_entry *entry)
595 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
596 bdf = amd_iommu_alias_table[i];
597 if (amd_iommu_rlookup_table[bdf] == iommu)
605 * Init the unity mappings for a specific IOMMU in the system
607 * Basically iterates over all unity mapping entries and applies them to
608 * the default domain DMA of that IOMMU if necessary.
610 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
612 struct unity_map_entry *entry;
615 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
616 if (!iommu_for_unity_map(iommu, entry))
618 ret = dma_ops_unity_map(iommu->default_dom, entry);
627 * This function actually applies the mapping to the page table of the
630 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
631 struct unity_map_entry *e)
636 for (addr = e->address_start; addr < e->address_end;
638 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
642 * if unity mapping is in aperture range mark the page
643 * as allocated in the aperture
645 if (addr < dma_dom->aperture_size)
646 __set_bit(addr >> PAGE_SHIFT,
647 dma_dom->aperture[0]->bitmap);
654 * Inits the unity mappings required for a specific device
656 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
659 struct unity_map_entry *e;
662 list_for_each_entry(e, &amd_iommu_unity_map, list) {
663 if (!(devid >= e->devid_start && devid <= e->devid_end))
665 ret = dma_ops_unity_map(dma_dom, e);
673 /****************************************************************************
675 * The next functions belong to the address allocator for the dma_ops
676 * interface functions. They work like the allocators in the other IOMMU
677 * drivers. Its basically a bitmap which marks the allocated pages in
678 * the aperture. Maybe it could be enhanced in the future to a more
679 * efficient allocator.
681 ****************************************************************************/
684 * The address allocator core functions.
686 * called with domain->lock held
690 * This function checks if there is a PTE for a given dma address. If
691 * there is one, it returns the pointer to it.
693 static u64* fetch_pte(struct protection_domain *domain,
694 unsigned long address)
698 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(address)];
700 if (!IOMMU_PTE_PRESENT(*pte))
703 pte = IOMMU_PTE_PAGE(*pte);
704 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
706 if (!IOMMU_PTE_PRESENT(*pte))
709 pte = IOMMU_PTE_PAGE(*pte);
710 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
716 * This function is used to add a new aperture range to an existing
717 * aperture in case of dma_ops domain allocation or address allocation
720 static int alloc_new_range(struct amd_iommu *iommu,
721 struct dma_ops_domain *dma_dom,
722 bool populate, gfp_t gfp)
724 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
727 #ifdef CONFIG_IOMMU_STRESS
731 if (index >= APERTURE_MAX_RANGES)
734 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
735 if (!dma_dom->aperture[index])
738 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
739 if (!dma_dom->aperture[index]->bitmap)
742 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
745 unsigned long address = dma_dom->aperture_size;
746 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
749 for (i = 0; i < num_ptes; ++i) {
750 pte = alloc_pte(&dma_dom->domain, address,
755 dma_dom->aperture[index]->pte_pages[i] = pte_page;
757 address += APERTURE_RANGE_SIZE / 64;
761 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
763 /* Intialize the exclusion range if necessary */
764 if (iommu->exclusion_start &&
765 iommu->exclusion_start >= dma_dom->aperture[index]->offset &&
766 iommu->exclusion_start < dma_dom->aperture_size) {
767 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
768 int pages = iommu_num_pages(iommu->exclusion_start,
769 iommu->exclusion_length,
771 dma_ops_reserve_addresses(dma_dom, startpage, pages);
775 * Check for areas already mapped as present in the new aperture
776 * range and mark those pages as reserved in the allocator. Such
777 * mappings may already exist as a result of requested unity
778 * mappings for devices.
780 for (i = dma_dom->aperture[index]->offset;
781 i < dma_dom->aperture_size;
783 u64 *pte = fetch_pte(&dma_dom->domain, i);
784 if (!pte || !IOMMU_PTE_PRESENT(*pte))
787 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
793 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
795 kfree(dma_dom->aperture[index]);
796 dma_dom->aperture[index] = NULL;
801 static unsigned long dma_ops_area_alloc(struct device *dev,
802 struct dma_ops_domain *dom,
804 unsigned long align_mask,
808 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
809 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
810 int i = start >> APERTURE_RANGE_SHIFT;
811 unsigned long boundary_size;
812 unsigned long address = -1;
815 next_bit >>= PAGE_SHIFT;
817 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
818 PAGE_SIZE) >> PAGE_SHIFT;
820 for (;i < max_index; ++i) {
821 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
823 if (dom->aperture[i]->offset >= dma_mask)
826 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
827 dma_mask >> PAGE_SHIFT);
829 address = iommu_area_alloc(dom->aperture[i]->bitmap,
830 limit, next_bit, pages, 0,
831 boundary_size, align_mask);
833 address = dom->aperture[i]->offset +
834 (address << PAGE_SHIFT);
835 dom->next_address = address + (pages << PAGE_SHIFT);
845 static unsigned long dma_ops_alloc_addresses(struct device *dev,
846 struct dma_ops_domain *dom,
848 unsigned long align_mask,
851 unsigned long address;
853 #ifdef CONFIG_IOMMU_STRESS
854 dom->next_address = 0;
855 dom->need_flush = true;
858 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
859 dma_mask, dom->next_address);
862 dom->next_address = 0;
863 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
865 dom->need_flush = true;
868 if (unlikely(address == -1))
869 address = bad_dma_address;
871 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
877 * The address free function.
879 * called with domain->lock held
881 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
882 unsigned long address,
885 unsigned i = address >> APERTURE_RANGE_SHIFT;
886 struct aperture_range *range = dom->aperture[i];
888 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
890 #ifdef CONFIG_IOMMU_STRESS
895 if (address >= dom->next_address)
896 dom->need_flush = true;
898 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
900 iommu_area_free(range->bitmap, address, pages);
904 /****************************************************************************
906 * The next functions belong to the domain allocation. A domain is
907 * allocated for every IOMMU as the default domain. If device isolation
908 * is enabled, every device get its own domain. The most important thing
909 * about domains is the page table mapping the DMA address space they
912 ****************************************************************************/
914 static u16 domain_id_alloc(void)
919 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
920 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
922 if (id > 0 && id < MAX_DOMAIN_ID)
923 __set_bit(id, amd_iommu_pd_alloc_bitmap);
926 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
931 static void domain_id_free(int id)
935 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
936 if (id > 0 && id < MAX_DOMAIN_ID)
937 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
938 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
942 * Used to reserve address ranges in the aperture (e.g. for exclusion
945 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
946 unsigned long start_page,
949 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
951 if (start_page + pages > last_page)
952 pages = last_page - start_page;
954 for (i = start_page; i < start_page + pages; ++i) {
955 int index = i / APERTURE_RANGE_PAGES;
956 int page = i % APERTURE_RANGE_PAGES;
957 __set_bit(page, dom->aperture[index]->bitmap);
961 static void free_pagetable(struct protection_domain *domain)
966 p1 = domain->pt_root;
971 for (i = 0; i < 512; ++i) {
972 if (!IOMMU_PTE_PRESENT(p1[i]))
975 p2 = IOMMU_PTE_PAGE(p1[i]);
976 for (j = 0; j < 512; ++j) {
977 if (!IOMMU_PTE_PRESENT(p2[j]))
979 p3 = IOMMU_PTE_PAGE(p2[j]);
980 free_page((unsigned long)p3);
983 free_page((unsigned long)p2);
986 free_page((unsigned long)p1);
988 domain->pt_root = NULL;
992 * Free a domain, only used if something went wrong in the
993 * allocation path and we need to free an already allocated page table
995 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1002 free_pagetable(&dom->domain);
1004 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1005 if (!dom->aperture[i])
1007 free_page((unsigned long)dom->aperture[i]->bitmap);
1008 kfree(dom->aperture[i]);
1015 * Allocates a new protection domain usable for the dma_ops functions.
1016 * It also intializes the page table and the address allocator data
1017 * structures required for the dma_ops interface
1019 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu)
1021 struct dma_ops_domain *dma_dom;
1023 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1027 spin_lock_init(&dma_dom->domain.lock);
1029 dma_dom->domain.id = domain_id_alloc();
1030 if (dma_dom->domain.id == 0)
1032 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1033 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1034 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1035 dma_dom->domain.priv = dma_dom;
1036 if (!dma_dom->domain.pt_root)
1039 dma_dom->need_flush = false;
1040 dma_dom->target_dev = 0xffff;
1042 if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL))
1046 * mark the first page as allocated so we never return 0 as
1047 * a valid dma-address. So we can use 0 as error value
1049 dma_dom->aperture[0]->bitmap[0] = 1;
1050 dma_dom->next_address = 0;
1056 dma_ops_domain_free(dma_dom);
1062 * little helper function to check whether a given protection domain is a
1065 static bool dma_ops_domain(struct protection_domain *domain)
1067 return domain->flags & PD_DMA_OPS_MASK;
1071 * Find out the protection domain structure for a given PCI device. This
1072 * will give us the pointer to the page table root for example.
1074 static struct protection_domain *domain_for_device(u16 devid)
1076 struct protection_domain *dom;
1077 unsigned long flags;
1079 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1080 dom = amd_iommu_pd_table[devid];
1081 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1087 * If a device is not yet associated with a domain, this function does
1088 * assigns it visible for the hardware
1090 static void attach_device(struct amd_iommu *iommu,
1091 struct protection_domain *domain,
1094 unsigned long flags;
1095 u64 pte_root = virt_to_phys(domain->pt_root);
1097 domain->dev_cnt += 1;
1099 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1100 << DEV_ENTRY_MODE_SHIFT;
1101 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1103 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1104 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1105 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1106 amd_iommu_dev_table[devid].data[2] = domain->id;
1108 amd_iommu_pd_table[devid] = domain;
1109 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1112 * We might boot into a crash-kernel here. The crashed kernel
1113 * left the caches in the IOMMU dirty. So we have to flush
1114 * here to evict all dirty stuff.
1116 iommu_queue_inv_dev_entry(iommu, devid);
1117 iommu_flush_tlb_pde(iommu, domain->id);
1121 * Removes a device from a protection domain (unlocked)
1123 static void __detach_device(struct protection_domain *domain, u16 devid)
1127 spin_lock(&domain->lock);
1129 /* remove domain from the lookup table */
1130 amd_iommu_pd_table[devid] = NULL;
1132 /* remove entry from the device table seen by the hardware */
1133 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1134 amd_iommu_dev_table[devid].data[1] = 0;
1135 amd_iommu_dev_table[devid].data[2] = 0;
1137 /* decrease reference counter */
1138 domain->dev_cnt -= 1;
1141 spin_unlock(&domain->lock);
1145 * Removes a device from a protection domain (with devtable_lock held)
1147 static void detach_device(struct protection_domain *domain, u16 devid)
1149 unsigned long flags;
1151 /* lock device table */
1152 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1153 __detach_device(domain, devid);
1154 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1157 static int device_change_notifier(struct notifier_block *nb,
1158 unsigned long action, void *data)
1160 struct device *dev = data;
1161 struct pci_dev *pdev = to_pci_dev(dev);
1162 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
1163 struct protection_domain *domain;
1164 struct dma_ops_domain *dma_domain;
1165 struct amd_iommu *iommu;
1166 unsigned long flags;
1168 if (devid > amd_iommu_last_bdf)
1171 devid = amd_iommu_alias_table[devid];
1173 iommu = amd_iommu_rlookup_table[devid];
1177 domain = domain_for_device(devid);
1179 if (domain && !dma_ops_domain(domain))
1180 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1181 "to a non-dma-ops domain\n", dev_name(dev));
1184 case BUS_NOTIFY_UNBOUND_DRIVER:
1187 detach_device(domain, devid);
1189 case BUS_NOTIFY_ADD_DEVICE:
1190 /* allocate a protection domain if a device is added */
1191 dma_domain = find_protection_domain(devid);
1194 dma_domain = dma_ops_domain_alloc(iommu);
1197 dma_domain->target_dev = devid;
1199 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1200 list_add_tail(&dma_domain->list, &iommu_pd_list);
1201 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1208 iommu_queue_inv_dev_entry(iommu, devid);
1209 iommu_completion_wait(iommu);
1215 static struct notifier_block device_nb = {
1216 .notifier_call = device_change_notifier,
1219 /*****************************************************************************
1221 * The next functions belong to the dma_ops mapping/unmapping code.
1223 *****************************************************************************/
1226 * This function checks if the driver got a valid device from the caller to
1227 * avoid dereferencing invalid pointers.
1229 static bool check_device(struct device *dev)
1231 if (!dev || !dev->dma_mask)
1238 * In this function the list of preallocated protection domains is traversed to
1239 * find the domain for a specific device
1241 static struct dma_ops_domain *find_protection_domain(u16 devid)
1243 struct dma_ops_domain *entry, *ret = NULL;
1244 unsigned long flags;
1246 if (list_empty(&iommu_pd_list))
1249 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1251 list_for_each_entry(entry, &iommu_pd_list, list) {
1252 if (entry->target_dev == devid) {
1258 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1264 * In the dma_ops path we only have the struct device. This function
1265 * finds the corresponding IOMMU, the protection domain and the
1266 * requestor id for a given device.
1267 * If the device is not yet associated with a domain this is also done
1270 static int get_device_resources(struct device *dev,
1271 struct amd_iommu **iommu,
1272 struct protection_domain **domain,
1275 struct dma_ops_domain *dma_dom;
1276 struct pci_dev *pcidev;
1283 if (dev->bus != &pci_bus_type)
1286 pcidev = to_pci_dev(dev);
1287 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1289 /* device not translated by any IOMMU in the system? */
1290 if (_bdf > amd_iommu_last_bdf)
1293 *bdf = amd_iommu_alias_table[_bdf];
1295 *iommu = amd_iommu_rlookup_table[*bdf];
1298 *domain = domain_for_device(*bdf);
1299 if (*domain == NULL) {
1300 dma_dom = find_protection_domain(*bdf);
1302 dma_dom = (*iommu)->default_dom;
1303 *domain = &dma_dom->domain;
1304 attach_device(*iommu, *domain, *bdf);
1305 DUMP_printk("Using protection domain %d for device %s\n",
1306 (*domain)->id, dev_name(dev));
1309 if (domain_for_device(_bdf) == NULL)
1310 attach_device(*iommu, *domain, _bdf);
1316 * If the pte_page is not yet allocated this function is called
1318 static u64* alloc_pte(struct protection_domain *dom,
1319 unsigned long address, u64 **pte_page, gfp_t gfp)
1323 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)];
1325 if (!IOMMU_PTE_PRESENT(*pte)) {
1326 page = (u64 *)get_zeroed_page(gfp);
1329 *pte = IOMMU_L2_PDE(virt_to_phys(page));
1332 pte = IOMMU_PTE_PAGE(*pte);
1333 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
1335 if (!IOMMU_PTE_PRESENT(*pte)) {
1336 page = (u64 *)get_zeroed_page(gfp);
1339 *pte = IOMMU_L1_PDE(virt_to_phys(page));
1342 pte = IOMMU_PTE_PAGE(*pte);
1347 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
1353 * This function fetches the PTE for a given address in the aperture
1355 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1356 unsigned long address)
1358 struct aperture_range *aperture;
1359 u64 *pte, *pte_page;
1361 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1365 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1367 pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC);
1368 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1370 pte += IOMMU_PTE_L0_INDEX(address);
1376 * This is the generic map function. It maps one 4kb page at paddr to
1377 * the given address in the DMA address space for the domain.
1379 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1380 struct dma_ops_domain *dom,
1381 unsigned long address,
1387 WARN_ON(address > dom->aperture_size);
1391 pte = dma_ops_get_pte(dom, address);
1393 return bad_dma_address;
1395 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1397 if (direction == DMA_TO_DEVICE)
1398 __pte |= IOMMU_PTE_IR;
1399 else if (direction == DMA_FROM_DEVICE)
1400 __pte |= IOMMU_PTE_IW;
1401 else if (direction == DMA_BIDIRECTIONAL)
1402 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1408 return (dma_addr_t)address;
1412 * The generic unmapping function for on page in the DMA address space.
1414 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1415 struct dma_ops_domain *dom,
1416 unsigned long address)
1418 struct aperture_range *aperture;
1421 if (address >= dom->aperture_size)
1424 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1428 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1432 pte += IOMMU_PTE_L0_INDEX(address);
1440 * This function contains common code for mapping of a physically
1441 * contiguous memory region into DMA address space. It is used by all
1442 * mapping functions provided with this IOMMU driver.
1443 * Must be called with the domain lock held.
1445 static dma_addr_t __map_single(struct device *dev,
1446 struct amd_iommu *iommu,
1447 struct dma_ops_domain *dma_dom,
1454 dma_addr_t offset = paddr & ~PAGE_MASK;
1455 dma_addr_t address, start, ret;
1457 unsigned long align_mask = 0;
1460 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1463 INC_STATS_COUNTER(total_map_requests);
1466 INC_STATS_COUNTER(cross_page);
1469 align_mask = (1UL << get_order(size)) - 1;
1472 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1474 if (unlikely(address == bad_dma_address)) {
1476 * setting next_address here will let the address
1477 * allocator only scan the new allocated range in the
1478 * first run. This is a small optimization.
1480 dma_dom->next_address = dma_dom->aperture_size;
1482 if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC))
1486 * aperture was sucessfully enlarged by 128 MB, try
1493 for (i = 0; i < pages; ++i) {
1494 ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1495 if (ret == bad_dma_address)
1503 ADD_STATS_COUNTER(alloced_io_mem, size);
1505 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1506 iommu_flush_tlb(iommu, dma_dom->domain.id);
1507 dma_dom->need_flush = false;
1508 } else if (unlikely(iommu_has_npcache(iommu)))
1509 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1516 for (--i; i >= 0; --i) {
1518 dma_ops_domain_unmap(iommu, dma_dom, start);
1521 dma_ops_free_addresses(dma_dom, address, pages);
1523 return bad_dma_address;
1527 * Does the reverse of the __map_single function. Must be called with
1528 * the domain lock held too
1530 static void __unmap_single(struct amd_iommu *iommu,
1531 struct dma_ops_domain *dma_dom,
1532 dma_addr_t dma_addr,
1536 dma_addr_t i, start;
1539 if ((dma_addr == bad_dma_address) ||
1540 (dma_addr + size > dma_dom->aperture_size))
1543 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1544 dma_addr &= PAGE_MASK;
1547 for (i = 0; i < pages; ++i) {
1548 dma_ops_domain_unmap(iommu, dma_dom, start);
1552 SUB_STATS_COUNTER(alloced_io_mem, size);
1554 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1556 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1557 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1558 dma_dom->need_flush = false;
1563 * The exported map_single function for dma_ops.
1565 static dma_addr_t map_page(struct device *dev, struct page *page,
1566 unsigned long offset, size_t size,
1567 enum dma_data_direction dir,
1568 struct dma_attrs *attrs)
1570 unsigned long flags;
1571 struct amd_iommu *iommu;
1572 struct protection_domain *domain;
1576 phys_addr_t paddr = page_to_phys(page) + offset;
1578 INC_STATS_COUNTER(cnt_map_single);
1580 if (!check_device(dev))
1581 return bad_dma_address;
1583 dma_mask = *dev->dma_mask;
1585 get_device_resources(dev, &iommu, &domain, &devid);
1587 if (iommu == NULL || domain == NULL)
1588 /* device not handled by any AMD IOMMU */
1589 return (dma_addr_t)paddr;
1591 if (!dma_ops_domain(domain))
1592 return bad_dma_address;
1594 spin_lock_irqsave(&domain->lock, flags);
1595 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1597 if (addr == bad_dma_address)
1600 iommu_completion_wait(iommu);
1603 spin_unlock_irqrestore(&domain->lock, flags);
1609 * The exported unmap_single function for dma_ops.
1611 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1612 enum dma_data_direction dir, struct dma_attrs *attrs)
1614 unsigned long flags;
1615 struct amd_iommu *iommu;
1616 struct protection_domain *domain;
1619 INC_STATS_COUNTER(cnt_unmap_single);
1621 if (!check_device(dev) ||
1622 !get_device_resources(dev, &iommu, &domain, &devid))
1623 /* device not handled by any AMD IOMMU */
1626 if (!dma_ops_domain(domain))
1629 spin_lock_irqsave(&domain->lock, flags);
1631 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1633 iommu_completion_wait(iommu);
1635 spin_unlock_irqrestore(&domain->lock, flags);
1639 * This is a special map_sg function which is used if we should map a
1640 * device which is not handled by an AMD IOMMU in the system.
1642 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1643 int nelems, int dir)
1645 struct scatterlist *s;
1648 for_each_sg(sglist, s, nelems, i) {
1649 s->dma_address = (dma_addr_t)sg_phys(s);
1650 s->dma_length = s->length;
1657 * The exported map_sg function for dma_ops (handles scatter-gather
1660 static int map_sg(struct device *dev, struct scatterlist *sglist,
1661 int nelems, enum dma_data_direction dir,
1662 struct dma_attrs *attrs)
1664 unsigned long flags;
1665 struct amd_iommu *iommu;
1666 struct protection_domain *domain;
1669 struct scatterlist *s;
1671 int mapped_elems = 0;
1674 INC_STATS_COUNTER(cnt_map_sg);
1676 if (!check_device(dev))
1679 dma_mask = *dev->dma_mask;
1681 get_device_resources(dev, &iommu, &domain, &devid);
1683 if (!iommu || !domain)
1684 return map_sg_no_iommu(dev, sglist, nelems, dir);
1686 if (!dma_ops_domain(domain))
1689 spin_lock_irqsave(&domain->lock, flags);
1691 for_each_sg(sglist, s, nelems, i) {
1694 s->dma_address = __map_single(dev, iommu, domain->priv,
1695 paddr, s->length, dir, false,
1698 if (s->dma_address) {
1699 s->dma_length = s->length;
1705 iommu_completion_wait(iommu);
1708 spin_unlock_irqrestore(&domain->lock, flags);
1710 return mapped_elems;
1712 for_each_sg(sglist, s, mapped_elems, i) {
1714 __unmap_single(iommu, domain->priv, s->dma_address,
1715 s->dma_length, dir);
1716 s->dma_address = s->dma_length = 0;
1725 * The exported map_sg function for dma_ops (handles scatter-gather
1728 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1729 int nelems, enum dma_data_direction dir,
1730 struct dma_attrs *attrs)
1732 unsigned long flags;
1733 struct amd_iommu *iommu;
1734 struct protection_domain *domain;
1735 struct scatterlist *s;
1739 INC_STATS_COUNTER(cnt_unmap_sg);
1741 if (!check_device(dev) ||
1742 !get_device_resources(dev, &iommu, &domain, &devid))
1745 if (!dma_ops_domain(domain))
1748 spin_lock_irqsave(&domain->lock, flags);
1750 for_each_sg(sglist, s, nelems, i) {
1751 __unmap_single(iommu, domain->priv, s->dma_address,
1752 s->dma_length, dir);
1753 s->dma_address = s->dma_length = 0;
1756 iommu_completion_wait(iommu);
1758 spin_unlock_irqrestore(&domain->lock, flags);
1762 * The exported alloc_coherent function for dma_ops.
1764 static void *alloc_coherent(struct device *dev, size_t size,
1765 dma_addr_t *dma_addr, gfp_t flag)
1767 unsigned long flags;
1769 struct amd_iommu *iommu;
1770 struct protection_domain *domain;
1773 u64 dma_mask = dev->coherent_dma_mask;
1775 INC_STATS_COUNTER(cnt_alloc_coherent);
1777 if (!check_device(dev))
1780 if (!get_device_resources(dev, &iommu, &domain, &devid))
1781 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1784 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1788 paddr = virt_to_phys(virt_addr);
1790 if (!iommu || !domain) {
1791 *dma_addr = (dma_addr_t)paddr;
1795 if (!dma_ops_domain(domain))
1799 dma_mask = *dev->dma_mask;
1801 spin_lock_irqsave(&domain->lock, flags);
1803 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1804 size, DMA_BIDIRECTIONAL, true, dma_mask);
1806 if (*dma_addr == bad_dma_address) {
1807 spin_unlock_irqrestore(&domain->lock, flags);
1811 iommu_completion_wait(iommu);
1813 spin_unlock_irqrestore(&domain->lock, flags);
1819 free_pages((unsigned long)virt_addr, get_order(size));
1825 * The exported free_coherent function for dma_ops.
1827 static void free_coherent(struct device *dev, size_t size,
1828 void *virt_addr, dma_addr_t dma_addr)
1830 unsigned long flags;
1831 struct amd_iommu *iommu;
1832 struct protection_domain *domain;
1835 INC_STATS_COUNTER(cnt_free_coherent);
1837 if (!check_device(dev))
1840 get_device_resources(dev, &iommu, &domain, &devid);
1842 if (!iommu || !domain)
1845 if (!dma_ops_domain(domain))
1848 spin_lock_irqsave(&domain->lock, flags);
1850 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1852 iommu_completion_wait(iommu);
1854 spin_unlock_irqrestore(&domain->lock, flags);
1857 free_pages((unsigned long)virt_addr, get_order(size));
1861 * This function is called by the DMA layer to find out if we can handle a
1862 * particular device. It is part of the dma_ops.
1864 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1867 struct pci_dev *pcidev;
1869 /* No device or no PCI device */
1870 if (!dev || dev->bus != &pci_bus_type)
1873 pcidev = to_pci_dev(dev);
1875 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1877 /* Out of our scope? */
1878 if (bdf > amd_iommu_last_bdf)
1885 * The function for pre-allocating protection domains.
1887 * If the driver core informs the DMA layer if a driver grabs a device
1888 * we don't need to preallocate the protection domains anymore.
1889 * For now we have to.
1891 static void prealloc_protection_domains(void)
1893 struct pci_dev *dev = NULL;
1894 struct dma_ops_domain *dma_dom;
1895 struct amd_iommu *iommu;
1898 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1899 devid = calc_devid(dev->bus->number, dev->devfn);
1900 if (devid > amd_iommu_last_bdf)
1902 devid = amd_iommu_alias_table[devid];
1903 if (domain_for_device(devid))
1905 iommu = amd_iommu_rlookup_table[devid];
1908 dma_dom = dma_ops_domain_alloc(iommu);
1911 init_unity_mappings_for_device(dma_dom, devid);
1912 dma_dom->target_dev = devid;
1914 list_add_tail(&dma_dom->list, &iommu_pd_list);
1918 static struct dma_map_ops amd_iommu_dma_ops = {
1919 .alloc_coherent = alloc_coherent,
1920 .free_coherent = free_coherent,
1921 .map_page = map_page,
1922 .unmap_page = unmap_page,
1924 .unmap_sg = unmap_sg,
1925 .dma_supported = amd_iommu_dma_supported,
1929 * The function which clues the AMD IOMMU driver into dma_ops.
1931 int __init amd_iommu_init_dma_ops(void)
1933 struct amd_iommu *iommu;
1937 * first allocate a default protection domain for every IOMMU we
1938 * found in the system. Devices not assigned to any other
1939 * protection domain will be assigned to the default one.
1941 for_each_iommu(iommu) {
1942 iommu->default_dom = dma_ops_domain_alloc(iommu);
1943 if (iommu->default_dom == NULL)
1945 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1946 ret = iommu_init_unity_mappings(iommu);
1952 * If device isolation is enabled, pre-allocate the protection
1953 * domains for each device.
1955 if (amd_iommu_isolate)
1956 prealloc_protection_domains();
1960 bad_dma_address = 0;
1961 #ifdef CONFIG_GART_IOMMU
1962 gart_iommu_aperture_disabled = 1;
1963 gart_iommu_aperture = 0;
1966 /* Make the driver finally visible to the drivers */
1967 dma_ops = &amd_iommu_dma_ops;
1969 register_iommu(&amd_iommu_ops);
1971 bus_register_notifier(&pci_bus_type, &device_nb);
1973 amd_iommu_stats_init();
1979 for_each_iommu(iommu) {
1980 if (iommu->default_dom)
1981 dma_ops_domain_free(iommu->default_dom);
1987 /*****************************************************************************
1989 * The following functions belong to the exported interface of AMD IOMMU
1991 * This interface allows access to lower level functions of the IOMMU
1992 * like protection domain handling and assignement of devices to domains
1993 * which is not possible with the dma_ops interface.
1995 *****************************************************************************/
1997 static void cleanup_domain(struct protection_domain *domain)
1999 unsigned long flags;
2002 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2004 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2005 if (amd_iommu_pd_table[devid] == domain)
2006 __detach_device(domain, devid);
2008 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2011 static int amd_iommu_domain_init(struct iommu_domain *dom)
2013 struct protection_domain *domain;
2015 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2019 spin_lock_init(&domain->lock);
2020 domain->mode = PAGE_MODE_3_LEVEL;
2021 domain->id = domain_id_alloc();
2024 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2025 if (!domain->pt_root)
2038 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2040 struct protection_domain *domain = dom->priv;
2045 if (domain->dev_cnt > 0)
2046 cleanup_domain(domain);
2048 BUG_ON(domain->dev_cnt != 0);
2050 free_pagetable(domain);
2052 domain_id_free(domain->id);
2059 static void amd_iommu_detach_device(struct iommu_domain *dom,
2062 struct protection_domain *domain = dom->priv;
2063 struct amd_iommu *iommu;
2064 struct pci_dev *pdev;
2067 if (dev->bus != &pci_bus_type)
2070 pdev = to_pci_dev(dev);
2072 devid = calc_devid(pdev->bus->number, pdev->devfn);
2075 detach_device(domain, devid);
2077 iommu = amd_iommu_rlookup_table[devid];
2081 iommu_queue_inv_dev_entry(iommu, devid);
2082 iommu_completion_wait(iommu);
2085 static int amd_iommu_attach_device(struct iommu_domain *dom,
2088 struct protection_domain *domain = dom->priv;
2089 struct protection_domain *old_domain;
2090 struct amd_iommu *iommu;
2091 struct pci_dev *pdev;
2094 if (dev->bus != &pci_bus_type)
2097 pdev = to_pci_dev(dev);
2099 devid = calc_devid(pdev->bus->number, pdev->devfn);
2101 if (devid >= amd_iommu_last_bdf ||
2102 devid != amd_iommu_alias_table[devid])
2105 iommu = amd_iommu_rlookup_table[devid];
2109 old_domain = domain_for_device(devid);
2111 detach_device(old_domain, devid);
2113 attach_device(iommu, domain, devid);
2115 iommu_completion_wait(iommu);
2120 static int amd_iommu_map_range(struct iommu_domain *dom,
2121 unsigned long iova, phys_addr_t paddr,
2122 size_t size, int iommu_prot)
2124 struct protection_domain *domain = dom->priv;
2125 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2129 if (iommu_prot & IOMMU_READ)
2130 prot |= IOMMU_PROT_IR;
2131 if (iommu_prot & IOMMU_WRITE)
2132 prot |= IOMMU_PROT_IW;
2137 for (i = 0; i < npages; ++i) {
2138 ret = iommu_map_page(domain, iova, paddr, prot);
2149 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2150 unsigned long iova, size_t size)
2153 struct protection_domain *domain = dom->priv;
2154 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2158 for (i = 0; i < npages; ++i) {
2159 iommu_unmap_page(domain, iova);
2163 iommu_flush_domain(domain->id);
2166 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2169 struct protection_domain *domain = dom->priv;
2170 unsigned long offset = iova & ~PAGE_MASK;
2174 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
2176 if (!IOMMU_PTE_PRESENT(*pte))
2179 pte = IOMMU_PTE_PAGE(*pte);
2180 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
2182 if (!IOMMU_PTE_PRESENT(*pte))
2185 pte = IOMMU_PTE_PAGE(*pte);
2186 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
2188 if (!IOMMU_PTE_PRESENT(*pte))
2191 paddr = *pte & IOMMU_PAGE_MASK;
2197 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2203 static struct iommu_ops amd_iommu_ops = {
2204 .domain_init = amd_iommu_domain_init,
2205 .domain_destroy = amd_iommu_domain_destroy,
2206 .attach_dev = amd_iommu_attach_device,
2207 .detach_dev = amd_iommu_detach_device,
2208 .map = amd_iommu_map_range,
2209 .unmap = amd_iommu_unmap_range,
2210 .iova_to_phys = amd_iommu_iova_to_phys,
2211 .domain_has_cap = amd_iommu_domain_has_cap,