1 // SPDX-License-Identifier: GPL-2.0-only
3 * Dynamic DMA mapping support for AMD Hammer.
5 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
6 * This allows to use PCI devices that only support 32bit addresses on systems
9 * See Documentation/core-api/dma-api-howto.rst for the interface specification.
11 * Copyright 2002 Andi Kleen, SuSE Labs.
14 #include <linux/types.h>
15 #include <linux/ctype.h>
16 #include <linux/agp_backend.h>
17 #include <linux/init.h>
19 #include <linux/sched.h>
20 #include <linux/sched/debug.h>
21 #include <linux/string.h>
22 #include <linux/spinlock.h>
23 #include <linux/pci.h>
24 #include <linux/topology.h>
25 #include <linux/interrupt.h>
26 #include <linux/bitmap.h>
27 #include <linux/kdebug.h>
28 #include <linux/scatterlist.h>
29 #include <linux/iommu-helper.h>
30 #include <linux/syscore_ops.h>
32 #include <linux/gfp.h>
33 #include <linux/atomic.h>
34 #include <linux/dma-direct.h>
36 #include <asm/proto.h>
37 #include <asm/iommu.h>
39 #include <asm/set_memory.h>
40 #include <asm/swiotlb.h>
42 #include <asm/amd_nb.h>
43 #include <asm/x86_init.h>
44 #include <asm/iommu_table.h>
46 static unsigned long iommu_bus_base; /* GART remapping area (physical) */
47 static unsigned long iommu_size; /* size of remapping area bytes */
48 static unsigned long iommu_pages; /* .. and in pages */
50 static u32 *iommu_gatt_base; /* Remapping table */
53 * If this is disabled the IOMMU will use an optimized flushing strategy
54 * of only flushing when an mapping is reused. With it true the GART is
55 * flushed for every mapping. Problem is that doing the lazy flush seems
56 * to trigger bugs with some popular PCI cards, in particular 3ware (but
57 * has been also also seen with Qlogic at least).
59 static int iommu_fullflush = 1;
61 /* Allocation bitmap for the remapping area: */
62 static DEFINE_SPINLOCK(iommu_bitmap_lock);
63 /* Guarded by iommu_bitmap_lock: */
64 static unsigned long *iommu_gart_bitmap;
66 static u32 gart_unmapped_entry;
69 #define GPTE_COHERENT 2
70 #define GPTE_ENCODE(x) \
71 (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
72 #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
75 #define AGPEXTERN extern
80 /* GART can only remap to physical addresses < 1TB */
81 #define GART_MAX_PHYS_ADDR (1ULL << 40)
83 /* backdoor interface to AGP driver */
84 AGPEXTERN int agp_memory_reserved;
85 AGPEXTERN __u32 *agp_gatt_table;
87 static unsigned long next_bit; /* protected by iommu_bitmap_lock */
88 static bool need_flush; /* global flush state. set for each gart wrap */
90 static unsigned long alloc_iommu(struct device *dev, int size,
91 unsigned long align_mask)
93 unsigned long offset, flags;
94 unsigned long boundary_size;
95 unsigned long base_index;
97 base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev),
98 PAGE_SIZE) >> PAGE_SHIFT;
99 boundary_size = dma_get_seg_boundary_nr_pages(dev, PAGE_SHIFT);
101 spin_lock_irqsave(&iommu_bitmap_lock, flags);
102 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit,
103 size, base_index, boundary_size, align_mask);
106 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0,
107 size, base_index, boundary_size,
111 next_bit = offset+size;
112 if (next_bit >= iommu_pages) {
119 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
124 static void free_iommu(unsigned long offset, int size)
128 spin_lock_irqsave(&iommu_bitmap_lock, flags);
129 bitmap_clear(iommu_gart_bitmap, offset, size);
130 if (offset >= next_bit)
131 next_bit = offset + size;
132 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
136 * Use global flush state to avoid races with multiple flushers.
138 static void flush_gart(void)
142 spin_lock_irqsave(&iommu_bitmap_lock, flags);
147 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
150 #ifdef CONFIG_IOMMU_LEAK
151 /* Debugging aid for drivers that don't free their IOMMU tables */
152 static void dump_leak(void)
160 show_stack(NULL, NULL, KERN_ERR);
161 debug_dma_dump_mappings(NULL);
165 static void iommu_full(struct device *dev, size_t size, int dir)
168 * Ran out of IOMMU space for this operation. This is very bad.
169 * Unfortunately the drivers cannot handle this operation properly.
170 * Return some non mapped prereserved space in the aperture and
171 * let the Northbridge deal with it. This will result in garbage
172 * in the IO operation. When the size exceeds the prereserved space
173 * memory corruption will occur or random memory will be DMAed
174 * out. Hopefully no network devices use single mappings that big.
177 dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size);
178 #ifdef CONFIG_IOMMU_LEAK
184 need_iommu(struct device *dev, unsigned long addr, size_t size)
186 return force_iommu || !dma_capable(dev, addr, size, true);
190 nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
192 return !dma_capable(dev, addr, size, true);
195 /* Map a single continuous physical area into the IOMMU.
196 * Caller needs to check if the iommu is needed and flush.
198 static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
199 size_t size, int dir, unsigned long align_mask)
201 unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE);
202 unsigned long iommu_page;
205 if (unlikely(phys_mem + size > GART_MAX_PHYS_ADDR))
206 return DMA_MAPPING_ERROR;
208 iommu_page = alloc_iommu(dev, npages, align_mask);
209 if (iommu_page == -1) {
210 if (!nonforced_iommu(dev, phys_mem, size))
212 if (panic_on_overflow)
213 panic("dma_map_area overflow %lu bytes\n", size);
214 iommu_full(dev, size, dir);
215 return DMA_MAPPING_ERROR;
218 for (i = 0; i < npages; i++) {
219 iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
220 phys_mem += PAGE_SIZE;
222 return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
225 /* Map a single area into the IOMMU */
226 static dma_addr_t gart_map_page(struct device *dev, struct page *page,
227 unsigned long offset, size_t size,
228 enum dma_data_direction dir,
232 phys_addr_t paddr = page_to_phys(page) + offset;
234 if (!need_iommu(dev, paddr, size))
237 bus = dma_map_area(dev, paddr, size, dir, 0);
244 * Free a DMA mapping.
246 static void gart_unmap_page(struct device *dev, dma_addr_t dma_addr,
247 size_t size, enum dma_data_direction dir,
250 unsigned long iommu_page;
254 if (WARN_ON_ONCE(dma_addr == DMA_MAPPING_ERROR))
258 * This driver will not always use a GART mapping, but might have
259 * created a direct mapping instead. If that is the case there is
260 * nothing to unmap here.
262 if (dma_addr < iommu_bus_base ||
263 dma_addr >= iommu_bus_base + iommu_size)
266 iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
267 npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
268 for (i = 0; i < npages; i++) {
269 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
271 free_iommu(iommu_page, npages);
275 * Wrapper for pci_unmap_single working with scatterlists.
277 static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
278 enum dma_data_direction dir, unsigned long attrs)
280 struct scatterlist *s;
283 for_each_sg(sg, s, nents, i) {
284 if (!s->dma_length || !s->length)
286 gart_unmap_page(dev, s->dma_address, s->dma_length, dir, 0);
290 /* Fallback for dma_map_sg in case of overflow */
291 static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
294 struct scatterlist *s;
297 #ifdef CONFIG_IOMMU_DEBUG
298 pr_debug("dma_map_sg overflow\n");
301 for_each_sg(sg, s, nents, i) {
302 unsigned long addr = sg_phys(s);
304 if (nonforced_iommu(dev, addr, s->length)) {
305 addr = dma_map_area(dev, addr, s->length, dir, 0);
306 if (addr == DMA_MAPPING_ERROR) {
308 gart_unmap_sg(dev, sg, i, dir, 0);
310 sg[0].dma_length = 0;
314 s->dma_address = addr;
315 s->dma_length = s->length;
322 /* Map multiple scatterlist entries continuous into the first. */
323 static int __dma_map_cont(struct device *dev, struct scatterlist *start,
324 int nelems, struct scatterlist *sout,
327 unsigned long iommu_start = alloc_iommu(dev, pages, 0);
328 unsigned long iommu_page = iommu_start;
329 struct scatterlist *s;
332 if (iommu_start == -1)
335 for_each_sg(start, s, nelems, i) {
336 unsigned long pages, addr;
337 unsigned long phys_addr = s->dma_address;
339 BUG_ON(s != start && s->offset);
341 sout->dma_address = iommu_bus_base;
342 sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
343 sout->dma_length = s->length;
345 sout->dma_length += s->length;
349 pages = iommu_num_pages(s->offset, s->length, PAGE_SIZE);
351 iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
356 BUG_ON(iommu_page - iommu_start != pages);
362 dma_map_cont(struct device *dev, struct scatterlist *start, int nelems,
363 struct scatterlist *sout, unsigned long pages, int need)
367 sout->dma_address = start->dma_address;
368 sout->dma_length = start->length;
371 return __dma_map_cont(dev, start, nelems, sout, pages);
375 * DMA map all entries in a scatterlist.
376 * Merge chunks that have page aligned sizes into a continuous mapping.
378 static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents,
379 enum dma_data_direction dir, unsigned long attrs)
381 struct scatterlist *s, *ps, *start_sg, *sgmap;
382 int need = 0, nextneed, i, out, start;
383 unsigned long pages = 0;
384 unsigned int seg_size;
385 unsigned int max_seg_size;
395 max_seg_size = dma_get_max_seg_size(dev);
396 ps = NULL; /* shut up gcc */
398 for_each_sg(sg, s, nents, i) {
399 dma_addr_t addr = sg_phys(s);
401 s->dma_address = addr;
402 BUG_ON(s->length == 0);
404 nextneed = need_iommu(dev, addr, s->length);
406 /* Handle the previous not yet processed entries */
409 * Can only merge when the last chunk ends on a
410 * page boundary and the new one doesn't have an
413 if (!iommu_merge || !nextneed || !need || s->offset ||
414 (s->length + seg_size > max_seg_size) ||
415 (ps->offset + ps->length) % PAGE_SIZE) {
416 if (dma_map_cont(dev, start_sg, i - start,
417 sgmap, pages, need) < 0)
422 sgmap = sg_next(sgmap);
429 seg_size += s->length;
431 pages += iommu_num_pages(s->offset, s->length, PAGE_SIZE);
434 if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0)
439 sgmap = sg_next(sgmap);
440 sgmap->dma_length = 0;
446 gart_unmap_sg(dev, sg, out, dir, 0);
448 /* When it was forced or merged try again in a dumb way */
449 if (force_iommu || iommu_merge) {
450 out = dma_map_sg_nonforce(dev, sg, nents, dir);
454 if (panic_on_overflow)
455 panic("dma_map_sg: overflow on %lu pages\n", pages);
457 iommu_full(dev, pages << PAGE_SHIFT, dir);
458 for_each_sg(sg, s, nents, i)
459 s->dma_address = DMA_MAPPING_ERROR;
463 /* allocate and map a coherent mapping */
465 gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
466 gfp_t flag, unsigned long attrs)
470 vaddr = dma_direct_alloc(dev, size, dma_addr, flag, attrs);
472 !force_iommu || dev->coherent_dma_mask <= DMA_BIT_MASK(24))
475 *dma_addr = dma_map_area(dev, virt_to_phys(vaddr), size,
476 DMA_BIDIRECTIONAL, (1UL << get_order(size)) - 1);
478 if (unlikely(*dma_addr == DMA_MAPPING_ERROR))
482 dma_direct_free(dev, size, vaddr, *dma_addr, attrs);
486 /* free a coherent mapping */
488 gart_free_coherent(struct device *dev, size_t size, void *vaddr,
489 dma_addr_t dma_addr, unsigned long attrs)
491 gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, 0);
492 dma_direct_free(dev, size, vaddr, dma_addr, attrs);
497 static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
502 iommu_size = aper_size;
507 a = aper + iommu_size;
508 iommu_size -= round_up(a, PMD_PAGE_SIZE) - a;
510 if (iommu_size < 64*1024*1024) {
511 pr_warn("PCI-DMA: Warning: Small IOMMU %luMB."
512 " Consider increasing the AGP aperture in BIOS\n",
519 static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
521 unsigned aper_size = 0, aper_base_32, aper_order;
524 pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
525 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
526 aper_order = (aper_order >> 1) & 7;
528 aper_base = aper_base_32 & 0x7fff;
531 aper_size = (32 * 1024 * 1024) << aper_order;
532 if (aper_base + aper_size > 0x100000000UL || !aper_size)
539 static void enable_gart_translations(void)
543 if (!amd_nb_has_feature(AMD_NB_GART))
546 for (i = 0; i < amd_nb_num(); i++) {
547 struct pci_dev *dev = node_to_amd_nb(i)->misc;
549 enable_gart_translation(dev, __pa(agp_gatt_table));
552 /* Flush the GART-TLB to remove stale entries */
557 * If fix_up_north_bridges is set, the north bridges have to be fixed up on
558 * resume in the same way as they are handled in gart_iommu_hole_init().
560 static bool fix_up_north_bridges;
561 static u32 aperture_order;
562 static u32 aperture_alloc;
564 void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
566 fix_up_north_bridges = true;
567 aperture_order = aper_order;
568 aperture_alloc = aper_alloc;
571 static void gart_fixup_northbridges(void)
575 if (!fix_up_north_bridges)
578 if (!amd_nb_has_feature(AMD_NB_GART))
581 pr_info("PCI-DMA: Restoring GART aperture settings\n");
583 for (i = 0; i < amd_nb_num(); i++) {
584 struct pci_dev *dev = node_to_amd_nb(i)->misc;
587 * Don't enable translations just yet. That is the next
588 * step. Restore the pre-suspend aperture settings.
590 gart_set_size_and_enable(dev, aperture_order);
591 pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE, aperture_alloc >> 25);
595 static void gart_resume(void)
597 pr_info("PCI-DMA: Resuming GART IOMMU\n");
599 gart_fixup_northbridges();
601 enable_gart_translations();
604 static struct syscore_ops gart_syscore_ops = {
605 .resume = gart_resume,
610 * Private Northbridge GATT initialization in case we cannot use the
611 * AGP driver for some reason.
613 static __init int init_amd_gatt(struct agp_kern_info *info)
615 unsigned aper_size, gatt_size, new_aper_size;
616 unsigned aper_base, new_aper_base;
621 pr_info("PCI-DMA: Disabling AGP.\n");
623 aper_size = aper_base = info->aper_size = 0;
625 for (i = 0; i < amd_nb_num(); i++) {
626 dev = node_to_amd_nb(i)->misc;
627 new_aper_base = read_aperture(dev, &new_aper_size);
632 aper_size = new_aper_size;
633 aper_base = new_aper_base;
635 if (aper_size != new_aper_size || aper_base != new_aper_base)
641 info->aper_base = aper_base;
642 info->aper_size = aper_size >> 20;
644 gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
645 gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
646 get_order(gatt_size));
648 panic("Cannot allocate GATT table");
649 if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
650 panic("Could not set GART PTEs to uncacheable pages");
652 agp_gatt_table = gatt;
654 register_syscore_ops(&gart_syscore_ops);
658 pr_info("PCI-DMA: aperture base @ %x size %u KB\n",
659 aper_base, aper_size>>10);
664 /* Should not happen anymore */
665 pr_warn("PCI-DMA: More than 4GB of RAM and no IOMMU - falling back to iommu=soft.\n");
669 static const struct dma_map_ops gart_dma_ops = {
670 .map_sg = gart_map_sg,
671 .unmap_sg = gart_unmap_sg,
672 .map_page = gart_map_page,
673 .unmap_page = gart_unmap_page,
674 .alloc = gart_alloc_coherent,
675 .free = gart_free_coherent,
676 .mmap = dma_common_mmap,
677 .get_sgtable = dma_common_get_sgtable,
678 .dma_supported = dma_direct_supported,
679 .get_required_mask = dma_direct_get_required_mask,
680 .alloc_pages = dma_direct_alloc_pages,
681 .free_pages = dma_direct_free_pages,
684 static void gart_iommu_shutdown(void)
689 /* don't shutdown it if there is AGP installed */
693 if (!amd_nb_has_feature(AMD_NB_GART))
696 for (i = 0; i < amd_nb_num(); i++) {
699 dev = node_to_amd_nb(i)->misc;
700 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
704 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
708 int __init gart_iommu_init(void)
710 struct agp_kern_info info;
711 unsigned long iommu_start;
712 unsigned long aper_base, aper_size;
713 unsigned long start_pfn, end_pfn;
714 unsigned long scratch;
716 if (!amd_nb_has_feature(AMD_NB_GART))
719 #ifndef CONFIG_AGP_AMD64
722 /* Makefile puts PCI initialization via subsys_initcall first. */
723 /* Add other AMD AGP bridge drivers here */
725 (agp_amd64_init() < 0) ||
726 (agp_copy_info(agp_bridge, &info) < 0);
730 (!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
731 !gart_iommu_aperture ||
732 (no_agp && init_amd_gatt(&info) < 0)) {
733 if (max_pfn > MAX_DMA32_PFN) {
734 pr_warn("More than 4GB of memory but GART IOMMU not available.\n");
735 pr_warn("falling back to iommu=soft.\n");
740 /* need to map that range */
741 aper_size = info.aper_size << 20;
742 aper_base = info.aper_base;
743 end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
745 start_pfn = PFN_DOWN(aper_base);
746 if (!pfn_range_is_mapped(start_pfn, end_pfn))
747 init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT,
750 pr_info("PCI-DMA: using GART IOMMU.\n");
751 iommu_size = check_iommu_size(info.aper_base, aper_size);
752 iommu_pages = iommu_size >> PAGE_SHIFT;
754 iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO,
755 get_order(iommu_pages/8));
756 if (!iommu_gart_bitmap)
757 panic("Cannot allocate iommu bitmap\n");
759 pr_info("PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
762 agp_memory_reserved = iommu_size;
763 iommu_start = aper_size - iommu_size;
764 iommu_bus_base = info.aper_base + iommu_start;
765 iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
768 * Unmap the IOMMU part of the GART. The alias of the page is
769 * always mapped with cache enabled and there is no full cache
770 * coherency across the GART remapping. The unmapping avoids
771 * automatic prefetches from the CPU allocating cache lines in
772 * there. All CPU accesses are done via the direct mapping to
773 * the backing memory. The GART address is only used by PCI
776 set_memory_np((unsigned long)__va(iommu_bus_base),
777 iommu_size >> PAGE_SHIFT);
779 * Tricky. The GART table remaps the physical memory range,
780 * so the CPU wont notice potential aliases and if the memory
781 * is remapped to UC later on, we might surprise the PCI devices
782 * with a stray writeout of a cacheline. So play it sure and
783 * do an explicit, full-scale wbinvd() _after_ having marked all
784 * the pages as Not-Present:
789 * Now all caches are flushed and we can safely enable
790 * GART hardware. Doing it early leaves the possibility
791 * of stale cache entries that can lead to GART PTE
794 enable_gart_translations();
797 * Try to workaround a bug (thanks to BenH):
798 * Set unmapped entries to a scratch page instead of 0.
799 * Any prefetches that hit unmapped entries won't get an bus abort
800 * then. (P2P bridge may be prefetching on DMA reads).
802 scratch = get_zeroed_page(GFP_KERNEL);
804 panic("Cannot allocate iommu scratch page");
805 gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
808 dma_ops = &gart_dma_ops;
809 x86_platform.iommu_shutdown = gart_iommu_shutdown;
815 void __init gart_parse_options(char *p)
819 if (isdigit(*p) && get_option(&p, &arg))
821 if (!strncmp(p, "fullflush", 9))
823 if (!strncmp(p, "nofullflush", 11))
825 if (!strncmp(p, "noagp", 5))
827 if (!strncmp(p, "noaperture", 10))
829 /* duplicated from pci-dma.c */
830 if (!strncmp(p, "force", 5))
831 gart_iommu_aperture_allowed = 1;
832 if (!strncmp(p, "allowed", 7))
833 gart_iommu_aperture_allowed = 1;
834 if (!strncmp(p, "memaper", 7)) {
835 fallback_aper_force = 1;
839 if (get_option(&p, &arg))
840 fallback_aper_order = arg;
844 IOMMU_INIT_POST(gart_iommu_hole_init);