2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV architectural definitions
8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
11 #ifndef _ASM_X86_UV_UV_HUB_H
12 #define _ASM_X86_UV_UV_HUB_H
15 #include <linux/numa.h>
16 #include <linux/percpu.h>
17 #include <linux/timer.h>
19 #include <linux/topology.h>
20 #include <asm/types.h>
21 #include <asm/percpu.h>
22 #include <asm/uv/uv_mmrs.h>
23 #include <asm/irq_vectors.h>
24 #include <asm/io_apic.h>
28 * Addressing Terminology
30 * M - The low M bits of a physical address represent the offset
31 * into the blade local memory. RAM memory on a blade is physically
32 * contiguous (although various IO spaces may punch holes in
35 * N - Number of bits in the node portion of a socket physical
38 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
39 * routers always have low bit of 1, C/MBricks have low bit
40 * equal to 0. Most addressing macros that target UV hub chips
41 * right shift the NASID by 1 to exclude the always-zero bit.
42 * NASIDs contain up to 15 bits.
44 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
47 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
48 * of the nasid for socket usage.
50 * GPA - (global physical address) a socket physical address converted
51 * so that it can be used by the GRU as a global address. Socket
52 * physical addresses 1) need additional NASID (node) bits added
53 * to the high end of the address, and 2) unaliased if the
54 * partition does not have a physical address 0. In addition, on
55 * UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40.
58 * NumaLink Global Physical Address Format:
59 * +--------------------------------+---------------------+
60 * |00..000| GNODE | NodeOffset |
61 * +--------------------------------+---------------------+
62 * |<-------53 - M bits --->|<--------M bits ----->
64 * M - number of node offset bits (35 .. 40)
67 * Memory/UV-HUB Processor Socket Address Format:
68 * +----------------+---------------+---------------------+
69 * |00..000000000000| PNODE | NodeOffset |
70 * +----------------+---------------+---------------------+
71 * <--- N bits --->|<--------M bits ----->
73 * M - number of node offset bits (35 .. 40)
74 * N - number of PNODE bits (0 .. 10)
76 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
77 * The actual values are configuration dependent and are set at
78 * boot time. M & N values are set by the hardware/BIOS at boot.
82 * NOTE!!!!!! This is the current format of the APICID. However, code
83 * should assume that this will change in the future. Use functions
84 * in this file for all APICID bit manipulations and conversion.
88 * pppppppppplc0cch Nehalem-EX (12 bits in hdw reg)
89 * ppppppppplcc0cch Westmere-EX (12 bits in hdw reg)
90 * pppppppppppcccch SandyBridge (15 bits in hdw reg)
94 * l = socket number on board
97 * s = bits that are in the SOCKET_ID CSR
99 * Note: Processor may support fewer bits in the APICID register. The ACPI
100 * tables hold all 16 bits. Software needs to be aware of this.
102 * Unless otherwise specified, all references to APICID refer to
103 * the FULL value contained in ACPI tables, not the subset in the
104 * processor APICID register.
109 * Maximum number of bricks in all partitions and in all coherency domains.
110 * This is the total number of bricks accessible in the numalink fabric. It
111 * includes all C & M bricks. Routers are NOT included.
113 * This value is also the value of the maximum number of non-router NASIDs
114 * in the numalink fabric.
116 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
118 #define UV_MAX_NUMALINK_BLADES 16384
121 * Maximum number of C/Mbricks within a software SSI (hardware may support
124 #define UV_MAX_SSI_BLADES 256
127 * The largest possible NASID of a C or M brick (+ 2)
129 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2)
131 /* System Controller Interface Reg info */
133 struct timer_list timer;
134 unsigned long offset;
136 unsigned long idle_on;
137 unsigned long idle_off;
139 unsigned char enabled;
143 * The following defines attributes of the HUB chip. These attributes are
144 * frequently referenced and are kept in a common per hub struct.
145 * After setup, the struct is read only, so it should be readily
146 * available in the L3 cache on the cpu socket for the node.
148 struct uv_hub_info_s {
149 unsigned long global_mmr_base;
150 unsigned long global_mmr_shift;
151 unsigned long gpa_mask;
152 unsigned short min_socket;
153 unsigned short min_pnode;
154 unsigned char hub_revision;
155 unsigned char apic_pnode_shift;
156 unsigned char gpa_shift;
157 unsigned char m_shift;
158 unsigned char n_lshift;
159 unsigned int gnode_extra;
160 unsigned long gnode_upper;
161 unsigned long lowmem_remap_top;
162 unsigned long lowmem_remap_base;
163 unsigned long global_gru_base;
164 unsigned long global_gru_shift;
165 unsigned short pnode;
166 unsigned short pnode_mask;
167 unsigned short coherency_domain_number;
168 unsigned short numa_blade_id;
171 unsigned short nr_possible_cpus;
172 unsigned short nr_online_cpus;
176 /* CPU specific info with a pointer to the hub common info struct */
177 struct uv_cpu_info_s {
179 unsigned char blade_cpu_id;
180 struct uv_scir_s scir;
182 DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
184 #define uv_cpu_info this_cpu_ptr(&__uv_cpu_info)
185 #define uv_cpu_info_per(cpu) (&per_cpu(__uv_cpu_info, cpu))
187 #define uv_scir_info (&uv_cpu_info->scir)
188 #define uv_cpu_scir_info(cpu) (&uv_cpu_info_per(cpu)->scir)
190 /* Node specific hub common info struct */
191 extern void **__uv_hub_info_list;
192 static inline struct uv_hub_info_s *uv_hub_info_list(int node)
194 return (struct uv_hub_info_s *)__uv_hub_info_list[node];
197 static inline struct uv_hub_info_s *_uv_hub_info(void)
199 return (struct uv_hub_info_s *)uv_cpu_info->p_uv_hub_info;
201 #define uv_hub_info _uv_hub_info()
203 static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu)
205 return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info;
208 #define UV_HUB_INFO_VERSION 0x7150
209 extern int uv_hub_info_version(void);
210 static inline int uv_hub_info_check(int version)
212 if (uv_hub_info_version() == version)
215 pr_crit("UV: uv_hub_info version(%x) mismatch, expecting(%x)\n",
216 uv_hub_info_version(), version);
218 BUG(); /* Catastrophic - cannot continue on unknown UV system */
220 #define _uv_hub_info_check() uv_hub_info_check(UV_HUB_INFO_VERSION)
223 * HUB revision ranges for each UV HUB architecture.
224 * This is a software convention - NOT the hardware revision numbers in
227 #define UV1_HUB_REVISION_BASE 1
228 #define UV2_HUB_REVISION_BASE 3
229 #define UV3_HUB_REVISION_BASE 5
230 #define UV4_HUB_REVISION_BASE 7
232 #ifdef UV1_HUB_IS_SUPPORTED
233 static inline int is_uv1_hub(void)
235 return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE;
238 static inline int is_uv1_hub(void)
244 #ifdef UV2_HUB_IS_SUPPORTED
245 static inline int is_uv2_hub(void)
247 return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) &&
248 (uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE));
251 static inline int is_uv2_hub(void)
257 #ifdef UV3_HUB_IS_SUPPORTED
258 static inline int is_uv3_hub(void)
260 return ((uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE) &&
261 (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE));
264 static inline int is_uv3_hub(void)
270 #ifdef UV4_HUB_IS_SUPPORTED
271 static inline int is_uv4_hub(void)
273 return uv_hub_info->hub_revision >= UV4_HUB_REVISION_BASE;
276 static inline int is_uv4_hub(void)
282 static inline int is_uvx_hub(void)
284 if (uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE)
285 return uv_hub_info->hub_revision;
290 static inline int is_uv_hub(void)
292 #ifdef UV1_HUB_IS_SUPPORTED
293 return uv_hub_info->hub_revision;
300 struct uvh_apicid_s {
301 unsigned long local_apic_mask : 24;
302 unsigned long local_apic_shift : 5;
303 unsigned long unused1 : 3;
304 unsigned long pnode_mask : 24;
305 unsigned long pnode_shift : 5;
306 unsigned long unused2 : 3;
311 * Local & Global MMR space macros.
312 * Note: macros are intended to be used ONLY by inline functions
313 * in this file - not by other kernel code.
314 * n - NASID (full 15-bit global nasid)
315 * g - GNODE (full 15-bit global nasid, right shifted 1)
316 * p - PNODE (local part of nsids, right shifted 1)
318 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
319 #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra)
320 #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1)
322 #define UV1_LOCAL_MMR_BASE 0xf4000000UL
323 #define UV1_GLOBAL_MMR32_BASE 0xf8000000UL
324 #define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
325 #define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
327 #define UV2_LOCAL_MMR_BASE 0xfa000000UL
328 #define UV2_GLOBAL_MMR32_BASE 0xfc000000UL
329 #define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
330 #define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024)
332 #define UV3_LOCAL_MMR_BASE 0xfa000000UL
333 #define UV3_GLOBAL_MMR32_BASE 0xfc000000UL
334 #define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
335 #define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024)
337 #define UV4_LOCAL_MMR_BASE 0xfa000000UL
338 #define UV4_GLOBAL_MMR32_BASE 0xfc000000UL
339 #define UV4_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
340 #define UV4_GLOBAL_MMR32_SIZE (16UL * 1024 * 1024)
342 #define UV_LOCAL_MMR_BASE ( \
343 is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \
344 is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \
345 is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \
346 /*is_uv4_hub*/ UV4_LOCAL_MMR_BASE)
348 #define UV_GLOBAL_MMR32_BASE ( \
349 is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE : \
350 is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \
351 is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \
352 /*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE)
354 #define UV_LOCAL_MMR_SIZE ( \
355 is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \
356 is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \
357 is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \
358 /*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE)
360 #define UV_GLOBAL_MMR32_SIZE ( \
361 is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE : \
362 is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \
363 is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \
364 /*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE)
366 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
368 #define UV_GLOBAL_GRU_MMR_BASE 0x4000000
370 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15
371 #define _UV_GLOBAL_MMR64_PNODE_SHIFT 26
372 #define UV_GLOBAL_MMR64_PNODE_SHIFT (uv_hub_info->global_mmr_shift)
374 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
376 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \
377 (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
379 #define UVH_APICID 0x002D0E00L
380 #define UV_APIC_PNODE_SHIFT 6
382 #define UV_APICID_HIBIT_MASK 0xffff0000
384 /* Local Bus from cpu's perspective */
385 #define LOCAL_BUS_BASE 0x1c00000
386 #define LOCAL_BUS_SIZE (4 * 1024 * 1024)
389 * System Controller Interface Reg
391 * Note there are NO leds on a UV system. This register is only
392 * used by the system controller to monitor system-wide operation.
393 * There are 64 regs per node. With Nahelem cpus (2 cores per node,
394 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
397 * The window is located at top of ACPI MMR space
399 #define SCIR_WINDOW_COUNT 64
400 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \
404 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */
405 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */
406 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */
408 /* Loop through all installed blades */
409 #define for_each_possible_blade(bid) \
410 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
413 * Macros for converting between kernel virtual addresses, socket local physical
414 * addresses, and UV global physical addresses.
415 * Note: use the standard __pa() & __va() macros for converting
416 * between socket virtual and socket physical addresses.
419 /* socket phys RAM --> UV global physical address */
420 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
422 if (paddr < uv_hub_info->lowmem_remap_top)
423 paddr |= uv_hub_info->lowmem_remap_base;
424 paddr |= uv_hub_info->gnode_upper;
425 paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
426 ((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift);
431 /* socket virtual --> UV global physical address */
432 static inline unsigned long uv_gpa(void *v)
434 return uv_soc_phys_ram_to_gpa(__pa(v));
437 /* Top two bits indicate the requested address is in MMR space. */
439 uv_gpa_in_mmr_space(unsigned long gpa)
441 return (gpa >> 62) == 0x3UL;
444 /* UV global physical address --> socket phys RAM */
445 static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa)
448 unsigned long remap_base = uv_hub_info->lowmem_remap_base;
449 unsigned long remap_top = uv_hub_info->lowmem_remap_top;
451 gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
452 ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val);
453 paddr = gpa & uv_hub_info->gpa_mask;
454 if (paddr >= remap_base && paddr < remap_base + remap_top)
461 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa)
463 return gpa >> uv_hub_info->n_lshift;
467 static inline int uv_gpa_to_pnode(unsigned long gpa)
469 return uv_gpa_to_gnode(gpa) & uv_hub_info->pnode_mask;
472 /* gpa -> node offset */
473 static inline unsigned long uv_gpa_to_offset(unsigned long gpa)
475 return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift;
478 /* pnode, offset --> socket virtual */
479 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
481 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
484 /* Extract a PNODE from an APICID (full apicid, not processor subset) */
485 static inline int uv_apicid_to_pnode(int apicid)
487 return (apicid >> uv_hub_info->apic_pnode_shift);
490 /* Convert an apicid to the socket number on the blade */
491 static inline int uv_apicid_to_socket(int apicid)
494 return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1;
500 * Access global MMRs using the low memory MMR32 space. This region supports
501 * faster MMR access but not all MMRs are accessible in this space.
503 static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset)
505 return __va(UV_GLOBAL_MMR32_BASE |
506 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
509 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val)
511 writeq(val, uv_global_mmr32_address(pnode, offset));
514 static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset)
516 return readq(uv_global_mmr32_address(pnode, offset));
520 * Access Global MMR space using the MMR space located at the top of physical
523 static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset)
525 return __va(UV_GLOBAL_MMR64_BASE |
526 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
529 static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val)
531 writeq(val, uv_global_mmr64_address(pnode, offset));
534 static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset)
536 return readq(uv_global_mmr64_address(pnode, offset));
540 * Global MMR space addresses when referenced by the GRU. (GRU does
541 * NOT use socket addressing).
543 static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset)
545 return UV_GLOBAL_GRU_MMR_BASE | offset |
546 ((unsigned long)pnode << uv_hub_info->m_val);
549 static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val)
551 writeb(val, uv_global_mmr64_address(pnode, offset));
554 static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset)
556 return readb(uv_global_mmr64_address(pnode, offset));
560 * Access hub local MMRs. Faster than using global space but only local MMRs
563 static inline unsigned long *uv_local_mmr_address(unsigned long offset)
565 return __va(UV_LOCAL_MMR_BASE | offset);
568 static inline unsigned long uv_read_local_mmr(unsigned long offset)
570 return readq(uv_local_mmr_address(offset));
573 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
575 writeq(val, uv_local_mmr_address(offset));
578 static inline unsigned char uv_read_local_mmr8(unsigned long offset)
580 return readb(uv_local_mmr_address(offset));
583 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
585 writeb(val, uv_local_mmr_address(offset));
588 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
589 static inline int uv_blade_processor_id(void)
591 return uv_cpu_info->blade_cpu_id;
594 /* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */
595 static inline int uv_cpu_blade_processor_id(int cpu)
597 return uv_cpu_info_per(cpu)->blade_cpu_id;
599 #define _uv_cpu_blade_processor_id 1 /* indicate function available */
601 /* Blade number to Node number (UV1..UV4 is 1:1) */
602 static inline int uv_blade_to_node(int blade)
607 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
608 static inline int uv_numa_blade_id(void)
610 return uv_hub_info->numa_blade_id;
614 * Convert linux node number to the UV blade number.
615 * .. Currently for UV1 thru UV4 the node and the blade are identical.
616 * .. If this changes then you MUST check references to this function!
618 static inline int uv_node_to_blade_id(int nid)
623 /* Convert a cpu number to the the UV blade number */
624 static inline int uv_cpu_to_blade_id(int cpu)
626 return uv_node_to_blade_id(cpu_to_node(cpu));
629 /* Convert a blade id to the PNODE of the blade */
630 static inline int uv_blade_to_pnode(int bid)
632 return uv_hub_info_list(uv_blade_to_node(bid))->pnode;
635 /* Nid of memory node on blade. -1 if no blade-local memory */
636 static inline int uv_blade_to_memory_nid(int bid)
638 return uv_hub_info_list(uv_blade_to_node(bid))->memory_nid;
641 /* Determine the number of possible cpus on a blade */
642 static inline int uv_blade_nr_possible_cpus(int bid)
644 return uv_hub_info_list(uv_blade_to_node(bid))->nr_possible_cpus;
647 /* Determine the number of online cpus on a blade */
648 static inline int uv_blade_nr_online_cpus(int bid)
650 return uv_hub_info_list(uv_blade_to_node(bid))->nr_online_cpus;
653 /* Convert a cpu id to the PNODE of the blade containing the cpu */
654 static inline int uv_cpu_to_pnode(int cpu)
656 return uv_cpu_hub_info(cpu)->pnode;
659 /* Convert a linux node number to the PNODE of the blade */
660 static inline int uv_node_to_pnode(int nid)
662 return uv_hub_info_list(nid)->pnode;
665 /* Maximum possible number of blades */
666 extern short uv_possible_blades;
667 static inline int uv_num_possible_blades(void)
669 return uv_possible_blades;
672 /* Per Hub NMI support */
673 extern void uv_nmi_setup(void);
675 /* BMC sets a bit this MMR non-zero before sending an NMI */
676 #define UVH_NMI_MMR UVH_SCRATCH5
677 #define UVH_NMI_MMR_CLEAR UVH_SCRATCH5_ALIAS
678 #define UVH_NMI_MMR_SHIFT 63
679 #define UVH_NMI_MMR_TYPE "SCRATCH5"
681 /* Newer SMM NMI handler, not present in all systems */
682 #define UVH_NMI_MMRX UVH_EVENT_OCCURRED0
683 #define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS
684 #define UVH_NMI_MMRX_SHIFT UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT
685 #define UVH_NMI_MMRX_TYPE "EXTIO_INT0"
687 /* Non-zero indicates newer SMM NMI handler present */
688 #define UVH_NMI_MMRX_SUPPORTED UVH_EXTIO_INT0_BROADCAST
690 /* Indicates to BIOS that we want to use the newer SMM NMI handler */
691 #define UVH_NMI_MMRX_REQ UVH_SCRATCH5_ALIAS_2
692 #define UVH_NMI_MMRX_REQ_SHIFT 62
694 struct uv_hub_nmi_s {
695 raw_spinlock_t nmi_lock;
696 atomic_t in_nmi; /* flag this node in UV NMI IRQ */
697 atomic_t cpu_owner; /* last locker of this struct */
698 atomic_t read_mmr_count; /* count of MMR reads */
699 atomic_t nmi_count; /* count of true UV NMIs */
700 unsigned long nmi_value; /* last value read from NMI MMR */
703 struct uv_cpu_nmi_s {
704 struct uv_hub_nmi_s *hub;
711 DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi);
713 #define uv_hub_nmi this_cpu_read(uv_cpu_nmi.hub)
714 #define uv_cpu_nmi_per(cpu) (per_cpu(uv_cpu_nmi, cpu))
715 #define uv_hub_nmi_per(cpu) (uv_cpu_nmi_per(cpu).hub)
717 /* uv_cpu_nmi_states */
718 #define UV_NMI_STATE_OUT 0
719 #define UV_NMI_STATE_IN 1
720 #define UV_NMI_STATE_DUMP 2
721 #define UV_NMI_STATE_DUMP_DONE 3
723 /* Update SCIR state */
724 static inline void uv_set_scir_bits(unsigned char value)
726 if (uv_scir_info->state != value) {
727 uv_scir_info->state = value;
728 uv_write_local_mmr8(uv_scir_info->offset, value);
732 static inline unsigned long uv_scir_offset(int apicid)
734 return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f);
737 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
739 if (uv_cpu_scir_info(cpu)->state != value) {
740 uv_write_global_mmr8(uv_cpu_to_pnode(cpu),
741 uv_cpu_scir_info(cpu)->offset, value);
742 uv_cpu_scir_info(cpu)->state = value;
746 extern unsigned int uv_apicid_hibits;
747 static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode)
749 apicid |= uv_apicid_hibits;
750 return (1UL << UVH_IPI_INT_SEND_SHFT) |
751 ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
752 (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
753 (vector << UVH_IPI_INT_VECTOR_SHFT);
756 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
759 unsigned long dmode = dest_Fixed;
761 if (vector == NMI_VECTOR)
764 val = uv_hub_ipi_value(apicid, vector, dmode);
765 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
769 * Get the minimum revision number of the hub chips within the partition.
770 * (See UVx_HUB_REVISION_BASE above for specific values.)
772 static inline int uv_get_min_hub_revision_id(void)
774 return uv_hub_info->hub_revision;
777 #endif /* CONFIG_X86_64 */
778 #endif /* _ASM_X86_UV_UV_HUB_H */