1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_TLBFLUSH_H
3 #define _ASM_X86_TLBFLUSH_H
5 #include <linux/mm_types.h>
6 #include <linux/sched.h>
8 #include <asm/processor.h>
9 #include <asm/cpufeature.h>
10 #include <asm/special_insns.h>
12 #include <asm/invpcid.h>
14 #include <asm/processor-flags.h>
15 #include <asm/pgtable.h>
17 DECLARE_PER_CPU(u64, tlbstate_untag_mask);
19 void __flush_tlb_all(void);
21 #define TLB_FLUSH_ALL -1UL
22 #define TLB_GENERATION_INVALID 0
24 void cr4_update_irqsoff(unsigned long set, unsigned long clear);
25 unsigned long cr4_read_shadow(void);
27 /* Set in this cpu's CR4. */
28 static inline void cr4_set_bits_irqsoff(unsigned long mask)
30 cr4_update_irqsoff(mask, 0);
33 /* Clear in this cpu's CR4. */
34 static inline void cr4_clear_bits_irqsoff(unsigned long mask)
36 cr4_update_irqsoff(0, mask);
39 /* Set in this cpu's CR4. */
40 static inline void cr4_set_bits(unsigned long mask)
44 local_irq_save(flags);
45 cr4_set_bits_irqsoff(mask);
46 local_irq_restore(flags);
49 /* Clear in this cpu's CR4. */
50 static inline void cr4_clear_bits(unsigned long mask)
54 local_irq_save(flags);
55 cr4_clear_bits_irqsoff(mask);
56 local_irq_restore(flags);
61 * 6 because 6 should be plenty and struct tlb_state will fit in two cache
64 #define TLB_NR_DYN_ASIDS 6
73 * cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
74 * are on. This means that it may not match current->active_mm,
75 * which will contain the previous user mm when we're in lazy TLB
76 * mode even if we've already switched back to swapper_pg_dir.
78 * During switch_mm_irqs_off(), loaded_mm will be set to
79 * LOADED_MM_SWITCHING during the brief interrupts-off window
80 * when CR3 and loaded_mm would otherwise be inconsistent. This
81 * is for nmi_uaccess_okay()'s benefit.
83 struct mm_struct *loaded_mm;
85 #define LOADED_MM_SWITCHING ((struct mm_struct *)1UL)
87 /* Last user mm for optimizing IBPB */
89 struct mm_struct *last_user_mm;
90 unsigned long last_user_mm_spec;
97 * If set we changed the page tables in such a way that we
98 * needed an invalidation of all contexts (aka. PCIDs / ASIDs).
99 * This tells us to go invalidate all the non-loaded ctxs[]
100 * on the next context switch.
102 * The current ctx was kept up-to-date as it ran and does not
103 * need to be invalidated.
105 bool invalidate_other;
107 #ifdef CONFIG_ADDRESS_MASKING
111 * X86_CR3_LAM_U57/U48 shifted right by X86_CR3_LAM_U57_BIT or 0 if LAM
118 * Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
119 * the corresponding user PCID needs a flush next time we
120 * switch to it; see SWITCH_TO_USER_CR3.
122 unsigned short user_pcid_flush_mask;
125 * Access to this CR4 shadow and to H/W CR4 is protected by
126 * disabling interrupts when modifying either one.
131 * This is a list of all contexts that might exist in the TLB.
132 * There is one per ASID that we use, and the ASID (what the
133 * CPU calls PCID) is the index into ctxts.
135 * For each context, ctx_id indicates which mm the TLB's user
136 * entries came from. As an invariant, the TLB will never
137 * contain entries that are out-of-date as when that mm reached
138 * the tlb_gen in the list.
140 * To be clear, this means that it's legal for the TLB code to
141 * flush the TLB without updating tlb_gen. This can happen
142 * (for now, at least) due to paravirt remote flushes.
144 * NB: context 0 is a bit special, since it's also used by
145 * various bits of init code. This is fine -- code that
146 * isn't aware of PCID will end up harmlessly flushing
149 struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
151 DECLARE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate);
153 struct tlb_state_shared {
155 * We can be in one of several states:
157 * - Actively using an mm. Our CPU's bit will be set in
158 * mm_cpumask(loaded_mm) and is_lazy == false;
160 * - Not using a real mm. loaded_mm == &init_mm. Our CPU's bit
161 * will not be set in mm_cpumask(&init_mm) and is_lazy == false.
163 * - Lazily using a real mm. loaded_mm != &init_mm, our bit
164 * is set in mm_cpumask(loaded_mm), but is_lazy == true.
165 * We're heuristically guessing that the CR3 load we
166 * skipped more than makes up for the overhead added by
171 DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state_shared, cpu_tlbstate_shared);
173 bool nmi_uaccess_okay(void);
174 #define nmi_uaccess_okay nmi_uaccess_okay
176 /* Initialize cr4 shadow for this CPU. */
177 static inline void cr4_init_shadow(void)
179 this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
182 extern unsigned long mmu_cr4_features;
183 extern u32 *trampoline_cr4_features;
185 extern void initialize_tlbstate_and_flush(void);
190 * - flush_tlb_all() flushes all processes TLBs
191 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
192 * - flush_tlb_page(vma, vmaddr) flushes one page
193 * - flush_tlb_range(vma, start, end) flushes a range of pages
194 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
195 * - flush_tlb_multi(cpumask, info) flushes TLBs on multiple cpus
197 * ..but the i386 has somewhat limited tlb flushing capabilities,
198 * and page-granular flushes are available only on i486 and up.
200 struct flush_tlb_info {
202 * We support several kinds of flushes.
204 * - Fully flush a single mm. .mm will be set, .end will be
205 * TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
206 * which the IPI sender is trying to catch us up.
208 * - Partially flush a single mm. .mm will be set, .start and
209 * .end will indicate the range, and .new_tlb_gen will be set
210 * such that the changes between generation .new_tlb_gen-1 and
211 * .new_tlb_gen are entirely contained in the indicated range.
213 * - Fully flush all mms whose tlb_gens have been updated. .mm
214 * will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
217 struct mm_struct *mm;
221 unsigned int initiating_cpu;
226 void flush_tlb_local(void);
227 void flush_tlb_one_user(unsigned long addr);
228 void flush_tlb_one_kernel(unsigned long addr);
229 void flush_tlb_multi(const struct cpumask *cpumask,
230 const struct flush_tlb_info *info);
232 #ifdef CONFIG_PARAVIRT
233 #include <asm/paravirt.h>
236 #define flush_tlb_mm(mm) \
237 flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL, true)
239 #define flush_tlb_range(vma, start, end) \
240 flush_tlb_mm_range((vma)->vm_mm, start, end, \
241 ((vma)->vm_flags & VM_HUGETLB) \
242 ? huge_page_shift(hstate_vma(vma)) \
245 extern void flush_tlb_all(void);
246 extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
247 unsigned long end, unsigned int stride_shift,
249 extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
251 static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
253 flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, PAGE_SHIFT, false);
256 static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
259 * Bump the generation count. This also serves as a full barrier
260 * that synchronizes with switch_mm(): callers are required to order
261 * their read of mm_cpumask after their writes to the paging
264 return atomic64_inc_return(&mm->context.tlb_gen);
267 static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
268 struct mm_struct *mm)
271 cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
274 extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);
276 static inline bool pte_flags_need_flush(unsigned long oldflags,
277 unsigned long newflags,
281 * Flags that require a flush when cleared but not when they are set.
282 * Only include flags that would not trigger spurious page-faults.
283 * Non-present entries are not cached. Hardware would set the
284 * dirty/access bit if needed without a fault.
286 const pteval_t flush_on_clear = _PAGE_DIRTY | _PAGE_PRESENT |
288 const pteval_t software_flags = _PAGE_SOFTW1 | _PAGE_SOFTW2 |
289 _PAGE_SOFTW3 | _PAGE_SOFTW4;
290 const pteval_t flush_on_change = _PAGE_RW | _PAGE_USER | _PAGE_PWT |
291 _PAGE_PCD | _PAGE_PSE | _PAGE_GLOBAL | _PAGE_PAT |
292 _PAGE_PAT_LARGE | _PAGE_PKEY_BIT0 | _PAGE_PKEY_BIT1 |
293 _PAGE_PKEY_BIT2 | _PAGE_PKEY_BIT3 | _PAGE_NX;
294 unsigned long diff = oldflags ^ newflags;
296 BUILD_BUG_ON(flush_on_clear & software_flags);
297 BUILD_BUG_ON(flush_on_clear & flush_on_change);
298 BUILD_BUG_ON(flush_on_change & software_flags);
300 /* Ignore software flags */
301 diff &= ~software_flags;
304 diff &= ~_PAGE_ACCESSED;
307 * Did any of the 'flush_on_clear' flags was clleared set from between
308 * 'oldflags' and 'newflags'?
310 if (diff & oldflags & flush_on_clear)
313 /* Flush on modified flags. */
314 if (diff & flush_on_change)
317 /* Ensure there are no flags that were left behind */
318 if (IS_ENABLED(CONFIG_DEBUG_VM) &&
319 (diff & ~(flush_on_clear | software_flags | flush_on_change))) {
328 * pte_needs_flush() checks whether permissions were demoted and require a
329 * flush. It should only be used for userspace PTEs.
331 static inline bool pte_needs_flush(pte_t oldpte, pte_t newpte)
333 /* !PRESENT -> * ; no need for flush */
334 if (!(pte_flags(oldpte) & _PAGE_PRESENT))
337 /* PFN changed ; needs flush */
338 if (pte_pfn(oldpte) != pte_pfn(newpte))
342 * check PTE flags; ignore access-bit; see comment in
343 * ptep_clear_flush_young().
345 return pte_flags_need_flush(pte_flags(oldpte), pte_flags(newpte),
348 #define pte_needs_flush pte_needs_flush
351 * huge_pmd_needs_flush() checks whether permissions were demoted and require a
352 * flush. It should only be used for userspace huge PMDs.
354 static inline bool huge_pmd_needs_flush(pmd_t oldpmd, pmd_t newpmd)
356 /* !PRESENT -> * ; no need for flush */
357 if (!(pmd_flags(oldpmd) & _PAGE_PRESENT))
360 /* PFN changed ; needs flush */
361 if (pmd_pfn(oldpmd) != pmd_pfn(newpmd))
365 * check PMD flags; do not ignore access-bit; see
366 * pmdp_clear_flush_young().
368 return pte_flags_need_flush(pmd_flags(oldpmd), pmd_flags(newpmd),
371 #define huge_pmd_needs_flush huge_pmd_needs_flush
373 #ifdef CONFIG_ADDRESS_MASKING
374 static inline u64 tlbstate_lam_cr3_mask(void)
376 u64 lam = this_cpu_read(cpu_tlbstate.lam);
378 return lam << X86_CR3_LAM_U57_BIT;
381 static inline void set_tlbstate_lam_mode(struct mm_struct *mm)
383 this_cpu_write(cpu_tlbstate.lam,
384 mm->context.lam_cr3_mask >> X86_CR3_LAM_U57_BIT);
385 this_cpu_write(tlbstate_untag_mask, mm->context.untag_mask);
390 static inline u64 tlbstate_lam_cr3_mask(void)
395 static inline void set_tlbstate_lam_mode(struct mm_struct *mm)
401 static inline void __native_tlb_flush_global(unsigned long cr4)
403 native_write_cr4(cr4 ^ X86_CR4_PGE);
404 native_write_cr4(cr4);
406 #endif /* _ASM_X86_TLBFLUSH_H */