1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_SPECIAL_INSNS_H
3 #define _ASM_X86_SPECIAL_INSNS_H
9 #include <asm/processor-flags.h>
10 #include <linux/jump_label.h>
13 * Volatile isn't enough to prevent the compiler from reordering the
14 * read/write functions for the control registers and messing everything up.
15 * A memory clobber would solve the problem, but would prevent reordering of
16 * all loads stores around it, which can hurt performance. Solution is to
17 * use a variable and mimic reads and writes to it to enforce serialization
19 extern unsigned long __force_order;
21 void native_write_cr0(unsigned long val);
23 static inline unsigned long native_read_cr0(void)
26 asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
30 static inline unsigned long native_read_cr2(void)
33 asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
37 static inline void native_write_cr2(unsigned long val)
39 asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order));
42 static inline unsigned long __native_read_cr3(void)
45 asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
49 static inline void native_write_cr3(unsigned long val)
51 asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order));
54 static inline unsigned long native_read_cr4(void)
59 * This could fault if CR4 does not exist. Non-existent CR4
60 * is functionally equivalent to CR4 == 0. Keep it simple and pretend
61 * that CR4 == 0 on CPUs that don't have CR4.
63 asm volatile("1: mov %%cr4, %0\n"
66 : "=r" (val), "=m" (__force_order) : "0" (0));
68 /* CR4 always exists on x86_64. */
69 asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
74 void native_write_cr4(unsigned long val);
77 static inline unsigned long native_read_cr8(void)
80 asm volatile("movq %%cr8,%0" : "=r" (cr8));
84 static inline void native_write_cr8(unsigned long val)
86 asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
90 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
91 static inline u32 rdpkru(void)
97 * "rdpkru" instruction. Places PKRU contents in to EAX,
98 * clears EDX and requires that ecx=0.
100 asm volatile(".byte 0x0f,0x01,0xee\n\t"
101 : "=a" (pkru), "=d" (edx)
106 static inline void wrpkru(u32 pkru)
108 u32 ecx = 0, edx = 0;
111 * "wrpkru" instruction. Loads contents in EAX to PKRU,
112 * requires that ecx = edx = 0.
114 asm volatile(".byte 0x0f,0x01,0xef\n\t"
115 : : "a" (pkru), "c"(ecx), "d"(edx));
118 static inline void __write_pkru(u32 pkru)
121 * WRPKRU is relatively expensive compared to RDPKRU.
122 * Avoid WRPKRU when it would not change the value.
124 if (pkru == rdpkru())
131 static inline u32 rdpkru(void)
136 static inline void __write_pkru(u32 pkru)
141 static inline void native_wbinvd(void)
143 asm volatile("wbinvd": : :"memory");
146 extern asmlinkage void native_load_gs_index(unsigned);
148 static inline unsigned long __read_cr4(void)
150 return native_read_cr4();
153 #ifdef CONFIG_PARAVIRT_XXL
154 #include <asm/paravirt.h>
157 static inline unsigned long read_cr0(void)
159 return native_read_cr0();
162 static inline void write_cr0(unsigned long x)
167 static inline unsigned long read_cr2(void)
169 return native_read_cr2();
172 static inline void write_cr2(unsigned long x)
178 * Careful! CR3 contains more than just an address. You probably want
179 * read_cr3_pa() instead.
181 static inline unsigned long __read_cr3(void)
183 return __native_read_cr3();
186 static inline void write_cr3(unsigned long x)
191 static inline void __write_cr4(unsigned long x)
196 static inline void wbinvd(void)
203 static inline unsigned long read_cr8(void)
205 return native_read_cr8();
208 static inline void write_cr8(unsigned long x)
213 static inline void load_gs_index(unsigned selector)
215 native_load_gs_index(selector);
220 #endif /* CONFIG_PARAVIRT_XXL */
222 static inline void clflush(volatile void *__p)
224 asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
227 static inline void clflushopt(volatile void *__p)
229 alternative_io(".byte " __stringify(NOP_DS_PREFIX) "; clflush %P0",
230 ".byte 0x66; clflush %P0",
231 X86_FEATURE_CLFLUSHOPT,
232 "+m" (*(volatile char __force *)__p));
235 static inline void clwb(volatile void *__p)
237 volatile struct { char x[64]; } *p = __p;
239 asm volatile(ALTERNATIVE_2(
240 ".byte " __stringify(NOP_DS_PREFIX) "; clflush (%[pax])",
241 ".byte 0x66; clflush (%[pax])", /* clflushopt (%%rax) */
242 X86_FEATURE_CLFLUSHOPT,
243 ".byte 0x66, 0x0f, 0xae, 0x30", /* clwb (%%rax) */
249 #define nop() asm volatile ("nop")
252 #endif /* __KERNEL__ */
254 #endif /* _ASM_X86_SPECIAL_INSNS_H */