1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PROCESSOR_H
3 #define _ASM_X86_PROCESSOR_H
5 #include <asm/processor-flags.h>
7 /* Forward declaration, a strange C thing */
12 #include <asm/math_emu.h>
13 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <uapi/asm/sigcontext.h>
16 #include <asm/current.h>
17 #include <asm/cpufeatures.h>
19 #include <asm/pgtable_types.h>
20 #include <asm/percpu.h>
22 #include <asm/desc_defs.h>
24 #include <asm/special_insns.h>
25 #include <asm/fpu/types.h>
26 #include <asm/unwind_hints.h>
28 #include <linux/personality.h>
29 #include <linux/cache.h>
30 #include <linux/threads.h>
31 #include <linux/math64.h>
32 #include <linux/err.h>
33 #include <linux/irqflags.h>
34 #include <linux/mem_encrypt.h>
37 * We handle most unaligned accesses in hardware. On the other hand
38 * unaligned DMA can be quite expensive on some Nehalem processors.
40 * Based on this we disable the IP header alignment in network drivers.
42 #define NET_IP_ALIGN 0
47 * These alignment constraints are for performance in the vSMP case,
48 * but in the task_struct case we must also meet hardware imposed
49 * alignment requirements of the FPU state:
51 #ifdef CONFIG_X86_VSMP
52 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
53 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
55 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
56 # define ARCH_MIN_MMSTRUCT_ALIGN 0
64 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
65 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
66 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
67 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
68 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
69 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
70 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
73 * CPU type and hardware bug flags. Kept separately for each CPU.
74 * Members of this structure are referenced in head_32.S, so think twice
75 * before touching them. [mj]
79 __u8 x86; /* CPU family */
80 __u8 x86_vendor; /* CPU vendor */
84 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
89 /* CPUID returned core id bits: */
92 /* Max extended CPUID function supported: */
93 __u32 extended_cpuid_level;
94 /* Maximum supported CPUID level, -1=no CPUID: */
96 __u32 x86_capability[NCAPINTS + NBUGINTS];
97 char x86_vendor_id[16];
98 char x86_model_id[64];
99 /* in KB - valid for CPUS which support this call: */
100 unsigned int x86_cache_size;
101 int x86_cache_alignment; /* In bytes */
102 /* Cache QoS architectural values: */
103 int x86_cache_max_rmid; /* max index */
104 int x86_cache_occ_scale; /* scale to bytes */
106 unsigned long loops_per_jiffy;
107 /* cpuid returned max cores value: */
111 u16 x86_clflush_size;
112 /* number of cores as seen by the OS: */
114 /* Physical processor id: */
116 /* Logical processor id: */
120 /* Index into per_cpu list: */
123 /* Address space bits used by the cache internally */
125 unsigned initialized : 1;
126 } __randomize_layout;
129 u32 eax, ebx, ecx, edx;
132 enum cpuid_regs_idx {
139 #define X86_VENDOR_INTEL 0
140 #define X86_VENDOR_CYRIX 1
141 #define X86_VENDOR_AMD 2
142 #define X86_VENDOR_UMC 3
143 #define X86_VENDOR_CENTAUR 5
144 #define X86_VENDOR_TRANSMETA 7
145 #define X86_VENDOR_NSC 8
146 #define X86_VENDOR_HYGON 9
147 #define X86_VENDOR_NUM 10
149 #define X86_VENDOR_UNKNOWN 0xff
152 * capabilities of CPUs
154 extern struct cpuinfo_x86 boot_cpu_data;
155 extern struct cpuinfo_x86 new_cpu_data;
157 extern struct x86_hw_tss doublefault_tss;
158 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
159 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
162 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
163 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
165 #define cpu_info boot_cpu_data
166 #define cpu_data(cpu) boot_cpu_data
169 extern const struct seq_operations cpuinfo_op;
171 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
173 extern void cpu_detect(struct cpuinfo_x86 *c);
175 static inline unsigned long long l1tf_pfn_limit(void)
177 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
180 extern void early_cpu_init(void);
181 extern void identify_boot_cpu(void);
182 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
183 extern void print_cpu_info(struct cpuinfo_x86 *);
184 void print_cpu_msr(struct cpuinfo_x86 *);
187 extern int have_cpuid_p(void);
189 static inline int have_cpuid_p(void)
194 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
195 unsigned int *ecx, unsigned int *edx)
197 /* ecx is often an input as well as an output. */
203 : "0" (*eax), "2" (*ecx)
207 #define native_cpuid_reg(reg) \
208 static inline unsigned int native_cpuid_##reg(unsigned int op) \
210 unsigned int eax = op, ebx, ecx = 0, edx; \
212 native_cpuid(&eax, &ebx, &ecx, &edx); \
218 * Native CPUID functions returning a single datum.
220 native_cpuid_reg(eax)
221 native_cpuid_reg(ebx)
222 native_cpuid_reg(ecx)
223 native_cpuid_reg(edx)
226 * Friendlier CR3 helpers.
228 static inline unsigned long read_cr3_pa(void)
230 return __read_cr3() & CR3_ADDR_MASK;
233 static inline unsigned long native_read_cr3_pa(void)
235 return __native_read_cr3() & CR3_ADDR_MASK;
238 static inline void load_cr3(pgd_t *pgdir)
240 write_cr3(__sme_pa(pgdir));
244 * Note that while the legacy 'TSS' name comes from 'Task State Segment',
245 * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
246 * unrelated to the task-switch mechanism:
249 /* This is the TSS defined by the hardware. */
251 unsigned short back_link, __blh;
253 unsigned short ss0, __ss0h;
257 * We don't use ring 1, so ss1 is a convenient scratch space in
258 * the same cacheline as sp0. We use ss1 to cache the value in
259 * MSR_IA32_SYSENTER_CS. When we context switch
260 * MSR_IA32_SYSENTER_CS, we first check if the new value being
261 * written matches ss1, and, if it's not, then we wrmsr the new
262 * value and update ss1.
264 * The only reason we context switch MSR_IA32_SYSENTER_CS is
265 * that we set it to zero in vm86 tasks to avoid corrupting the
266 * stack if we were to go through the sysenter path from vm86
269 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
271 unsigned short __ss1h;
273 unsigned short ss2, __ss2h;
285 unsigned short es, __esh;
286 unsigned short cs, __csh;
287 unsigned short ss, __ssh;
288 unsigned short ds, __dsh;
289 unsigned short fs, __fsh;
290 unsigned short gs, __gsh;
291 unsigned short ldt, __ldth;
292 unsigned short trace;
293 unsigned short io_bitmap_base;
295 } __attribute__((packed));
302 * We store cpu_current_top_of_stack in sp1 so it's always accessible.
303 * Linux does not use ring 1, so sp1 is not otherwise needed.
308 * Since Linux does not use ring 2, the 'sp2' slot is unused by
309 * hardware. entry_SYSCALL_64 uses it as scratch space to stash
310 * the user RSP value.
321 } __attribute__((packed));
327 #define IO_BITMAP_BITS 65536
328 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
329 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
330 #define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss))
331 #define INVALID_IO_BITMAP_OFFSET 0x8000
334 unsigned long words[64];
337 struct entry_stack_page {
338 struct entry_stack stack;
339 } __aligned(PAGE_SIZE);
343 * The fixed hardware portion. This must not cross a page boundary
344 * at risk of violating the SDM's advice and potentially triggering
347 struct x86_hw_tss x86_tss;
350 * The extra 1 is there because the CPU will access an
351 * additional byte beyond the end of the IO permission
352 * bitmap. The extra byte must be all 1 bits, and must
353 * be within the limit.
355 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
356 } __aligned(PAGE_SIZE);
358 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
361 * sizeof(unsigned long) coming from an extra "long" at the end
364 * -1? seg base+limit should be pointing to the address of the
367 #define __KERNEL_TSS_LIMIT \
368 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)
370 /* Per CPU interrupt stacks */
372 char stack[IRQ_STACK_SIZE];
373 } __aligned(IRQ_STACK_SIZE);
375 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
378 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
380 /* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */
381 #define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1
385 struct fixed_percpu_data {
387 * GCC hardcodes the stack canary as %gs:40. Since the
388 * irq_stack is the object at %gs:0, we reserve the bottom
389 * 48 bytes of the irq stack for the canary.
392 unsigned long stack_canary;
395 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible;
396 DECLARE_INIT_PER_CPU(fixed_percpu_data);
398 static inline unsigned long cpu_kernelmode_gs_base(int cpu)
400 return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu);
403 DECLARE_PER_CPU(unsigned int, irq_count);
404 extern asmlinkage void ignore_sysret(void);
406 #if IS_ENABLED(CONFIG_KVM)
407 /* Save actual FS/GS selectors and bases to current->thread */
408 void save_fsgs_for_kvm(void);
411 #ifdef CONFIG_STACKPROTECTOR
413 * Make sure stack canary segment base is cached-aligned:
414 * "For Intel Atom processors, avoid non zero segment base address
415 * that is not aligned to cache line boundary at all cost."
416 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
418 struct stack_canary {
419 char __pad[20]; /* canary at %gs:20 */
420 unsigned long canary;
422 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
424 /* Per CPU softirq stack pointer */
425 DECLARE_PER_CPU(struct irq_stack *, softirq_stack_ptr);
428 extern unsigned int fpu_kernel_xstate_size;
429 extern unsigned int fpu_user_xstate_size;
437 struct thread_struct {
438 /* Cached TLS descriptors: */
439 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
445 unsigned long sysenter_cs;
449 unsigned short fsindex;
450 unsigned short gsindex;
454 unsigned long fsbase;
455 unsigned long gsbase;
458 * XXX: this could presumably be unsigned short. Alternatively,
459 * 32-bit kernels could be taught to use fsindex instead.
465 /* Save middle states of ptrace breakpoints */
466 struct perf_event *ptrace_bps[HBP_NUM];
467 /* Debug status used for traps, single steps, etc... */
468 unsigned long debugreg6;
469 /* Keep track of the exact dr7 value set by the user */
470 unsigned long ptrace_dr7;
473 unsigned long trap_nr;
474 unsigned long error_code;
476 /* Virtual 86 mode info */
479 /* IO permissions: */
480 unsigned long *io_bitmap_ptr;
482 /* Max allowed port in the bitmap, in bytes: */
483 unsigned io_bitmap_max;
485 mm_segment_t addr_limit;
487 unsigned int sig_on_uaccess_err:1;
488 unsigned int uaccess_err:1; /* uaccess failed */
490 /* Floating point and extended processor state */
493 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
498 /* Whitelist the FPU state from the task_struct for hardened usercopy. */
499 static inline void arch_thread_struct_whitelist(unsigned long *offset,
502 *offset = offsetof(struct thread_struct, fpu.state);
503 *size = fpu_kernel_xstate_size;
507 * Thread-synchronous status.
509 * This is different from the flags in that nobody else
510 * ever touches our thread-synchronous status, so we don't
511 * have to worry about atomic accesses.
513 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
516 * Set IOPL bits in EFLAGS from given mask
518 static inline void native_set_iopl_mask(unsigned mask)
523 asm volatile ("pushfl;"
530 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
535 native_load_sp0(unsigned long sp0)
537 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
540 static inline void native_swapgs(void)
543 asm volatile("swapgs" ::: "memory");
547 static inline unsigned long current_top_of_stack(void)
550 * We can't read directly from tss.sp0: sp0 on x86_32 is special in
551 * and around vm86 mode and sp0 on x86_64 is special because of the
554 return this_cpu_read_stable(cpu_current_top_of_stack);
557 static inline bool on_thread_stack(void)
559 return (unsigned long)(current_top_of_stack() -
560 current_stack_pointer) < THREAD_SIZE;
563 #ifdef CONFIG_PARAVIRT_XXL
564 #include <asm/paravirt.h>
566 #define __cpuid native_cpuid
568 static inline void load_sp0(unsigned long sp0)
570 native_load_sp0(sp0);
573 #define set_iopl_mask native_set_iopl_mask
574 #endif /* CONFIG_PARAVIRT_XXL */
576 /* Free all resources held by a thread. */
577 extern void release_thread(struct task_struct *);
579 unsigned long get_wchan(struct task_struct *p);
582 * Generic CPUID function
583 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
584 * resulting in stale register contents being returned.
586 static inline void cpuid(unsigned int op,
587 unsigned int *eax, unsigned int *ebx,
588 unsigned int *ecx, unsigned int *edx)
592 __cpuid(eax, ebx, ecx, edx);
595 /* Some CPUID calls want 'count' to be placed in ecx */
596 static inline void cpuid_count(unsigned int op, int count,
597 unsigned int *eax, unsigned int *ebx,
598 unsigned int *ecx, unsigned int *edx)
602 __cpuid(eax, ebx, ecx, edx);
606 * CPUID functions returning a single datum
608 static inline unsigned int cpuid_eax(unsigned int op)
610 unsigned int eax, ebx, ecx, edx;
612 cpuid(op, &eax, &ebx, &ecx, &edx);
617 static inline unsigned int cpuid_ebx(unsigned int op)
619 unsigned int eax, ebx, ecx, edx;
621 cpuid(op, &eax, &ebx, &ecx, &edx);
626 static inline unsigned int cpuid_ecx(unsigned int op)
628 unsigned int eax, ebx, ecx, edx;
630 cpuid(op, &eax, &ebx, &ecx, &edx);
635 static inline unsigned int cpuid_edx(unsigned int op)
637 unsigned int eax, ebx, ecx, edx;
639 cpuid(op, &eax, &ebx, &ecx, &edx);
644 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
645 static __always_inline void rep_nop(void)
647 asm volatile("rep; nop" ::: "memory");
650 static __always_inline void cpu_relax(void)
656 * This function forces the icache and prefetched instruction stream to
657 * catch up with reality in two very specific cases:
659 * a) Text was modified using one virtual address and is about to be executed
660 * from the same physical page at a different virtual address.
662 * b) Text was modified on a different CPU, may subsequently be
663 * executed on this CPU, and you want to make sure the new version
664 * gets executed. This generally means you're calling this in a IPI.
666 * If you're calling this for a different reason, you're probably doing
669 static inline void sync_core(void)
672 * There are quite a few ways to do this. IRET-to-self is nice
673 * because it works on every CPU, at any CPL (so it's compatible
674 * with paravirtualization), and it never exits to a hypervisor.
675 * The only down sides are that it's a bit slow (it seems to be
676 * a bit more than 2x slower than the fastest options) and that
677 * it unmasks NMIs. The "push %cs" is needed because, in
678 * paravirtual environments, __KERNEL_CS may not be a valid CS
679 * value when we do IRET directly.
681 * In case NMI unmasking or performance ever becomes a problem,
682 * the next best option appears to be MOV-to-CR2 and an
683 * unconditional jump. That sequence also works on all CPUs,
684 * but it will fault at CPL3 (i.e. Xen PV).
686 * CPUID is the conventional way, but it's nasty: it doesn't
687 * exist on some 486-like CPUs, and it usually exits to a
690 * Like all of Linux's memory ordering operations, this is a
691 * compiler barrier as well.
700 : ASM_CALL_CONSTRAINT : : "memory");
709 "addq $8, (%%rsp)\n\t"
717 : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory");
721 extern void select_idle_routine(const struct cpuinfo_x86 *c);
722 extern void amd_e400_c1e_apic_setup(void);
724 extern unsigned long boot_option_idle_override;
726 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
729 extern void enable_sep_cpu(void);
730 extern int sysenter_setup(void);
733 /* Defined in head.S */
734 extern struct desc_ptr early_gdt_descr;
736 extern void switch_to_new_gdt(int);
737 extern void load_direct_gdt(int);
738 extern void load_fixmap_gdt(int);
739 extern void load_percpu_segment(int);
740 extern void cpu_init(void);
742 static inline unsigned long get_debugctlmsr(void)
744 unsigned long debugctlmsr = 0;
746 #ifndef CONFIG_X86_DEBUGCTLMSR
747 if (boot_cpu_data.x86 < 6)
750 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
755 static inline void update_debugctlmsr(unsigned long debugctlmsr)
757 #ifndef CONFIG_X86_DEBUGCTLMSR
758 if (boot_cpu_data.x86 < 6)
761 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
764 extern void set_task_blockstep(struct task_struct *task, bool on);
766 /* Boot loader type from the setup header: */
767 extern int bootloader_type;
768 extern int bootloader_version;
770 extern char ignore_fpu_irq;
772 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
773 #define ARCH_HAS_PREFETCHW
774 #define ARCH_HAS_SPINLOCK_PREFETCH
777 # define BASE_PREFETCH ""
778 # define ARCH_HAS_PREFETCH
780 # define BASE_PREFETCH "prefetcht0 %P1"
784 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
786 * It's not worth to care about 3dnow prefetches for the K6
787 * because they are microcoded there and very slow.
789 static inline void prefetch(const void *x)
791 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
793 "m" (*(const char *)x));
797 * 3dnow prefetch to get an exclusive cache line.
798 * Useful for spinlocks to avoid one state transition in the
799 * cache coherency protocol:
801 static inline void prefetchw(const void *x)
803 alternative_input(BASE_PREFETCH, "prefetchw %P1",
804 X86_FEATURE_3DNOWPREFETCH,
805 "m" (*(const char *)x));
808 static inline void spin_lock_prefetch(const void *x)
813 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
814 TOP_OF_KERNEL_STACK_PADDING)
816 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
818 #define task_pt_regs(task) \
820 unsigned long __ptr = (unsigned long)task_stack_page(task); \
821 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
822 ((struct pt_regs *)__ptr) - 1; \
827 * User space process size: 3GB (default).
829 #define IA32_PAGE_OFFSET PAGE_OFFSET
830 #define TASK_SIZE PAGE_OFFSET
831 #define TASK_SIZE_LOW TASK_SIZE
832 #define TASK_SIZE_MAX TASK_SIZE
833 #define DEFAULT_MAP_WINDOW TASK_SIZE
834 #define STACK_TOP TASK_SIZE
835 #define STACK_TOP_MAX STACK_TOP
837 #define INIT_THREAD { \
838 .sp0 = TOP_OF_INIT_STACK, \
839 .sysenter_cs = __KERNEL_CS, \
840 .io_bitmap_ptr = NULL, \
841 .addr_limit = KERNEL_DS, \
844 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
848 * User space process size. This is the first address outside the user range.
849 * There are a few constraints that determine this:
851 * On Intel CPUs, if a SYSCALL instruction is at the highest canonical
852 * address, then that syscall will enter the kernel with a
853 * non-canonical return address, and SYSRET will explode dangerously.
854 * We avoid this particular problem by preventing anything executable
855 * from being mapped at the maximum canonical address.
857 * On AMD CPUs in the Ryzen family, there's a nasty bug in which the
858 * CPUs malfunction if they execute code from the highest canonical page.
859 * They'll speculate right off the end of the canonical space, and
860 * bad things happen. This is worked around in the same way as the
863 * With page table isolation enabled, we map the LDT in ... [stay tuned]
865 #define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE)
867 #define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE)
869 /* This decides where the kernel will search for a free chunk of vm
870 * space during mmap's.
872 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
873 0xc0000000 : 0xFFFFe000)
875 #define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \
876 IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW)
877 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
878 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
879 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
880 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
882 #define STACK_TOP TASK_SIZE_LOW
883 #define STACK_TOP_MAX TASK_SIZE_MAX
885 #define INIT_THREAD { \
886 .addr_limit = KERNEL_DS, \
889 extern unsigned long KSTK_ESP(struct task_struct *task);
891 #endif /* CONFIG_X86_64 */
893 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
894 unsigned long new_sp);
897 * This decides where the kernel will search for a free chunk of vm
898 * space during mmap's.
900 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
901 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
903 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
905 /* Get/set a process' ability to use the timestamp counter instruction */
906 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
907 #define SET_TSC_CTL(val) set_tsc_mode((val))
909 extern int get_tsc_mode(unsigned long adr);
910 extern int set_tsc_mode(unsigned int val);
912 DECLARE_PER_CPU(u64, msr_misc_features_shadow);
914 /* Register/unregister a process' MPX related resource */
915 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
916 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
918 #ifdef CONFIG_X86_INTEL_MPX
919 extern int mpx_enable_management(void);
920 extern int mpx_disable_management(void);
922 static inline int mpx_enable_management(void)
926 static inline int mpx_disable_management(void)
930 #endif /* CONFIG_X86_INTEL_MPX */
932 #ifdef CONFIG_CPU_SUP_AMD
933 extern u16 amd_get_nb_id(int cpu);
934 extern u32 amd_get_nodes_per_socket(void);
936 static inline u16 amd_get_nb_id(int cpu) { return 0; }
937 static inline u32 amd_get_nodes_per_socket(void) { return 0; }
940 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
942 uint32_t base, eax, signature[3];
944 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
945 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
947 if (!memcmp(sig, signature, 12) &&
948 (leaves == 0 || ((eax - base) >= leaves)))
955 extern unsigned long arch_align_stack(unsigned long sp);
956 void free_init_pages(const char *what, unsigned long begin, unsigned long end);
957 extern void free_kernel_image_pages(void *begin, void *end);
959 void default_idle(void);
961 bool xen_set_default_idle(void);
963 #define xen_set_default_idle 0
966 void stop_this_cpu(void *dummy);
967 void df_debug(struct pt_regs *regs, long error_code);
968 void microcode_check(void);
970 enum l1tf_mitigations {
972 L1TF_MITIGATION_FLUSH_NOWARN,
973 L1TF_MITIGATION_FLUSH,
974 L1TF_MITIGATION_FLUSH_NOSMT,
975 L1TF_MITIGATION_FULL,
976 L1TF_MITIGATION_FULL_FORCE
979 extern enum l1tf_mitigations l1tf_mitigation;
981 enum mds_mitigations {
984 MDS_MITIGATION_VMWERV,
987 #endif /* _ASM_X86_PROCESSOR_H */