1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PROCESSOR_H
3 #define _ASM_X86_PROCESSOR_H
5 #include <asm/processor-flags.h>
7 /* Forward declaration, a strange C thing */
12 #include <asm/math_emu.h>
13 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <uapi/asm/sigcontext.h>
16 #include <asm/current.h>
17 #include <asm/cpufeatures.h>
19 #include <asm/pgtable_types.h>
20 #include <asm/percpu.h>
22 #include <asm/desc_defs.h>
24 #include <asm/special_insns.h>
25 #include <asm/fpu/types.h>
26 #include <asm/unwind_hints.h>
28 #include <linux/personality.h>
29 #include <linux/cache.h>
30 #include <linux/threads.h>
31 #include <linux/math64.h>
32 #include <linux/err.h>
33 #include <linux/irqflags.h>
34 #include <linux/mem_encrypt.h>
37 * We handle most unaligned accesses in hardware. On the other hand
38 * unaligned DMA can be quite expensive on some Nehalem processors.
40 * Based on this we disable the IP header alignment in network drivers.
42 #define NET_IP_ALIGN 0
47 * These alignment constraints are for performance in the vSMP case,
48 * but in the task_struct case we must also meet hardware imposed
49 * alignment requirements of the FPU state:
51 #ifdef CONFIG_X86_VSMP
52 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
53 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
55 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
56 # define ARCH_MIN_MMSTRUCT_ALIGN 0
64 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
65 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
66 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
67 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
68 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
69 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
70 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
73 * CPU type and hardware bug flags. Kept separately for each CPU.
74 * Members of this structure are referenced in head_32.S, so think twice
75 * before touching them. [mj]
79 __u8 x86; /* CPU family */
80 __u8 x86_vendor; /* CPU vendor */
84 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
89 /* CPUID returned core id bits: */
92 /* Max extended CPUID function supported: */
93 __u32 extended_cpuid_level;
94 /* Maximum supported CPUID level, -1=no CPUID: */
96 __u32 x86_capability[NCAPINTS + NBUGINTS];
97 char x86_vendor_id[16];
98 char x86_model_id[64];
99 /* in KB - valid for CPUS which support this call: */
100 unsigned int x86_cache_size;
101 int x86_cache_alignment; /* In bytes */
102 /* Cache QoS architectural values: */
103 int x86_cache_max_rmid; /* max index */
104 int x86_cache_occ_scale; /* scale to bytes */
106 unsigned long loops_per_jiffy;
107 /* cpuid returned max cores value: */
111 u16 x86_clflush_size;
112 /* number of cores as seen by the OS: */
114 /* Physical processor id: */
116 /* Logical processor id: */
120 /* Index into per_cpu list: */
123 /* Address space bits used by the cache internally */
125 unsigned initialized : 1;
126 } __randomize_layout;
129 u32 eax, ebx, ecx, edx;
132 enum cpuid_regs_idx {
139 #define X86_VENDOR_INTEL 0
140 #define X86_VENDOR_CYRIX 1
141 #define X86_VENDOR_AMD 2
142 #define X86_VENDOR_UMC 3
143 #define X86_VENDOR_CENTAUR 5
144 #define X86_VENDOR_TRANSMETA 7
145 #define X86_VENDOR_NSC 8
146 #define X86_VENDOR_HYGON 9
147 #define X86_VENDOR_ZHAOXIN 10
148 #define X86_VENDOR_NUM 11
150 #define X86_VENDOR_UNKNOWN 0xff
153 * capabilities of CPUs
155 extern struct cpuinfo_x86 boot_cpu_data;
156 extern struct cpuinfo_x86 new_cpu_data;
158 extern struct x86_hw_tss doublefault_tss;
159 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
160 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
163 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
164 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
166 #define cpu_info boot_cpu_data
167 #define cpu_data(cpu) boot_cpu_data
170 extern const struct seq_operations cpuinfo_op;
172 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
174 extern void cpu_detect(struct cpuinfo_x86 *c);
176 static inline unsigned long long l1tf_pfn_limit(void)
178 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
181 extern void early_cpu_init(void);
182 extern void identify_boot_cpu(void);
183 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
184 extern void print_cpu_info(struct cpuinfo_x86 *);
185 void print_cpu_msr(struct cpuinfo_x86 *);
188 extern int have_cpuid_p(void);
190 static inline int have_cpuid_p(void)
195 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
196 unsigned int *ecx, unsigned int *edx)
198 /* ecx is often an input as well as an output. */
204 : "0" (*eax), "2" (*ecx)
208 #define native_cpuid_reg(reg) \
209 static inline unsigned int native_cpuid_##reg(unsigned int op) \
211 unsigned int eax = op, ebx, ecx = 0, edx; \
213 native_cpuid(&eax, &ebx, &ecx, &edx); \
219 * Native CPUID functions returning a single datum.
221 native_cpuid_reg(eax)
222 native_cpuid_reg(ebx)
223 native_cpuid_reg(ecx)
224 native_cpuid_reg(edx)
227 * Friendlier CR3 helpers.
229 static inline unsigned long read_cr3_pa(void)
231 return __read_cr3() & CR3_ADDR_MASK;
234 static inline unsigned long native_read_cr3_pa(void)
236 return __native_read_cr3() & CR3_ADDR_MASK;
239 static inline void load_cr3(pgd_t *pgdir)
241 write_cr3(__sme_pa(pgdir));
245 * Note that while the legacy 'TSS' name comes from 'Task State Segment',
246 * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
247 * unrelated to the task-switch mechanism:
250 /* This is the TSS defined by the hardware. */
252 unsigned short back_link, __blh;
254 unsigned short ss0, __ss0h;
258 * We don't use ring 1, so ss1 is a convenient scratch space in
259 * the same cacheline as sp0. We use ss1 to cache the value in
260 * MSR_IA32_SYSENTER_CS. When we context switch
261 * MSR_IA32_SYSENTER_CS, we first check if the new value being
262 * written matches ss1, and, if it's not, then we wrmsr the new
263 * value and update ss1.
265 * The only reason we context switch MSR_IA32_SYSENTER_CS is
266 * that we set it to zero in vm86 tasks to avoid corrupting the
267 * stack if we were to go through the sysenter path from vm86
270 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
272 unsigned short __ss1h;
274 unsigned short ss2, __ss2h;
286 unsigned short es, __esh;
287 unsigned short cs, __csh;
288 unsigned short ss, __ssh;
289 unsigned short ds, __dsh;
290 unsigned short fs, __fsh;
291 unsigned short gs, __gsh;
292 unsigned short ldt, __ldth;
293 unsigned short trace;
294 unsigned short io_bitmap_base;
296 } __attribute__((packed));
303 * We store cpu_current_top_of_stack in sp1 so it's always accessible.
304 * Linux does not use ring 1, so sp1 is not otherwise needed.
309 * Since Linux does not use ring 2, the 'sp2' slot is unused by
310 * hardware. entry_SYSCALL_64 uses it as scratch space to stash
311 * the user RSP value.
322 } __attribute__((packed));
328 #define IO_BITMAP_BITS 65536
329 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
330 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
331 #define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss))
332 #define INVALID_IO_BITMAP_OFFSET 0x8000
335 unsigned long words[64];
338 struct entry_stack_page {
339 struct entry_stack stack;
340 } __aligned(PAGE_SIZE);
344 * The fixed hardware portion. This must not cross a page boundary
345 * at risk of violating the SDM's advice and potentially triggering
348 struct x86_hw_tss x86_tss;
351 * The extra 1 is there because the CPU will access an
352 * additional byte beyond the end of the IO permission
353 * bitmap. The extra byte must be all 1 bits, and must
354 * be within the limit.
356 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
357 } __aligned(PAGE_SIZE);
359 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
362 * sizeof(unsigned long) coming from an extra "long" at the end
365 * -1? seg base+limit should be pointing to the address of the
368 #define __KERNEL_TSS_LIMIT \
369 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)
371 /* Per CPU interrupt stacks */
373 char stack[IRQ_STACK_SIZE];
374 } __aligned(IRQ_STACK_SIZE);
376 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
379 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
381 /* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */
382 #define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1
386 struct fixed_percpu_data {
388 * GCC hardcodes the stack canary as %gs:40. Since the
389 * irq_stack is the object at %gs:0, we reserve the bottom
390 * 48 bytes of the irq stack for the canary.
393 unsigned long stack_canary;
396 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible;
397 DECLARE_INIT_PER_CPU(fixed_percpu_data);
399 static inline unsigned long cpu_kernelmode_gs_base(int cpu)
401 return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu);
404 DECLARE_PER_CPU(unsigned int, irq_count);
405 extern asmlinkage void ignore_sysret(void);
407 #if IS_ENABLED(CONFIG_KVM)
408 /* Save actual FS/GS selectors and bases to current->thread */
409 void save_fsgs_for_kvm(void);
412 #ifdef CONFIG_STACKPROTECTOR
414 * Make sure stack canary segment base is cached-aligned:
415 * "For Intel Atom processors, avoid non zero segment base address
416 * that is not aligned to cache line boundary at all cost."
417 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
419 struct stack_canary {
420 char __pad[20]; /* canary at %gs:20 */
421 unsigned long canary;
423 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
425 /* Per CPU softirq stack pointer */
426 DECLARE_PER_CPU(struct irq_stack *, softirq_stack_ptr);
429 extern unsigned int fpu_kernel_xstate_size;
430 extern unsigned int fpu_user_xstate_size;
438 struct thread_struct {
439 /* Cached TLS descriptors: */
440 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
446 unsigned long sysenter_cs;
450 unsigned short fsindex;
451 unsigned short gsindex;
455 unsigned long fsbase;
456 unsigned long gsbase;
459 * XXX: this could presumably be unsigned short. Alternatively,
460 * 32-bit kernels could be taught to use fsindex instead.
466 /* Save middle states of ptrace breakpoints */
467 struct perf_event *ptrace_bps[HBP_NUM];
468 /* Debug status used for traps, single steps, etc... */
469 unsigned long debugreg6;
470 /* Keep track of the exact dr7 value set by the user */
471 unsigned long ptrace_dr7;
474 unsigned long trap_nr;
475 unsigned long error_code;
477 /* Virtual 86 mode info */
480 /* IO permissions: */
481 unsigned long *io_bitmap_ptr;
483 /* Max allowed port in the bitmap, in bytes: */
484 unsigned io_bitmap_max;
486 mm_segment_t addr_limit;
488 unsigned int sig_on_uaccess_err:1;
489 unsigned int uaccess_err:1; /* uaccess failed */
491 /* Floating point and extended processor state */
494 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
499 /* Whitelist the FPU state from the task_struct for hardened usercopy. */
500 static inline void arch_thread_struct_whitelist(unsigned long *offset,
503 *offset = offsetof(struct thread_struct, fpu.state);
504 *size = fpu_kernel_xstate_size;
508 * Thread-synchronous status.
510 * This is different from the flags in that nobody else
511 * ever touches our thread-synchronous status, so we don't
512 * have to worry about atomic accesses.
514 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
517 * Set IOPL bits in EFLAGS from given mask
519 static inline void native_set_iopl_mask(unsigned mask)
524 asm volatile ("pushfl;"
531 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
536 native_load_sp0(unsigned long sp0)
538 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
541 static inline void native_swapgs(void)
544 asm volatile("swapgs" ::: "memory");
548 static inline unsigned long current_top_of_stack(void)
551 * We can't read directly from tss.sp0: sp0 on x86_32 is special in
552 * and around vm86 mode and sp0 on x86_64 is special because of the
555 return this_cpu_read_stable(cpu_current_top_of_stack);
558 static inline bool on_thread_stack(void)
560 return (unsigned long)(current_top_of_stack() -
561 current_stack_pointer) < THREAD_SIZE;
564 #ifdef CONFIG_PARAVIRT_XXL
565 #include <asm/paravirt.h>
567 #define __cpuid native_cpuid
569 static inline void load_sp0(unsigned long sp0)
571 native_load_sp0(sp0);
574 #define set_iopl_mask native_set_iopl_mask
575 #endif /* CONFIG_PARAVIRT_XXL */
577 /* Free all resources held by a thread. */
578 extern void release_thread(struct task_struct *);
580 unsigned long get_wchan(struct task_struct *p);
583 * Generic CPUID function
584 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
585 * resulting in stale register contents being returned.
587 static inline void cpuid(unsigned int op,
588 unsigned int *eax, unsigned int *ebx,
589 unsigned int *ecx, unsigned int *edx)
593 __cpuid(eax, ebx, ecx, edx);
596 /* Some CPUID calls want 'count' to be placed in ecx */
597 static inline void cpuid_count(unsigned int op, int count,
598 unsigned int *eax, unsigned int *ebx,
599 unsigned int *ecx, unsigned int *edx)
603 __cpuid(eax, ebx, ecx, edx);
607 * CPUID functions returning a single datum
609 static inline unsigned int cpuid_eax(unsigned int op)
611 unsigned int eax, ebx, ecx, edx;
613 cpuid(op, &eax, &ebx, &ecx, &edx);
618 static inline unsigned int cpuid_ebx(unsigned int op)
620 unsigned int eax, ebx, ecx, edx;
622 cpuid(op, &eax, &ebx, &ecx, &edx);
627 static inline unsigned int cpuid_ecx(unsigned int op)
629 unsigned int eax, ebx, ecx, edx;
631 cpuid(op, &eax, &ebx, &ecx, &edx);
636 static inline unsigned int cpuid_edx(unsigned int op)
638 unsigned int eax, ebx, ecx, edx;
640 cpuid(op, &eax, &ebx, &ecx, &edx);
645 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
646 static __always_inline void rep_nop(void)
648 asm volatile("rep; nop" ::: "memory");
651 static __always_inline void cpu_relax(void)
657 * This function forces the icache and prefetched instruction stream to
658 * catch up with reality in two very specific cases:
660 * a) Text was modified using one virtual address and is about to be executed
661 * from the same physical page at a different virtual address.
663 * b) Text was modified on a different CPU, may subsequently be
664 * executed on this CPU, and you want to make sure the new version
665 * gets executed. This generally means you're calling this in a IPI.
667 * If you're calling this for a different reason, you're probably doing
670 static inline void sync_core(void)
673 * There are quite a few ways to do this. IRET-to-self is nice
674 * because it works on every CPU, at any CPL (so it's compatible
675 * with paravirtualization), and it never exits to a hypervisor.
676 * The only down sides are that it's a bit slow (it seems to be
677 * a bit more than 2x slower than the fastest options) and that
678 * it unmasks NMIs. The "push %cs" is needed because, in
679 * paravirtual environments, __KERNEL_CS may not be a valid CS
680 * value when we do IRET directly.
682 * In case NMI unmasking or performance ever becomes a problem,
683 * the next best option appears to be MOV-to-CR2 and an
684 * unconditional jump. That sequence also works on all CPUs,
685 * but it will fault at CPL3 (i.e. Xen PV).
687 * CPUID is the conventional way, but it's nasty: it doesn't
688 * exist on some 486-like CPUs, and it usually exits to a
691 * Like all of Linux's memory ordering operations, this is a
692 * compiler barrier as well.
701 : ASM_CALL_CONSTRAINT : : "memory");
710 "addq $8, (%%rsp)\n\t"
718 : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory");
722 extern void select_idle_routine(const struct cpuinfo_x86 *c);
723 extern void amd_e400_c1e_apic_setup(void);
725 extern unsigned long boot_option_idle_override;
727 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
730 extern void enable_sep_cpu(void);
731 extern int sysenter_setup(void);
734 /* Defined in head.S */
735 extern struct desc_ptr early_gdt_descr;
737 extern void switch_to_new_gdt(int);
738 extern void load_direct_gdt(int);
739 extern void load_fixmap_gdt(int);
740 extern void load_percpu_segment(int);
741 extern void cpu_init(void);
743 static inline unsigned long get_debugctlmsr(void)
745 unsigned long debugctlmsr = 0;
747 #ifndef CONFIG_X86_DEBUGCTLMSR
748 if (boot_cpu_data.x86 < 6)
751 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
756 static inline void update_debugctlmsr(unsigned long debugctlmsr)
758 #ifndef CONFIG_X86_DEBUGCTLMSR
759 if (boot_cpu_data.x86 < 6)
762 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
765 extern void set_task_blockstep(struct task_struct *task, bool on);
767 /* Boot loader type from the setup header: */
768 extern int bootloader_type;
769 extern int bootloader_version;
771 extern char ignore_fpu_irq;
773 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
774 #define ARCH_HAS_PREFETCHW
775 #define ARCH_HAS_SPINLOCK_PREFETCH
778 # define BASE_PREFETCH ""
779 # define ARCH_HAS_PREFETCH
781 # define BASE_PREFETCH "prefetcht0 %P1"
785 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
787 * It's not worth to care about 3dnow prefetches for the K6
788 * because they are microcoded there and very slow.
790 static inline void prefetch(const void *x)
792 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
794 "m" (*(const char *)x));
798 * 3dnow prefetch to get an exclusive cache line.
799 * Useful for spinlocks to avoid one state transition in the
800 * cache coherency protocol:
802 static inline void prefetchw(const void *x)
804 alternative_input(BASE_PREFETCH, "prefetchw %P1",
805 X86_FEATURE_3DNOWPREFETCH,
806 "m" (*(const char *)x));
809 static inline void spin_lock_prefetch(const void *x)
814 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
815 TOP_OF_KERNEL_STACK_PADDING)
817 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
819 #define task_pt_regs(task) \
821 unsigned long __ptr = (unsigned long)task_stack_page(task); \
822 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
823 ((struct pt_regs *)__ptr) - 1; \
828 * User space process size: 3GB (default).
830 #define IA32_PAGE_OFFSET PAGE_OFFSET
831 #define TASK_SIZE PAGE_OFFSET
832 #define TASK_SIZE_LOW TASK_SIZE
833 #define TASK_SIZE_MAX TASK_SIZE
834 #define DEFAULT_MAP_WINDOW TASK_SIZE
835 #define STACK_TOP TASK_SIZE
836 #define STACK_TOP_MAX STACK_TOP
838 #define INIT_THREAD { \
839 .sp0 = TOP_OF_INIT_STACK, \
840 .sysenter_cs = __KERNEL_CS, \
841 .io_bitmap_ptr = NULL, \
842 .addr_limit = KERNEL_DS, \
845 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
849 * User space process size. This is the first address outside the user range.
850 * There are a few constraints that determine this:
852 * On Intel CPUs, if a SYSCALL instruction is at the highest canonical
853 * address, then that syscall will enter the kernel with a
854 * non-canonical return address, and SYSRET will explode dangerously.
855 * We avoid this particular problem by preventing anything executable
856 * from being mapped at the maximum canonical address.
858 * On AMD CPUs in the Ryzen family, there's a nasty bug in which the
859 * CPUs malfunction if they execute code from the highest canonical page.
860 * They'll speculate right off the end of the canonical space, and
861 * bad things happen. This is worked around in the same way as the
864 * With page table isolation enabled, we map the LDT in ... [stay tuned]
866 #define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE)
868 #define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE)
870 /* This decides where the kernel will search for a free chunk of vm
871 * space during mmap's.
873 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
874 0xc0000000 : 0xFFFFe000)
876 #define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \
877 IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW)
878 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
879 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
880 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
881 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
883 #define STACK_TOP TASK_SIZE_LOW
884 #define STACK_TOP_MAX TASK_SIZE_MAX
886 #define INIT_THREAD { \
887 .addr_limit = KERNEL_DS, \
890 extern unsigned long KSTK_ESP(struct task_struct *task);
892 #endif /* CONFIG_X86_64 */
894 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
895 unsigned long new_sp);
898 * This decides where the kernel will search for a free chunk of vm
899 * space during mmap's.
901 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
902 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
904 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
906 /* Get/set a process' ability to use the timestamp counter instruction */
907 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
908 #define SET_TSC_CTL(val) set_tsc_mode((val))
910 extern int get_tsc_mode(unsigned long adr);
911 extern int set_tsc_mode(unsigned int val);
913 DECLARE_PER_CPU(u64, msr_misc_features_shadow);
915 /* Register/unregister a process' MPX related resource */
916 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
917 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
919 #ifdef CONFIG_X86_INTEL_MPX
920 extern int mpx_enable_management(void);
921 extern int mpx_disable_management(void);
923 static inline int mpx_enable_management(void)
927 static inline int mpx_disable_management(void)
931 #endif /* CONFIG_X86_INTEL_MPX */
933 #ifdef CONFIG_CPU_SUP_AMD
934 extern u16 amd_get_nb_id(int cpu);
935 extern u32 amd_get_nodes_per_socket(void);
937 static inline u16 amd_get_nb_id(int cpu) { return 0; }
938 static inline u32 amd_get_nodes_per_socket(void) { return 0; }
941 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
943 uint32_t base, eax, signature[3];
945 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
946 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
948 if (!memcmp(sig, signature, 12) &&
949 (leaves == 0 || ((eax - base) >= leaves)))
956 extern unsigned long arch_align_stack(unsigned long sp);
957 void free_init_pages(const char *what, unsigned long begin, unsigned long end);
958 extern void free_kernel_image_pages(void *begin, void *end);
960 void default_idle(void);
962 bool xen_set_default_idle(void);
964 #define xen_set_default_idle 0
967 void stop_this_cpu(void *dummy);
968 void df_debug(struct pt_regs *regs, long error_code);
969 void microcode_check(void);
971 enum l1tf_mitigations {
973 L1TF_MITIGATION_FLUSH_NOWARN,
974 L1TF_MITIGATION_FLUSH,
975 L1TF_MITIGATION_FLUSH_NOSMT,
976 L1TF_MITIGATION_FULL,
977 L1TF_MITIGATION_FULL_FORCE
980 extern enum l1tf_mitigations l1tf_mitigation;
982 enum mds_mitigations {
985 MDS_MITIGATION_VMWERV,
988 #endif /* _ASM_X86_PROCESSOR_H */