1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <uapi/asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeatures.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
23 #include <asm/special_insns.h>
24 #include <asm/fpu/types.h>
26 #include <linux/personality.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/err.h>
31 #include <linux/irqflags.h>
32 #include <linux/mem_encrypt.h>
35 * We handle most unaligned accesses in hardware. On the other hand
36 * unaligned DMA can be quite expensive on some Nehalem processors.
38 * Based on this we disable the IP header alignment in network drivers.
40 #define NET_IP_ALIGN 0
44 * Default implementation of macro that returns current
45 * instruction pointer ("program counter").
47 static inline void *current_text_addr(void)
51 asm volatile("mov $1f, %0; 1:":"=r" (pc));
57 * These alignment constraints are for performance in the vSMP case,
58 * but in the task_struct case we must also meet hardware imposed
59 * alignment requirements of the FPU state:
61 #ifdef CONFIG_X86_VSMP
62 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
63 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
65 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
66 # define ARCH_MIN_MMSTRUCT_ALIGN 0
74 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
75 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
76 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
77 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
78 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
79 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
80 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
83 * CPU type and hardware bug flags. Kept separately for each CPU.
84 * Members of this structure are referenced in head_32.S, so think twice
85 * before touching them. [mj]
89 __u8 x86; /* CPU family */
90 __u8 x86_vendor; /* CPU vendor */
94 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
99 /* CPUID returned core id bits: */
100 __u8 x86_coreid_bits;
102 /* Max extended CPUID function supported: */
103 __u32 extended_cpuid_level;
104 /* Maximum supported CPUID level, -1=no CPUID: */
106 __u32 x86_capability[NCAPINTS + NBUGINTS];
107 char x86_vendor_id[16];
108 char x86_model_id[64];
109 /* in KB - valid for CPUS which support this call: */
111 int x86_cache_alignment; /* In bytes */
112 /* Cache QoS architectural values: */
113 int x86_cache_max_rmid; /* max index */
114 int x86_cache_occ_scale; /* scale to bytes */
116 unsigned long loops_per_jiffy;
117 /* cpuid returned max cores value: */
121 u16 x86_clflush_size;
122 /* number of cores as seen by the OS: */
124 /* Physical processor id: */
126 /* Logical processor id: */
130 /* Index into per_cpu list: */
136 u32 eax, ebx, ecx, edx;
139 enum cpuid_regs_idx {
146 #define X86_VENDOR_INTEL 0
147 #define X86_VENDOR_CYRIX 1
148 #define X86_VENDOR_AMD 2
149 #define X86_VENDOR_UMC 3
150 #define X86_VENDOR_CENTAUR 5
151 #define X86_VENDOR_TRANSMETA 7
152 #define X86_VENDOR_NSC 8
153 #define X86_VENDOR_NUM 9
155 #define X86_VENDOR_UNKNOWN 0xff
158 * capabilities of CPUs
160 extern struct cpuinfo_x86 boot_cpu_data;
161 extern struct cpuinfo_x86 new_cpu_data;
163 extern struct tss_struct doublefault_tss;
164 extern __u32 cpu_caps_cleared[NCAPINTS];
165 extern __u32 cpu_caps_set[NCAPINTS];
168 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
169 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
171 #define cpu_info boot_cpu_data
172 #define cpu_data(cpu) boot_cpu_data
175 extern const struct seq_operations cpuinfo_op;
177 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
179 extern void cpu_detect(struct cpuinfo_x86 *c);
181 extern void early_cpu_init(void);
182 extern void identify_boot_cpu(void);
183 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
184 extern void print_cpu_info(struct cpuinfo_x86 *);
185 void print_cpu_msr(struct cpuinfo_x86 *);
186 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
187 extern u32 get_scattered_cpuid_leaf(unsigned int level,
188 unsigned int sub_leaf,
189 enum cpuid_regs_idx reg);
190 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
191 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
193 extern void detect_extended_topology(struct cpuinfo_x86 *c);
194 extern void detect_ht(struct cpuinfo_x86 *c);
197 extern int have_cpuid_p(void);
199 static inline int have_cpuid_p(void)
204 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
205 unsigned int *ecx, unsigned int *edx)
207 /* ecx is often an input as well as an output. */
213 : "0" (*eax), "2" (*ecx)
217 #define native_cpuid_reg(reg) \
218 static inline unsigned int native_cpuid_##reg(unsigned int op) \
220 unsigned int eax = op, ebx, ecx = 0, edx; \
222 native_cpuid(&eax, &ebx, &ecx, &edx); \
228 * Native CPUID functions returning a single datum.
230 native_cpuid_reg(eax)
231 native_cpuid_reg(ebx)
232 native_cpuid_reg(ecx)
233 native_cpuid_reg(edx)
236 * Friendlier CR3 helpers.
238 static inline unsigned long read_cr3_pa(void)
240 return __read_cr3() & CR3_ADDR_MASK;
243 static inline void load_cr3(pgd_t *pgdir)
245 write_cr3(__sme_pa(pgdir));
249 /* This is the TSS defined by the hardware. */
251 unsigned short back_link, __blh;
253 unsigned short ss0, __ss0h;
257 * We don't use ring 1, so ss1 is a convenient scratch space in
258 * the same cacheline as sp0. We use ss1 to cache the value in
259 * MSR_IA32_SYSENTER_CS. When we context switch
260 * MSR_IA32_SYSENTER_CS, we first check if the new value being
261 * written matches ss1, and, if it's not, then we wrmsr the new
262 * value and update ss1.
264 * The only reason we context switch MSR_IA32_SYSENTER_CS is
265 * that we set it to zero in vm86 tasks to avoid corrupting the
266 * stack if we were to go through the sysenter path from vm86
269 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
271 unsigned short __ss1h;
273 unsigned short ss2, __ss2h;
285 unsigned short es, __esh;
286 unsigned short cs, __csh;
287 unsigned short ss, __ssh;
288 unsigned short ds, __dsh;
289 unsigned short fs, __fsh;
290 unsigned short gs, __gsh;
291 unsigned short ldt, __ldth;
292 unsigned short trace;
293 unsigned short io_bitmap_base;
295 } __attribute__((packed));
309 } __attribute__((packed));
315 #define IO_BITMAP_BITS 65536
316 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
317 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
318 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
319 #define INVALID_IO_BITMAP_OFFSET 0x8000
323 * The hardware state:
325 struct x86_hw_tss x86_tss;
328 * The extra 1 is there because the CPU will access an
329 * additional byte beyond the end of the IO permission
330 * bitmap. The extra byte must be all 1 bits, and must
331 * be within the limit.
333 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
337 * Space for the temporary SYSENTER stack.
339 unsigned long SYSENTER_stack_canary;
340 unsigned long SYSENTER_stack[64];
343 } ____cacheline_aligned;
345 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss);
348 * sizeof(unsigned long) coming from an extra "long" at the end
351 * -1? seg base+limit should be pointing to the address of the
354 #define __KERNEL_TSS_LIMIT \
355 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)
358 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
362 * Save the original ist values for checking stack pointers during debugging
365 unsigned long ist[7];
369 DECLARE_PER_CPU(struct orig_ist, orig_ist);
371 union irq_stack_union {
372 char irq_stack[IRQ_STACK_SIZE];
374 * GCC hardcodes the stack canary as %gs:40. Since the
375 * irq_stack is the object at %gs:0, we reserve the bottom
376 * 48 bytes of the irq stack for the canary.
380 unsigned long stack_canary;
384 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
385 DECLARE_INIT_PER_CPU(irq_stack_union);
387 DECLARE_PER_CPU(char *, irq_stack_ptr);
388 DECLARE_PER_CPU(unsigned int, irq_count);
389 extern asmlinkage void ignore_sysret(void);
391 #ifdef CONFIG_CC_STACKPROTECTOR
393 * Make sure stack canary segment base is cached-aligned:
394 * "For Intel Atom processors, avoid non zero segment base address
395 * that is not aligned to cache line boundary at all cost."
396 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
398 struct stack_canary {
399 char __pad[20]; /* canary at %gs:20 */
400 unsigned long canary;
402 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
405 * per-CPU IRQ handling stacks
408 u32 stack[THREAD_SIZE/sizeof(u32)];
409 } __aligned(THREAD_SIZE);
411 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
412 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
415 extern unsigned int fpu_kernel_xstate_size;
416 extern unsigned int fpu_user_xstate_size;
424 struct thread_struct {
425 /* Cached TLS descriptors: */
426 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
430 unsigned long sysenter_cs;
434 unsigned short fsindex;
435 unsigned short gsindex;
438 u32 status; /* thread synchronous flags */
441 unsigned long fsbase;
442 unsigned long gsbase;
445 * XXX: this could presumably be unsigned short. Alternatively,
446 * 32-bit kernels could be taught to use fsindex instead.
452 /* Save middle states of ptrace breakpoints */
453 struct perf_event *ptrace_bps[HBP_NUM];
454 /* Debug status used for traps, single steps, etc... */
455 unsigned long debugreg6;
456 /* Keep track of the exact dr7 value set by the user */
457 unsigned long ptrace_dr7;
460 unsigned long trap_nr;
461 unsigned long error_code;
463 /* Virtual 86 mode info */
466 /* IO permissions: */
467 unsigned long *io_bitmap_ptr;
469 /* Max allowed port in the bitmap, in bytes: */
470 unsigned io_bitmap_max;
472 mm_segment_t addr_limit;
474 unsigned int sig_on_uaccess_err:1;
475 unsigned int uaccess_err:1; /* uaccess failed */
477 /* Floating point and extended processor state */
480 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
486 * Thread-synchronous status.
488 * This is different from the flags in that nobody else
489 * ever touches our thread-synchronous status, so we don't
490 * have to worry about atomic accesses.
492 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
495 * Set IOPL bits in EFLAGS from given mask
497 static inline void native_set_iopl_mask(unsigned mask)
502 asm volatile ("pushfl;"
509 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
514 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
516 tss->x86_tss.sp0 = thread->sp0;
518 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
519 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
520 tss->x86_tss.ss1 = thread->sysenter_cs;
521 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
526 static inline void native_swapgs(void)
529 asm volatile("swapgs" ::: "memory");
533 static inline unsigned long current_top_of_stack(void)
536 return this_cpu_read_stable(cpu_tss.x86_tss.sp0);
538 /* sp0 on x86_32 is special in and around vm86 mode. */
539 return this_cpu_read_stable(cpu_current_top_of_stack);
543 #ifdef CONFIG_PARAVIRT
544 #include <asm/paravirt.h>
546 #define __cpuid native_cpuid
548 static inline void load_sp0(struct tss_struct *tss,
549 struct thread_struct *thread)
551 native_load_sp0(tss, thread);
554 #define set_iopl_mask native_set_iopl_mask
555 #endif /* CONFIG_PARAVIRT */
557 /* Free all resources held by a thread. */
558 extern void release_thread(struct task_struct *);
560 unsigned long get_wchan(struct task_struct *p);
563 * Generic CPUID function
564 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
565 * resulting in stale register contents being returned.
567 static inline void cpuid(unsigned int op,
568 unsigned int *eax, unsigned int *ebx,
569 unsigned int *ecx, unsigned int *edx)
573 __cpuid(eax, ebx, ecx, edx);
576 /* Some CPUID calls want 'count' to be placed in ecx */
577 static inline void cpuid_count(unsigned int op, int count,
578 unsigned int *eax, unsigned int *ebx,
579 unsigned int *ecx, unsigned int *edx)
583 __cpuid(eax, ebx, ecx, edx);
587 * CPUID functions returning a single datum
589 static inline unsigned int cpuid_eax(unsigned int op)
591 unsigned int eax, ebx, ecx, edx;
593 cpuid(op, &eax, &ebx, &ecx, &edx);
598 static inline unsigned int cpuid_ebx(unsigned int op)
600 unsigned int eax, ebx, ecx, edx;
602 cpuid(op, &eax, &ebx, &ecx, &edx);
607 static inline unsigned int cpuid_ecx(unsigned int op)
609 unsigned int eax, ebx, ecx, edx;
611 cpuid(op, &eax, &ebx, &ecx, &edx);
616 static inline unsigned int cpuid_edx(unsigned int op)
618 unsigned int eax, ebx, ecx, edx;
620 cpuid(op, &eax, &ebx, &ecx, &edx);
625 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
626 static __always_inline void rep_nop(void)
628 asm volatile("rep; nop" ::: "memory");
631 static __always_inline void cpu_relax(void)
637 * This function forces the icache and prefetched instruction stream to
638 * catch up with reality in two very specific cases:
640 * a) Text was modified using one virtual address and is about to be executed
641 * from the same physical page at a different virtual address.
643 * b) Text was modified on a different CPU, may subsequently be
644 * executed on this CPU, and you want to make sure the new version
645 * gets executed. This generally means you're calling this in a IPI.
647 * If you're calling this for a different reason, you're probably doing
650 static inline void sync_core(void)
653 * There are quite a few ways to do this. IRET-to-self is nice
654 * because it works on every CPU, at any CPL (so it's compatible
655 * with paravirtualization), and it never exits to a hypervisor.
656 * The only down sides are that it's a bit slow (it seems to be
657 * a bit more than 2x slower than the fastest options) and that
658 * it unmasks NMIs. The "push %cs" is needed because, in
659 * paravirtual environments, __KERNEL_CS may not be a valid CS
660 * value when we do IRET directly.
662 * In case NMI unmasking or performance ever becomes a problem,
663 * the next best option appears to be MOV-to-CR2 and an
664 * unconditional jump. That sequence also works on all CPUs,
665 * but it will fault at CPL3 (i.e. Xen PV and lguest).
667 * CPUID is the conventional way, but it's nasty: it doesn't
668 * exist on some 486-like CPUs, and it usually exits to a
671 * Like all of Linux's memory ordering operations, this is a
672 * compiler barrier as well.
674 register void *__sp asm(_ASM_SP);
683 : "+r" (__sp) : : "memory");
691 "addq $8, (%%rsp)\n\t"
698 : "=&r" (tmp), "+r" (__sp) : : "cc", "memory");
702 extern void select_idle_routine(const struct cpuinfo_x86 *c);
703 extern void amd_e400_c1e_apic_setup(void);
705 extern unsigned long boot_option_idle_override;
707 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
710 extern void enable_sep_cpu(void);
711 extern int sysenter_setup(void);
713 extern void early_trap_init(void);
714 void early_trap_pf_init(void);
716 /* Defined in head.S */
717 extern struct desc_ptr early_gdt_descr;
719 extern void cpu_set_gdt(int);
720 extern void switch_to_new_gdt(int);
721 extern void load_direct_gdt(int);
722 extern void load_fixmap_gdt(int);
723 extern void load_percpu_segment(int);
724 extern void cpu_init(void);
726 static inline unsigned long get_debugctlmsr(void)
728 unsigned long debugctlmsr = 0;
730 #ifndef CONFIG_X86_DEBUGCTLMSR
731 if (boot_cpu_data.x86 < 6)
734 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
739 static inline void update_debugctlmsr(unsigned long debugctlmsr)
741 #ifndef CONFIG_X86_DEBUGCTLMSR
742 if (boot_cpu_data.x86 < 6)
745 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
748 extern void set_task_blockstep(struct task_struct *task, bool on);
750 /* Boot loader type from the setup header: */
751 extern int bootloader_type;
752 extern int bootloader_version;
754 extern char ignore_fpu_irq;
756 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
757 #define ARCH_HAS_PREFETCHW
758 #define ARCH_HAS_SPINLOCK_PREFETCH
761 # define BASE_PREFETCH ""
762 # define ARCH_HAS_PREFETCH
764 # define BASE_PREFETCH "prefetcht0 %P1"
768 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
770 * It's not worth to care about 3dnow prefetches for the K6
771 * because they are microcoded there and very slow.
773 static inline void prefetch(const void *x)
775 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
777 "m" (*(const char *)x));
781 * 3dnow prefetch to get an exclusive cache line.
782 * Useful for spinlocks to avoid one state transition in the
783 * cache coherency protocol:
785 static inline void prefetchw(const void *x)
787 alternative_input(BASE_PREFETCH, "prefetchw %P1",
788 X86_FEATURE_3DNOWPREFETCH,
789 "m" (*(const char *)x));
792 static inline void spin_lock_prefetch(const void *x)
797 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
798 TOP_OF_KERNEL_STACK_PADDING)
802 * User space process size: 3GB (default).
804 #define IA32_PAGE_OFFSET PAGE_OFFSET
805 #define TASK_SIZE PAGE_OFFSET
806 #define TASK_SIZE_MAX TASK_SIZE
807 #define STACK_TOP TASK_SIZE
808 #define STACK_TOP_MAX STACK_TOP
810 #define INIT_THREAD { \
811 .sp0 = TOP_OF_INIT_STACK, \
812 .sysenter_cs = __KERNEL_CS, \
813 .io_bitmap_ptr = NULL, \
814 .addr_limit = KERNEL_DS, \
818 * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack.
819 * This is necessary to guarantee that the entire "struct pt_regs"
820 * is accessible even if the CPU haven't stored the SS/ESP registers
821 * on the stack (interrupt gate does not save these registers
822 * when switching to the same priv ring).
823 * Therefore beware: accessing the ss/esp fields of the
824 * "struct pt_regs" is possible, but they may contain the
825 * completely wrong values.
827 #define task_pt_regs(task) \
829 unsigned long __ptr = (unsigned long)task_stack_page(task); \
830 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
831 ((struct pt_regs *)__ptr) - 1; \
834 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
838 * User space process size. 47bits minus one guard page. The guard
839 * page is necessary on Intel CPUs: if a SYSCALL instruction is at
840 * the highest possible canonical userspace address, then that
841 * syscall will enter the kernel with a non-canonical return
842 * address, and SYSRET will explode dangerously. We avoid this
843 * particular problem by preventing anything from being mapped
844 * at the maximum canonical address.
846 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
848 /* This decides where the kernel will search for a free chunk of vm
849 * space during mmap's.
851 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
852 0xc0000000 : 0xFFFFe000)
854 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
855 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
856 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
857 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
859 #define STACK_TOP TASK_SIZE
860 #define STACK_TOP_MAX TASK_SIZE_MAX
862 #define INIT_THREAD { \
863 .sp0 = TOP_OF_INIT_STACK, \
864 .addr_limit = KERNEL_DS, \
867 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
868 extern unsigned long KSTK_ESP(struct task_struct *task);
870 #endif /* CONFIG_X86_64 */
872 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
873 unsigned long new_sp);
876 * This decides where the kernel will search for a free chunk of vm
877 * space during mmap's.
879 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
880 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE)
882 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
884 /* Get/set a process' ability to use the timestamp counter instruction */
885 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
886 #define SET_TSC_CTL(val) set_tsc_mode((val))
888 extern int get_tsc_mode(unsigned long adr);
889 extern int set_tsc_mode(unsigned int val);
891 DECLARE_PER_CPU(u64, msr_misc_features_shadow);
893 /* Register/unregister a process' MPX related resource */
894 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
895 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
897 #ifdef CONFIG_X86_INTEL_MPX
898 extern int mpx_enable_management(void);
899 extern int mpx_disable_management(void);
901 static inline int mpx_enable_management(void)
905 static inline int mpx_disable_management(void)
909 #endif /* CONFIG_X86_INTEL_MPX */
911 #ifdef CONFIG_CPU_SUP_AMD
912 extern u16 amd_get_nb_id(int cpu);
913 extern u32 amd_get_nodes_per_socket(void);
915 static inline u16 amd_get_nb_id(int cpu) { return 0; }
916 static inline u32 amd_get_nodes_per_socket(void) { return 0; }
919 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
921 uint32_t base, eax, signature[3];
923 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
924 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
926 if (!memcmp(sig, signature, 12) &&
927 (leaves == 0 || ((eax - base) >= leaves)))
934 extern unsigned long arch_align_stack(unsigned long sp);
935 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
937 void default_idle(void);
939 bool xen_set_default_idle(void);
941 #define xen_set_default_idle 0
944 void stop_this_cpu(void *dummy);
945 void df_debug(struct pt_regs *regs, long error_code);
946 #endif /* _ASM_X86_PROCESSOR_H */