1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
23 #include <asm/special_insns.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/err.h>
31 #include <linux/irqflags.h>
34 * We handle most unaligned accesses in hardware. On the other hand
35 * unaligned DMA can be quite expensive on some Nehalem processors.
37 * Based on this we disable the IP header alignment in network drivers.
39 #define NET_IP_ALIGN 0
43 * Default implementation of macro that returns current
44 * instruction pointer ("program counter").
46 static inline void *current_text_addr(void)
50 asm volatile("mov $1f, %0; 1:":"=r" (pc));
55 #ifdef CONFIG_X86_VSMP
56 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
57 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
59 # define ARCH_MIN_TASKALIGN 16
60 # define ARCH_MIN_MMSTRUCT_ALIGN 0
68 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
69 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
70 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
71 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
72 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
73 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
74 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
77 * CPU type and hardware bug flags. Kept separately for each CPU.
78 * Members of this structure are referenced in head.S, so think twice
79 * before touching them. [mj]
83 __u8 x86; /* CPU family */
84 __u8 x86_vendor; /* CPU vendor */
88 char wp_works_ok; /* It doesn't on 386's */
90 /* Problems on some 486Dx4's and old 386's: */
95 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
100 /* CPUID returned core id bits: */
101 __u8 x86_coreid_bits;
102 /* Max extended CPUID function supported: */
103 __u32 extended_cpuid_level;
104 /* Maximum supported CPUID level, -1=no CPUID: */
106 __u32 x86_capability[NCAPINTS + NBUGINTS];
107 char x86_vendor_id[16];
108 char x86_model_id[64];
109 /* in KB - valid for CPUS which support this call: */
111 int x86_cache_alignment; /* In bytes */
113 unsigned long loops_per_jiffy;
114 /* cpuid returned max cores value: */
118 u16 x86_clflush_size;
119 /* number of cores as seen by the OS: */
121 /* Physical processor id: */
125 /* Compute unit id */
127 /* Index into per_cpu list: */
132 #define X86_VENDOR_INTEL 0
133 #define X86_VENDOR_CYRIX 1
134 #define X86_VENDOR_AMD 2
135 #define X86_VENDOR_UMC 3
136 #define X86_VENDOR_CENTAUR 5
137 #define X86_VENDOR_TRANSMETA 7
138 #define X86_VENDOR_NSC 8
139 #define X86_VENDOR_NUM 9
141 #define X86_VENDOR_UNKNOWN 0xff
144 * capabilities of CPUs
146 extern struct cpuinfo_x86 boot_cpu_data;
147 extern struct cpuinfo_x86 new_cpu_data;
149 extern struct tss_struct doublefault_tss;
150 extern __u32 cpu_caps_cleared[NCAPINTS];
151 extern __u32 cpu_caps_set[NCAPINTS];
154 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
155 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
157 #define cpu_info boot_cpu_data
158 #define cpu_data(cpu) boot_cpu_data
161 extern const struct seq_operations cpuinfo_op;
163 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
165 extern void cpu_detect(struct cpuinfo_x86 *c);
166 extern void fpu_detect(struct cpuinfo_x86 *c);
168 extern void early_cpu_init(void);
169 extern void identify_boot_cpu(void);
170 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
171 extern void print_cpu_info(struct cpuinfo_x86 *);
172 void print_cpu_msr(struct cpuinfo_x86 *);
173 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
174 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
175 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
177 extern void detect_extended_topology(struct cpuinfo_x86 *c);
178 extern void detect_ht(struct cpuinfo_x86 *c);
181 extern int have_cpuid_p(void);
183 static inline int have_cpuid_p(void)
188 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
189 unsigned int *ecx, unsigned int *edx)
191 /* ecx is often an input as well as an output. */
197 : "0" (*eax), "2" (*ecx)
201 static inline void load_cr3(pgd_t *pgdir)
203 write_cr3(__pa(pgdir));
207 /* This is the TSS defined by the hardware. */
209 unsigned short back_link, __blh;
211 unsigned short ss0, __ss0h;
213 /* ss1 caches MSR_IA32_SYSENTER_CS: */
214 unsigned short ss1, __ss1h;
216 unsigned short ss2, __ss2h;
228 unsigned short es, __esh;
229 unsigned short cs, __csh;
230 unsigned short ss, __ssh;
231 unsigned short ds, __dsh;
232 unsigned short fs, __fsh;
233 unsigned short gs, __gsh;
234 unsigned short ldt, __ldth;
235 unsigned short trace;
236 unsigned short io_bitmap_base;
238 } __attribute__((packed));
252 } __attribute__((packed)) ____cacheline_aligned;
258 #define IO_BITMAP_BITS 65536
259 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
260 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
261 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
262 #define INVALID_IO_BITMAP_OFFSET 0x8000
266 * The hardware state:
268 struct x86_hw_tss x86_tss;
271 * The extra 1 is there because the CPU will access an
272 * additional byte beyond the end of the IO permission
273 * bitmap. The extra byte must be all 1 bits, and must
274 * be within the limit.
276 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
279 * .. and then another 0x100 bytes for the emergency kernel stack:
281 unsigned long stack[64];
283 } ____cacheline_aligned;
285 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss);
288 * Save the original ist values for checking stack pointers during debugging
291 unsigned long ist[7];
294 #define MXCSR_DEFAULT 0x1f80
296 struct i387_fsave_struct {
297 u32 cwd; /* FPU Control Word */
298 u32 swd; /* FPU Status Word */
299 u32 twd; /* FPU Tag Word */
300 u32 fip; /* FPU IP Offset */
301 u32 fcs; /* FPU IP Selector */
302 u32 foo; /* FPU Operand Pointer Offset */
303 u32 fos; /* FPU Operand Pointer Selector */
305 /* 8*10 bytes for each FP-reg = 80 bytes: */
308 /* Software status information [not touched by FSAVE ]: */
312 struct i387_fxsave_struct {
313 u16 cwd; /* Control Word */
314 u16 swd; /* Status Word */
315 u16 twd; /* Tag Word */
316 u16 fop; /* Last Instruction Opcode */
319 u64 rip; /* Instruction Pointer */
320 u64 rdp; /* Data Pointer */
323 u32 fip; /* FPU IP Offset */
324 u32 fcs; /* FPU IP Selector */
325 u32 foo; /* FPU Operand Offset */
326 u32 fos; /* FPU Operand Selector */
329 u32 mxcsr; /* MXCSR Register State */
330 u32 mxcsr_mask; /* MXCSR Mask */
332 /* 8*16 bytes for each FP-reg = 128 bytes: */
335 /* 16*16 bytes for each XMM-reg = 256 bytes: */
345 } __attribute__((aligned(16)));
347 struct i387_soft_struct {
355 /* 8*10 bytes for each FP-reg = 80 bytes: */
363 struct math_emu_info *info;
368 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
372 /* We don't support LWP yet: */
387 struct xsave_hdr_struct {
391 } __attribute__((packed));
393 struct xsave_struct {
394 struct i387_fxsave_struct i387;
395 struct xsave_hdr_struct xsave_hdr;
396 struct ymmh_struct ymmh;
397 struct lwp_struct lwp;
398 struct bndreg bndreg[4];
399 struct bndcsr bndcsr;
400 /* new processor state extensions will go here */
401 } __attribute__ ((packed, aligned (64)));
403 union thread_xstate {
404 struct i387_fsave_struct fsave;
405 struct i387_fxsave_struct fxsave;
406 struct i387_soft_struct soft;
407 struct xsave_struct xsave;
411 unsigned int last_cpu;
412 unsigned int has_fpu;
413 union thread_xstate *state;
417 DECLARE_PER_CPU(struct orig_ist, orig_ist);
419 union irq_stack_union {
420 char irq_stack[IRQ_STACK_SIZE];
422 * GCC hardcodes the stack canary as %gs:40. Since the
423 * irq_stack is the object at %gs:0, we reserve the bottom
424 * 48 bytes of the irq stack for the canary.
428 unsigned long stack_canary;
432 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
433 DECLARE_INIT_PER_CPU(irq_stack_union);
435 DECLARE_PER_CPU(char *, irq_stack_ptr);
436 DECLARE_PER_CPU(unsigned int, irq_count);
437 extern asmlinkage void ignore_sysret(void);
439 #ifdef CONFIG_CC_STACKPROTECTOR
441 * Make sure stack canary segment base is cached-aligned:
442 * "For Intel Atom processors, avoid non zero segment base address
443 * that is not aligned to cache line boundary at all cost."
444 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
446 struct stack_canary {
447 char __pad[20]; /* canary at %gs:20 */
448 unsigned long canary;
450 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
453 * per-CPU IRQ handling stacks
456 u32 stack[THREAD_SIZE/sizeof(u32)];
457 } __aligned(THREAD_SIZE);
459 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
460 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
463 extern unsigned int xstate_size;
464 extern void free_thread_xstate(struct task_struct *);
465 extern struct kmem_cache *task_xstate_cachep;
469 struct thread_struct {
470 /* Cached TLS descriptors: */
471 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
475 unsigned long sysenter_cs;
477 unsigned long usersp; /* Copy from PDA */
480 unsigned short fsindex;
481 unsigned short gsindex;
490 /* Save middle states of ptrace breakpoints */
491 struct perf_event *ptrace_bps[HBP_NUM];
492 /* Debug status used for traps, single steps, etc... */
493 unsigned long debugreg6;
494 /* Keep track of the exact dr7 value set by the user */
495 unsigned long ptrace_dr7;
498 unsigned long trap_nr;
499 unsigned long error_code;
500 /* floating point and extended processor state */
503 /* Virtual 86 mode info */
504 struct vm86_struct __user *vm86_info;
505 unsigned long screen_bitmap;
506 unsigned long v86flags;
507 unsigned long v86mask;
508 unsigned long saved_sp0;
509 unsigned int saved_fs;
510 unsigned int saved_gs;
512 /* IO permissions: */
513 unsigned long *io_bitmap_ptr;
515 /* Max allowed port in the bitmap, in bytes: */
516 unsigned io_bitmap_max;
518 * fpu_counter contains the number of consecutive context switches
519 * that the FPU is used. If this is over a threshold, the lazy fpu
520 * saving becomes unlazy to save the trap. This is an unsigned char
521 * so that after 256 times the counter wraps and the behavior turns
522 * lazy again; this to deal with bursty apps that only use FPU for
525 unsigned char fpu_counter;
529 * Set IOPL bits in EFLAGS from given mask
531 static inline void native_set_iopl_mask(unsigned mask)
536 asm volatile ("pushfl;"
543 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
548 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
550 tss->x86_tss.sp0 = thread->sp0;
552 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
553 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
554 tss->x86_tss.ss1 = thread->sysenter_cs;
555 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
560 static inline void native_swapgs(void)
563 asm volatile("swapgs" ::: "memory");
567 static inline unsigned long this_cpu_sp0(void)
569 return this_cpu_read_stable(cpu_tss.x86_tss.sp0);
572 #ifdef CONFIG_PARAVIRT
573 #include <asm/paravirt.h>
575 #define __cpuid native_cpuid
576 #define paravirt_enabled() 0
578 static inline void load_sp0(struct tss_struct *tss,
579 struct thread_struct *thread)
581 native_load_sp0(tss, thread);
584 #define set_iopl_mask native_set_iopl_mask
585 #endif /* CONFIG_PARAVIRT */
592 /* Free all resources held by a thread. */
593 extern void release_thread(struct task_struct *);
595 unsigned long get_wchan(struct task_struct *p);
598 * Generic CPUID function
599 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
600 * resulting in stale register contents being returned.
602 static inline void cpuid(unsigned int op,
603 unsigned int *eax, unsigned int *ebx,
604 unsigned int *ecx, unsigned int *edx)
608 __cpuid(eax, ebx, ecx, edx);
611 /* Some CPUID calls want 'count' to be placed in ecx */
612 static inline void cpuid_count(unsigned int op, int count,
613 unsigned int *eax, unsigned int *ebx,
614 unsigned int *ecx, unsigned int *edx)
618 __cpuid(eax, ebx, ecx, edx);
622 * CPUID functions returning a single datum
624 static inline unsigned int cpuid_eax(unsigned int op)
626 unsigned int eax, ebx, ecx, edx;
628 cpuid(op, &eax, &ebx, &ecx, &edx);
633 static inline unsigned int cpuid_ebx(unsigned int op)
635 unsigned int eax, ebx, ecx, edx;
637 cpuid(op, &eax, &ebx, &ecx, &edx);
642 static inline unsigned int cpuid_ecx(unsigned int op)
644 unsigned int eax, ebx, ecx, edx;
646 cpuid(op, &eax, &ebx, &ecx, &edx);
651 static inline unsigned int cpuid_edx(unsigned int op)
653 unsigned int eax, ebx, ecx, edx;
655 cpuid(op, &eax, &ebx, &ecx, &edx);
660 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
661 static inline void rep_nop(void)
663 asm volatile("rep; nop" ::: "memory");
666 static inline void cpu_relax(void)
671 #define cpu_relax_lowlatency() cpu_relax()
673 /* Stop speculative execution and prefetching of modified code. */
674 static inline void sync_core(void)
680 * Do a CPUID if available, otherwise do a jump. The jump
681 * can conveniently enough be the jump around CPUID.
683 asm volatile("cmpl %2,%1\n\t"
688 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
689 : "ebx", "ecx", "edx", "memory");
692 * CPUID is a barrier to speculative execution.
693 * Prefetched instructions are automatically
694 * invalidated when modified.
699 : "ebx", "ecx", "edx", "memory");
703 extern void select_idle_routine(const struct cpuinfo_x86 *c);
704 extern void init_amd_e400_c1e_mask(void);
706 extern unsigned long boot_option_idle_override;
707 extern bool amd_e400_c1e_detected;
709 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
712 extern void enable_sep_cpu(void);
713 extern int sysenter_setup(void);
715 extern void early_trap_init(void);
716 void early_trap_pf_init(void);
718 /* Defined in head.S */
719 extern struct desc_ptr early_gdt_descr;
721 extern void cpu_set_gdt(int);
722 extern void switch_to_new_gdt(int);
723 extern void load_percpu_segment(int);
724 extern void cpu_init(void);
726 static inline unsigned long get_debugctlmsr(void)
728 unsigned long debugctlmsr = 0;
730 #ifndef CONFIG_X86_DEBUGCTLMSR
731 if (boot_cpu_data.x86 < 6)
734 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
739 static inline void update_debugctlmsr(unsigned long debugctlmsr)
741 #ifndef CONFIG_X86_DEBUGCTLMSR
742 if (boot_cpu_data.x86 < 6)
745 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
748 extern void set_task_blockstep(struct task_struct *task, bool on);
751 * from system description table in BIOS. Mostly for MCA use, but
752 * others may find it useful:
754 extern unsigned int machine_id;
755 extern unsigned int machine_submodel_id;
756 extern unsigned int BIOS_revision;
758 /* Boot loader type from the setup header: */
759 extern int bootloader_type;
760 extern int bootloader_version;
762 extern char ignore_fpu_irq;
764 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
765 #define ARCH_HAS_PREFETCHW
766 #define ARCH_HAS_SPINLOCK_PREFETCH
769 # define BASE_PREFETCH ""
770 # define ARCH_HAS_PREFETCH
772 # define BASE_PREFETCH "prefetcht0 %P1"
776 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
778 * It's not worth to care about 3dnow prefetches for the K6
779 * because they are microcoded there and very slow.
781 static inline void prefetch(const void *x)
783 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
785 "m" (*(const char *)x));
789 * 3dnow prefetch to get an exclusive cache line.
790 * Useful for spinlocks to avoid one state transition in the
791 * cache coherency protocol:
793 static inline void prefetchw(const void *x)
795 alternative_input(BASE_PREFETCH, "prefetchw %P1",
796 X86_FEATURE_3DNOWPREFETCH,
797 "m" (*(const char *)x));
800 static inline void spin_lock_prefetch(const void *x)
807 * User space process size: 3GB (default).
809 #define TASK_SIZE PAGE_OFFSET
810 #define TASK_SIZE_MAX TASK_SIZE
811 #define STACK_TOP TASK_SIZE
812 #define STACK_TOP_MAX STACK_TOP
814 #define INIT_THREAD { \
815 .sp0 = sizeof(init_stack) + (long)&init_stack, \
817 .sysenter_cs = __KERNEL_CS, \
818 .io_bitmap_ptr = NULL, \
822 * Note that the .io_bitmap member must be extra-big. This is because
823 * the CPU will access an additional byte beyond the end of the IO
824 * permission bitmap. The extra byte must be all 1 bits, and must
825 * be within the limit.
829 .sp0 = sizeof(init_stack) + (long)&init_stack, \
830 .ss0 = __KERNEL_DS, \
831 .ss1 = __KERNEL_CS, \
832 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
834 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
837 extern unsigned long thread_saved_pc(struct task_struct *tsk);
839 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
840 #define KSTK_TOP(info) \
842 unsigned long *__ptr = (unsigned long *)(info); \
843 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
847 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
848 * This is necessary to guarantee that the entire "struct pt_regs"
849 * is accessible even if the CPU haven't stored the SS/ESP registers
850 * on the stack (interrupt gate does not save these registers
851 * when switching to the same priv ring).
852 * Therefore beware: accessing the ss/esp fields of the
853 * "struct pt_regs" is possible, but they may contain the
854 * completely wrong values.
856 #define task_pt_regs(task) \
858 struct pt_regs *__regs__; \
859 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
863 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
867 * User space process size. 47bits minus one guard page. The guard
868 * page is necessary on Intel CPUs: if a SYSCALL instruction is at
869 * the highest possible canonical userspace address, then that
870 * syscall will enter the kernel with a non-canonical return
871 * address, and SYSRET will explode dangerously. We avoid this
872 * particular problem by preventing anything from being mapped
873 * at the maximum canonical address.
875 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
877 /* This decides where the kernel will search for a free chunk of vm
878 * space during mmap's.
880 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
881 0xc0000000 : 0xFFFFe000)
883 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
884 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
885 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
886 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
888 #define STACK_TOP TASK_SIZE
889 #define STACK_TOP_MAX TASK_SIZE_MAX
891 #define INIT_THREAD { \
892 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
896 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
900 * Return saved PC of a blocked thread.
901 * What is this good for? it will be always the scheduler or ret_from_fork.
903 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
905 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
906 extern unsigned long KSTK_ESP(struct task_struct *task);
909 * User space RSP while inside the SYSCALL fast path
911 DECLARE_PER_CPU(unsigned long, old_rsp);
913 #endif /* CONFIG_X86_64 */
915 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
916 unsigned long new_sp);
919 * This decides where the kernel will search for a free chunk of vm
920 * space during mmap's.
922 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
924 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
926 /* Get/set a process' ability to use the timestamp counter instruction */
927 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
928 #define SET_TSC_CTL(val) set_tsc_mode((val))
930 extern int get_tsc_mode(unsigned long adr);
931 extern int set_tsc_mode(unsigned int val);
933 /* Register/unregister a process' MPX related resource */
934 #define MPX_ENABLE_MANAGEMENT(tsk) mpx_enable_management((tsk))
935 #define MPX_DISABLE_MANAGEMENT(tsk) mpx_disable_management((tsk))
937 #ifdef CONFIG_X86_INTEL_MPX
938 extern int mpx_enable_management(struct task_struct *tsk);
939 extern int mpx_disable_management(struct task_struct *tsk);
941 static inline int mpx_enable_management(struct task_struct *tsk)
945 static inline int mpx_disable_management(struct task_struct *tsk)
949 #endif /* CONFIG_X86_INTEL_MPX */
951 extern u16 amd_get_nb_id(int cpu);
953 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
955 uint32_t base, eax, signature[3];
957 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
958 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
960 if (!memcmp(sig, signature, 12) &&
961 (leaves == 0 || ((eax - base) >= leaves)))
968 extern unsigned long arch_align_stack(unsigned long sp);
969 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
971 void default_idle(void);
973 bool xen_set_default_idle(void);
975 #define xen_set_default_idle 0
978 void stop_this_cpu(void *dummy);
979 void df_debug(struct pt_regs *regs, long error_code);
980 #endif /* _ASM_X86_PROCESSOR_H */