arch/x86/include/asm/perf_event.h

   1 #ifndef _ASM_X86_PERF_EVENT_H
   2 #define _ASM_X86_PERF_EVENT_H
   3
   4 /*
   5  * Performance event hw details:
   6  */
   7
   8 #define X86_PMC_MAX_GENERIC                                    32
   9 #define X86_PMC_MAX_FIXED                                       3
  10
  11 #define X86_PMC_IDX_GENERIC                                     0
  12 #define X86_PMC_IDX_FIXED                                      32
  13 #define X86_PMC_IDX_MAX                                        64
  14
  15 #define MSR_ARCH_PERFMON_PERFCTR0                             0xc1
  16 #define MSR_ARCH_PERFMON_PERFCTR1                             0xc2
  17
  18 #define MSR_ARCH_PERFMON_EVENTSEL0                           0x186
  19 #define MSR_ARCH_PERFMON_EVENTSEL1                           0x187
  20
  21 #define ARCH_PERFMON_EVENTSEL_EVENT                     0x000000FFULL
  22 #define ARCH_PERFMON_EVENTSEL_UMASK                     0x0000FF00ULL
  23 #define ARCH_PERFMON_EVENTSEL_USR                       (1ULL << 16)
  24 #define ARCH_PERFMON_EVENTSEL_OS                        (1ULL << 17)
  25 #define ARCH_PERFMON_EVENTSEL_EDGE                      (1ULL << 18)
  26 #define ARCH_PERFMON_EVENTSEL_INT                       (1ULL << 20)
  27 #define ARCH_PERFMON_EVENTSEL_ANY                       (1ULL << 21)
  28 #define ARCH_PERFMON_EVENTSEL_ENABLE                    (1ULL << 22)
  29 #define ARCH_PERFMON_EVENTSEL_INV                       (1ULL << 23)
  30 #define ARCH_PERFMON_EVENTSEL_CMASK                     0xFF000000ULL
  31
  32 #define AMD_PERFMON_EVENTSEL_GUESTONLY                  (1ULL << 40)
  33 #define AMD_PERFMON_EVENTSEL_HOSTONLY                   (1ULL << 41)
  34
  35 #define AMD64_EVENTSEL_EVENT    \
  36         (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
  37 #define INTEL_ARCH_EVENT_MASK   \
  38         (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
  39
  40 #define X86_RAW_EVENT_MASK              \
  41         (ARCH_PERFMON_EVENTSEL_EVENT |  \
  42          ARCH_PERFMON_EVENTSEL_UMASK |  \
  43          ARCH_PERFMON_EVENTSEL_EDGE  |  \
  44          ARCH_PERFMON_EVENTSEL_INV   |  \
  45          ARCH_PERFMON_EVENTSEL_CMASK)
  46 #define AMD64_RAW_EVENT_MASK            \
  47         (X86_RAW_EVENT_MASK          |  \
  48          AMD64_EVENTSEL_EVENT)
  49
  50 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL                 0x3c
  51 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK         (0x00 << 8)
  52 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX                  0
  53 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
  54                 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
  55
  56 #define ARCH_PERFMON_BRANCH_MISSES_RETIRED                       6
  57
  58 /*
  59  * Intel "Architectural Performance Monitoring" CPUID
  60  * detection/enumeration details:
  61  */
  62 union cpuid10_eax {
  63         struct {
  64                 unsigned int version_id:8;
  65                 unsigned int num_counters:8;
  66                 unsigned int bit_width:8;
  67                 unsigned int mask_length:8;
  68         } split;
  69         unsigned int full;
  70 };
  71
  72 union cpuid10_edx {
  73         struct {
  74                 unsigned int num_counters_fixed:5;
  75                 unsigned int bit_width_fixed:8;
  76                 unsigned int reserved:19;
  77         } split;
  78         unsigned int full;
  79 };
  80
  81
  82 /*
  83  * Fixed-purpose performance events:
  84  */
  85
  86 /*
  87  * All 3 fixed-mode PMCs are configured via this single MSR:
  88  */
  89 #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL                 0x38d
  90
  91 /*
  92  * The counts are available in three separate MSRs:
  93  */
  94
  95 /* Instr_Retired.Any: */
  96 #define MSR_ARCH_PERFMON_FIXED_CTR0                     0x309
  97 #define X86_PMC_IDX_FIXED_INSTRUCTIONS                  (X86_PMC_IDX_FIXED + 0)
  98
  99 /* CPU_CLK_Unhalted.Core: */
 100 #define MSR_ARCH_PERFMON_FIXED_CTR1                     0x30a
 101 #define X86_PMC_IDX_FIXED_CPU_CYCLES                    (X86_PMC_IDX_FIXED + 1)
 102
 103 /* CPU_CLK_Unhalted.Ref: */
 104 #define MSR_ARCH_PERFMON_FIXED_CTR2                     0x30b
 105 #define X86_PMC_IDX_FIXED_BUS_CYCLES                    (X86_PMC_IDX_FIXED + 2)
 106
 107 /*
 108  * We model BTS tracing as another fixed-mode PMC.
 109  *
 110  * We choose a value in the middle of the fixed event range, since lower
 111  * values are used by actual fixed events and higher values are used
 112  * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
 113  */
 114 #define X86_PMC_IDX_FIXED_BTS                           (X86_PMC_IDX_FIXED + 16)
 115
 116 /* IbsFetchCtl bits/masks */
 117 #define IBS_FETCH_RAND_EN       (1ULL<<57)
 118 #define IBS_FETCH_VAL           (1ULL<<49)
 119 #define IBS_FETCH_ENABLE        (1ULL<<48)
 120 #define IBS_FETCH_CNT           0xFFFF0000ULL
 121 #define IBS_FETCH_MAX_CNT       0x0000FFFFULL
 122
 123 /* IbsOpCtl bits */
 124 #define IBS_OP_CNT_CTL          (1ULL<<19)
 125 #define IBS_OP_VAL              (1ULL<<18)
 126 #define IBS_OP_ENABLE           (1ULL<<17)
 127 #define IBS_OP_MAX_CNT          0x0000FFFFULL
 128 #define IBS_OP_MAX_CNT_EXT      0x007FFFFFULL   /* not a register bit mask */
 129
 130 #ifdef CONFIG_PERF_EVENTS
 131 extern void perf_events_lapic_init(void);
 132
 133 #define PERF_EVENT_INDEX_OFFSET                 0
 134
 135 /*
 136  * Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
 137  * This flag is otherwise unused and ABI specified to be 0, so nobody should
 138  * care what we do with it.
 139  */
 140 #define PERF_EFLAGS_EXACT       (1UL << 3)
 141
 142 struct pt_regs;
 143 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
 144 extern unsigned long perf_misc_flags(struct pt_regs *regs);
 145 #define perf_misc_flags(regs)   perf_misc_flags(regs)
 146
 147 #include <asm/stacktrace.h>
 148
 149 /*
 150  * We abuse bit 3 from flags to pass exact information, see perf_misc_flags
 151  * and the comment with PERF_EFLAGS_EXACT.
 152  */
 153 #define perf_arch_fetch_caller_regs(regs, __ip)         {       \
 154         (regs)->ip = (__ip);                                    \
 155         (regs)->bp = caller_frame_pointer();                    \
 156         (regs)->cs = __KERNEL_CS;                               \
 157         regs->flags = 0;                                        \
 158         asm volatile(                                           \
 159                 _ASM_MOV "%%"_ASM_SP ", %0\n"                   \
 160                 : "=m" ((regs)->sp)                             \
 161                 :: "memory"                                     \
 162         );                                                      \
 163 }
 164
 165 #else
 166 static inline void perf_events_lapic_init(void) { }
 167 #endif
 168
 169 #endif /* _ASM_X86_PERF_EVENT_H */