1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PARAVIRT_H
3 #define _ASM_X86_PARAVIRT_H
4 /* Various instructions on x86 need to be replaced for
5 * para-virtualization: those hooks are defined here. */
8 #include <asm/pgtable_types.h>
10 #include <asm/nospec-branch.h>
12 #include <asm/paravirt_types.h>
15 #include <linux/bug.h>
16 #include <linux/types.h>
17 #include <linux/cpumask.h>
18 #include <asm/frame.h>
20 static inline unsigned long long paravirt_sched_clock(void)
22 return PVOP_CALL0(unsigned long long, time.sched_clock);
26 extern struct static_key paravirt_steal_enabled;
27 extern struct static_key paravirt_steal_rq_enabled;
29 __visible void __native_queued_spin_unlock(struct qspinlock *lock);
30 bool pv_is_native_spin_unlock(void);
31 __visible bool __native_vcpu_is_preempted(long cpu);
32 bool pv_is_native_vcpu_is_preempted(void);
34 static inline u64 paravirt_steal_clock(int cpu)
36 return PVOP_CALL1(u64, time.steal_clock, cpu);
39 /* The paravirtualized I/O functions */
40 static inline void slow_down_io(void)
42 pv_ops.cpu.io_delay();
44 pv_ops.cpu.io_delay();
45 pv_ops.cpu.io_delay();
46 pv_ops.cpu.io_delay();
50 static inline void __flush_tlb(void)
52 PVOP_VCALL0(mmu.flush_tlb_user);
55 static inline void __flush_tlb_global(void)
57 PVOP_VCALL0(mmu.flush_tlb_kernel);
60 static inline void __flush_tlb_one_user(unsigned long addr)
62 PVOP_VCALL1(mmu.flush_tlb_one_user, addr);
65 static inline void flush_tlb_others(const struct cpumask *cpumask,
66 const struct flush_tlb_info *info)
68 PVOP_VCALL2(mmu.flush_tlb_others, cpumask, info);
71 static inline void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table)
73 PVOP_VCALL2(mmu.tlb_remove_table, tlb, table);
76 static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
78 PVOP_VCALL1(mmu.exit_mmap, mm);
81 #ifdef CONFIG_PARAVIRT_XXL
82 static inline void load_sp0(unsigned long sp0)
84 PVOP_VCALL1(cpu.load_sp0, sp0);
87 /* The paravirtualized CPUID instruction. */
88 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
89 unsigned int *ecx, unsigned int *edx)
91 PVOP_VCALL4(cpu.cpuid, eax, ebx, ecx, edx);
95 * These special macros can be used to get or set a debugging register
97 static inline unsigned long paravirt_get_debugreg(int reg)
99 return PVOP_CALL1(unsigned long, cpu.get_debugreg, reg);
101 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
102 static inline void set_debugreg(unsigned long val, int reg)
104 PVOP_VCALL2(cpu.set_debugreg, reg, val);
107 static inline unsigned long read_cr0(void)
109 return PVOP_CALL0(unsigned long, cpu.read_cr0);
112 static inline void write_cr0(unsigned long x)
114 PVOP_VCALL1(cpu.write_cr0, x);
117 static inline unsigned long read_cr2(void)
119 return PVOP_CALLEE0(unsigned long, mmu.read_cr2);
122 static inline void write_cr2(unsigned long x)
124 PVOP_VCALL1(mmu.write_cr2, x);
127 static inline unsigned long __read_cr3(void)
129 return PVOP_CALL0(unsigned long, mmu.read_cr3);
132 static inline void write_cr3(unsigned long x)
134 PVOP_VCALL1(mmu.write_cr3, x);
137 static inline void __write_cr4(unsigned long x)
139 PVOP_VCALL1(cpu.write_cr4, x);
142 static inline void arch_safe_halt(void)
144 PVOP_VCALL0(irq.safe_halt);
147 static inline void halt(void)
149 PVOP_VCALL0(irq.halt);
152 static inline void wbinvd(void)
154 PVOP_VCALL0(cpu.wbinvd);
157 #define get_kernel_rpl() (pv_info.kernel_rpl)
159 static inline u64 paravirt_read_msr(unsigned msr)
161 return PVOP_CALL1(u64, cpu.read_msr, msr);
164 static inline void paravirt_write_msr(unsigned msr,
165 unsigned low, unsigned high)
167 PVOP_VCALL3(cpu.write_msr, msr, low, high);
170 static inline u64 paravirt_read_msr_safe(unsigned msr, int *err)
172 return PVOP_CALL2(u64, cpu.read_msr_safe, msr, err);
175 static inline int paravirt_write_msr_safe(unsigned msr,
176 unsigned low, unsigned high)
178 return PVOP_CALL3(int, cpu.write_msr_safe, msr, low, high);
181 #define rdmsr(msr, val1, val2) \
183 u64 _l = paravirt_read_msr(msr); \
188 #define wrmsr(msr, val1, val2) \
190 paravirt_write_msr(msr, val1, val2); \
193 #define rdmsrl(msr, val) \
195 val = paravirt_read_msr(msr); \
198 static inline void wrmsrl(unsigned msr, u64 val)
200 wrmsr(msr, (u32)val, (u32)(val>>32));
203 #define wrmsr_safe(msr, a, b) paravirt_write_msr_safe(msr, a, b)
205 /* rdmsr with exception handling */
206 #define rdmsr_safe(msr, a, b) \
209 u64 _l = paravirt_read_msr_safe(msr, &_err); \
215 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
219 *p = paravirt_read_msr_safe(msr, &err);
223 static inline unsigned long long paravirt_read_pmc(int counter)
225 return PVOP_CALL1(u64, cpu.read_pmc, counter);
228 #define rdpmc(counter, low, high) \
230 u64 _l = paravirt_read_pmc(counter); \
235 #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter))
237 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
239 PVOP_VCALL2(cpu.alloc_ldt, ldt, entries);
242 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
244 PVOP_VCALL2(cpu.free_ldt, ldt, entries);
247 static inline void load_TR_desc(void)
249 PVOP_VCALL0(cpu.load_tr_desc);
251 static inline void load_gdt(const struct desc_ptr *dtr)
253 PVOP_VCALL1(cpu.load_gdt, dtr);
255 static inline void load_idt(const struct desc_ptr *dtr)
257 PVOP_VCALL1(cpu.load_idt, dtr);
259 static inline void set_ldt(const void *addr, unsigned entries)
261 PVOP_VCALL2(cpu.set_ldt, addr, entries);
263 static inline unsigned long paravirt_store_tr(void)
265 return PVOP_CALL0(unsigned long, cpu.store_tr);
268 #define store_tr(tr) ((tr) = paravirt_store_tr())
269 static inline void load_TLS(struct thread_struct *t, unsigned cpu)
271 PVOP_VCALL2(cpu.load_tls, t, cpu);
275 static inline void load_gs_index(unsigned int gs)
277 PVOP_VCALL1(cpu.load_gs_index, gs);
281 static inline void write_ldt_entry(struct desc_struct *dt, int entry,
284 PVOP_VCALL3(cpu.write_ldt_entry, dt, entry, desc);
287 static inline void write_gdt_entry(struct desc_struct *dt, int entry,
288 void *desc, int type)
290 PVOP_VCALL4(cpu.write_gdt_entry, dt, entry, desc, type);
293 static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
295 PVOP_VCALL3(cpu.write_idt_entry, dt, entry, g);
298 #ifdef CONFIG_X86_IOPL_IOPERM
299 static inline void tss_update_io_bitmap(void)
301 PVOP_VCALL0(cpu.update_io_bitmap);
305 static inline void paravirt_activate_mm(struct mm_struct *prev,
306 struct mm_struct *next)
308 PVOP_VCALL2(mmu.activate_mm, prev, next);
311 static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
312 struct mm_struct *mm)
314 PVOP_VCALL2(mmu.dup_mmap, oldmm, mm);
317 static inline int paravirt_pgd_alloc(struct mm_struct *mm)
319 return PVOP_CALL1(int, mmu.pgd_alloc, mm);
322 static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd)
324 PVOP_VCALL2(mmu.pgd_free, mm, pgd);
327 static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn)
329 PVOP_VCALL2(mmu.alloc_pte, mm, pfn);
331 static inline void paravirt_release_pte(unsigned long pfn)
333 PVOP_VCALL1(mmu.release_pte, pfn);
336 static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn)
338 PVOP_VCALL2(mmu.alloc_pmd, mm, pfn);
341 static inline void paravirt_release_pmd(unsigned long pfn)
343 PVOP_VCALL1(mmu.release_pmd, pfn);
346 static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn)
348 PVOP_VCALL2(mmu.alloc_pud, mm, pfn);
350 static inline void paravirt_release_pud(unsigned long pfn)
352 PVOP_VCALL1(mmu.release_pud, pfn);
355 static inline void paravirt_alloc_p4d(struct mm_struct *mm, unsigned long pfn)
357 PVOP_VCALL2(mmu.alloc_p4d, mm, pfn);
360 static inline void paravirt_release_p4d(unsigned long pfn)
362 PVOP_VCALL1(mmu.release_p4d, pfn);
365 static inline pte_t __pte(pteval_t val)
369 if (sizeof(pteval_t) > sizeof(long))
370 ret = PVOP_CALLEE2(pteval_t, mmu.make_pte, val, (u64)val >> 32);
372 ret = PVOP_CALLEE1(pteval_t, mmu.make_pte, val);
374 return (pte_t) { .pte = ret };
377 static inline pteval_t pte_val(pte_t pte)
381 if (sizeof(pteval_t) > sizeof(long))
382 ret = PVOP_CALLEE2(pteval_t, mmu.pte_val,
383 pte.pte, (u64)pte.pte >> 32);
385 ret = PVOP_CALLEE1(pteval_t, mmu.pte_val, pte.pte);
390 static inline pgd_t __pgd(pgdval_t val)
394 if (sizeof(pgdval_t) > sizeof(long))
395 ret = PVOP_CALLEE2(pgdval_t, mmu.make_pgd, val, (u64)val >> 32);
397 ret = PVOP_CALLEE1(pgdval_t, mmu.make_pgd, val);
399 return (pgd_t) { ret };
402 static inline pgdval_t pgd_val(pgd_t pgd)
406 if (sizeof(pgdval_t) > sizeof(long))
407 ret = PVOP_CALLEE2(pgdval_t, mmu.pgd_val,
408 pgd.pgd, (u64)pgd.pgd >> 32);
410 ret = PVOP_CALLEE1(pgdval_t, mmu.pgd_val, pgd.pgd);
415 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
416 static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma, unsigned long addr,
421 ret = PVOP_CALL3(pteval_t, mmu.ptep_modify_prot_start, vma, addr, ptep);
423 return (pte_t) { .pte = ret };
426 static inline void ptep_modify_prot_commit(struct vm_area_struct *vma, unsigned long addr,
427 pte_t *ptep, pte_t old_pte, pte_t pte)
430 if (sizeof(pteval_t) > sizeof(long))
432 pv_ops.mmu.ptep_modify_prot_commit(vma, addr, ptep, pte);
434 PVOP_VCALL4(mmu.ptep_modify_prot_commit,
435 vma, addr, ptep, pte.pte);
438 static inline void set_pte(pte_t *ptep, pte_t pte)
440 if (sizeof(pteval_t) > sizeof(long))
441 PVOP_VCALL3(mmu.set_pte, ptep, pte.pte, (u64)pte.pte >> 32);
443 PVOP_VCALL2(mmu.set_pte, ptep, pte.pte);
446 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
447 pte_t *ptep, pte_t pte)
449 if (sizeof(pteval_t) > sizeof(long))
451 pv_ops.mmu.set_pte_at(mm, addr, ptep, pte);
453 PVOP_VCALL4(mmu.set_pte_at, mm, addr, ptep, pte.pte);
456 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
458 pmdval_t val = native_pmd_val(pmd);
460 if (sizeof(pmdval_t) > sizeof(long))
461 PVOP_VCALL3(mmu.set_pmd, pmdp, val, (u64)val >> 32);
463 PVOP_VCALL2(mmu.set_pmd, pmdp, val);
466 #if CONFIG_PGTABLE_LEVELS >= 3
467 static inline pmd_t __pmd(pmdval_t val)
471 if (sizeof(pmdval_t) > sizeof(long))
472 ret = PVOP_CALLEE2(pmdval_t, mmu.make_pmd, val, (u64)val >> 32);
474 ret = PVOP_CALLEE1(pmdval_t, mmu.make_pmd, val);
476 return (pmd_t) { ret };
479 static inline pmdval_t pmd_val(pmd_t pmd)
483 if (sizeof(pmdval_t) > sizeof(long))
484 ret = PVOP_CALLEE2(pmdval_t, mmu.pmd_val,
485 pmd.pmd, (u64)pmd.pmd >> 32);
487 ret = PVOP_CALLEE1(pmdval_t, mmu.pmd_val, pmd.pmd);
492 static inline void set_pud(pud_t *pudp, pud_t pud)
494 pudval_t val = native_pud_val(pud);
496 if (sizeof(pudval_t) > sizeof(long))
497 PVOP_VCALL3(mmu.set_pud, pudp, val, (u64)val >> 32);
499 PVOP_VCALL2(mmu.set_pud, pudp, val);
501 #if CONFIG_PGTABLE_LEVELS >= 4
502 static inline pud_t __pud(pudval_t val)
506 ret = PVOP_CALLEE1(pudval_t, mmu.make_pud, val);
508 return (pud_t) { ret };
511 static inline pudval_t pud_val(pud_t pud)
513 return PVOP_CALLEE1(pudval_t, mmu.pud_val, pud.pud);
516 static inline void pud_clear(pud_t *pudp)
518 set_pud(pudp, __pud(0));
521 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
523 p4dval_t val = native_p4d_val(p4d);
525 PVOP_VCALL2(mmu.set_p4d, p4dp, val);
528 #if CONFIG_PGTABLE_LEVELS >= 5
530 static inline p4d_t __p4d(p4dval_t val)
532 p4dval_t ret = PVOP_CALLEE1(p4dval_t, mmu.make_p4d, val);
534 return (p4d_t) { ret };
537 static inline p4dval_t p4d_val(p4d_t p4d)
539 return PVOP_CALLEE1(p4dval_t, mmu.p4d_val, p4d.p4d);
542 static inline void __set_pgd(pgd_t *pgdp, pgd_t pgd)
544 PVOP_VCALL2(mmu.set_pgd, pgdp, native_pgd_val(pgd));
547 #define set_pgd(pgdp, pgdval) do { \
548 if (pgtable_l5_enabled()) \
549 __set_pgd(pgdp, pgdval); \
551 set_p4d((p4d_t *)(pgdp), (p4d_t) { (pgdval).pgd }); \
554 #define pgd_clear(pgdp) do { \
555 if (pgtable_l5_enabled()) \
556 set_pgd(pgdp, __pgd(0)); \
559 #endif /* CONFIG_PGTABLE_LEVELS == 5 */
561 static inline void p4d_clear(p4d_t *p4dp)
563 set_p4d(p4dp, __p4d(0));
566 #endif /* CONFIG_PGTABLE_LEVELS == 4 */
568 #endif /* CONFIG_PGTABLE_LEVELS >= 3 */
570 #ifdef CONFIG_X86_PAE
571 /* Special-case pte-setting operations for PAE, which can't update a
572 64-bit pte atomically */
573 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
575 PVOP_VCALL3(mmu.set_pte_atomic, ptep, pte.pte, pte.pte >> 32);
578 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
581 PVOP_VCALL3(mmu.pte_clear, mm, addr, ptep);
584 static inline void pmd_clear(pmd_t *pmdp)
586 PVOP_VCALL1(mmu.pmd_clear, pmdp);
588 #else /* !CONFIG_X86_PAE */
589 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
594 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
597 set_pte_at(mm, addr, ptep, __pte(0));
600 static inline void pmd_clear(pmd_t *pmdp)
602 set_pmd(pmdp, __pmd(0));
604 #endif /* CONFIG_X86_PAE */
606 #define __HAVE_ARCH_START_CONTEXT_SWITCH
607 static inline void arch_start_context_switch(struct task_struct *prev)
609 PVOP_VCALL1(cpu.start_context_switch, prev);
612 static inline void arch_end_context_switch(struct task_struct *next)
614 PVOP_VCALL1(cpu.end_context_switch, next);
617 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
618 static inline void arch_enter_lazy_mmu_mode(void)
620 PVOP_VCALL0(mmu.lazy_mode.enter);
623 static inline void arch_leave_lazy_mmu_mode(void)
625 PVOP_VCALL0(mmu.lazy_mode.leave);
628 static inline void arch_flush_lazy_mmu_mode(void)
630 PVOP_VCALL0(mmu.lazy_mode.flush);
633 static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
634 phys_addr_t phys, pgprot_t flags)
636 pv_ops.mmu.set_fixmap(idx, phys, flags);
640 #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS)
642 static __always_inline void pv_queued_spin_lock_slowpath(struct qspinlock *lock,
645 PVOP_VCALL2(lock.queued_spin_lock_slowpath, lock, val);
648 static __always_inline void pv_queued_spin_unlock(struct qspinlock *lock)
650 PVOP_VCALLEE1(lock.queued_spin_unlock, lock);
653 static __always_inline void pv_wait(u8 *ptr, u8 val)
655 PVOP_VCALL2(lock.wait, ptr, val);
658 static __always_inline void pv_kick(int cpu)
660 PVOP_VCALL1(lock.kick, cpu);
663 static __always_inline bool pv_vcpu_is_preempted(long cpu)
665 return PVOP_CALLEE1(bool, lock.vcpu_is_preempted, cpu);
668 void __raw_callee_save___native_queued_spin_unlock(struct qspinlock *lock);
669 bool __raw_callee_save___native_vcpu_is_preempted(long cpu);
671 #endif /* SMP && PARAVIRT_SPINLOCKS */
674 #define PV_SAVE_REGS "pushl %ecx; pushl %edx;"
675 #define PV_RESTORE_REGS "popl %edx; popl %ecx;"
677 /* save and restore all caller-save registers, except return value */
678 #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;"
679 #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;"
681 #define PV_FLAGS_ARG "0"
682 #define PV_EXTRA_CLOBBERS
683 #define PV_VEXTRA_CLOBBERS
685 /* save and restore all caller-save registers, except return value */
686 #define PV_SAVE_ALL_CALLER_REGS \
695 #define PV_RESTORE_ALL_CALLER_REGS \
705 /* We save some registers, but all of them, that's too much. We clobber all
706 * caller saved registers but the argument parameter */
707 #define PV_SAVE_REGS "pushq %%rdi;"
708 #define PV_RESTORE_REGS "popq %%rdi;"
709 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi"
710 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi"
711 #define PV_FLAGS_ARG "D"
715 * Generate a thunk around a function which saves all caller-save
716 * registers except for the return value. This allows C functions to
717 * be called from assembler code where fewer than normal registers are
718 * available. It may also help code generation around calls from C
719 * code if the common case doesn't use many registers.
721 * When a callee is wrapped in a thunk, the caller can assume that all
722 * arg regs and all scratch registers are preserved across the
723 * call. The return value in rax/eax will not be saved, even for void
726 #define PV_THUNK_NAME(func) "__raw_callee_save_" #func
727 #define PV_CALLEE_SAVE_REGS_THUNK(func) \
728 extern typeof(func) __raw_callee_save_##func; \
730 asm(".pushsection .text;" \
731 ".globl " PV_THUNK_NAME(func) ";" \
732 ".type " PV_THUNK_NAME(func) ", @function;" \
733 PV_THUNK_NAME(func) ":" \
735 PV_SAVE_ALL_CALLER_REGS \
737 PV_RESTORE_ALL_CALLER_REGS \
740 ".size " PV_THUNK_NAME(func) ", .-" PV_THUNK_NAME(func) ";" \
743 /* Get a reference to a callee-save function */
744 #define PV_CALLEE_SAVE(func) \
745 ((struct paravirt_callee_save) { __raw_callee_save_##func })
747 /* Promise that "func" already uses the right calling convention */
748 #define __PV_IS_CALLEE_SAVE(func) \
749 ((struct paravirt_callee_save) { func })
751 #ifdef CONFIG_PARAVIRT_XXL
752 static inline notrace unsigned long arch_local_save_flags(void)
754 return PVOP_CALLEE0(unsigned long, irq.save_fl);
757 static inline notrace void arch_local_irq_restore(unsigned long f)
759 PVOP_VCALLEE1(irq.restore_fl, f);
762 static inline notrace void arch_local_irq_disable(void)
764 PVOP_VCALLEE0(irq.irq_disable);
767 static inline notrace void arch_local_irq_enable(void)
769 PVOP_VCALLEE0(irq.irq_enable);
772 static inline notrace unsigned long arch_local_irq_save(void)
776 f = arch_local_save_flags();
777 arch_local_irq_disable();
783 /* Make sure as little as possible of this mess escapes. */
798 extern void default_banner(void);
800 #else /* __ASSEMBLY__ */
802 #define _PVSITE(ptype, ops, word, algn) \
806 .pushsection .parainstructions,"a"; \
814 #define COND_PUSH(set, mask, reg) \
815 .if ((~(set)) & mask); push %reg; .endif
816 #define COND_POP(set, mask, reg) \
817 .if ((~(set)) & mask); pop %reg; .endif
821 #define PV_SAVE_REGS(set) \
822 COND_PUSH(set, CLBR_RAX, rax); \
823 COND_PUSH(set, CLBR_RCX, rcx); \
824 COND_PUSH(set, CLBR_RDX, rdx); \
825 COND_PUSH(set, CLBR_RSI, rsi); \
826 COND_PUSH(set, CLBR_RDI, rdi); \
827 COND_PUSH(set, CLBR_R8, r8); \
828 COND_PUSH(set, CLBR_R9, r9); \
829 COND_PUSH(set, CLBR_R10, r10); \
830 COND_PUSH(set, CLBR_R11, r11)
831 #define PV_RESTORE_REGS(set) \
832 COND_POP(set, CLBR_R11, r11); \
833 COND_POP(set, CLBR_R10, r10); \
834 COND_POP(set, CLBR_R9, r9); \
835 COND_POP(set, CLBR_R8, r8); \
836 COND_POP(set, CLBR_RDI, rdi); \
837 COND_POP(set, CLBR_RSI, rsi); \
838 COND_POP(set, CLBR_RDX, rdx); \
839 COND_POP(set, CLBR_RCX, rcx); \
840 COND_POP(set, CLBR_RAX, rax)
842 #define PARA_PATCH(off) ((off) / 8)
843 #define PARA_SITE(ptype, ops) _PVSITE(ptype, ops, .quad, 8)
844 #define PARA_INDIRECT(addr) *addr(%rip)
846 #define PV_SAVE_REGS(set) \
847 COND_PUSH(set, CLBR_EAX, eax); \
848 COND_PUSH(set, CLBR_EDI, edi); \
849 COND_PUSH(set, CLBR_ECX, ecx); \
850 COND_PUSH(set, CLBR_EDX, edx)
851 #define PV_RESTORE_REGS(set) \
852 COND_POP(set, CLBR_EDX, edx); \
853 COND_POP(set, CLBR_ECX, ecx); \
854 COND_POP(set, CLBR_EDI, edi); \
855 COND_POP(set, CLBR_EAX, eax)
857 #define PARA_PATCH(off) ((off) / 4)
858 #define PARA_SITE(ptype, ops) _PVSITE(ptype, ops, .long, 4)
859 #define PARA_INDIRECT(addr) *%cs:addr
862 #ifdef CONFIG_PARAVIRT_XXL
863 #define INTERRUPT_RETURN \
864 PARA_SITE(PARA_PATCH(PV_CPU_iret), \
865 ANNOTATE_RETPOLINE_SAFE; \
866 jmp PARA_INDIRECT(pv_ops+PV_CPU_iret);)
868 #define DISABLE_INTERRUPTS(clobbers) \
869 PARA_SITE(PARA_PATCH(PV_IRQ_irq_disable), \
870 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
871 ANNOTATE_RETPOLINE_SAFE; \
872 call PARA_INDIRECT(pv_ops+PV_IRQ_irq_disable); \
873 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
875 #define ENABLE_INTERRUPTS(clobbers) \
876 PARA_SITE(PARA_PATCH(PV_IRQ_irq_enable), \
877 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
878 ANNOTATE_RETPOLINE_SAFE; \
879 call PARA_INDIRECT(pv_ops+PV_IRQ_irq_enable); \
880 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
884 #ifdef CONFIG_PARAVIRT_XXL
886 * If swapgs is used while the userspace stack is still current,
887 * there's no way to call a pvop. The PV replacement *must* be
888 * inlined, or the swapgs instruction must be trapped and emulated.
890 #define SWAPGS_UNSAFE_STACK \
891 PARA_SITE(PARA_PATCH(PV_CPU_swapgs), swapgs)
894 * Note: swapgs is very special, and in practise is either going to be
895 * implemented with a single "swapgs" instruction or something very
896 * special. Either way, we don't need to save any registers for
900 PARA_SITE(PARA_PATCH(PV_CPU_swapgs), \
901 ANNOTATE_RETPOLINE_SAFE; \
902 call PARA_INDIRECT(pv_ops+PV_CPU_swapgs); \
905 #define USERGS_SYSRET64 \
906 PARA_SITE(PARA_PATCH(PV_CPU_usergs_sysret64), \
907 ANNOTATE_RETPOLINE_SAFE; \
908 jmp PARA_INDIRECT(pv_ops+PV_CPU_usergs_sysret64);)
910 #ifdef CONFIG_DEBUG_ENTRY
911 #define SAVE_FLAGS(clobbers) \
912 PARA_SITE(PARA_PATCH(PV_IRQ_save_fl), \
913 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
914 ANNOTATE_RETPOLINE_SAFE; \
915 call PARA_INDIRECT(pv_ops+PV_IRQ_save_fl); \
916 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
918 #endif /* CONFIG_PARAVIRT_XXL */
919 #endif /* CONFIG_X86_64 */
921 #ifdef CONFIG_PARAVIRT_XXL
923 #define GET_CR2_INTO_AX \
924 PARA_SITE(PARA_PATCH(PV_MMU_read_cr2), \
925 ANNOTATE_RETPOLINE_SAFE; \
926 call PARA_INDIRECT(pv_ops+PV_MMU_read_cr2); \
929 #endif /* CONFIG_PARAVIRT_XXL */
932 #endif /* __ASSEMBLY__ */
933 #else /* CONFIG_PARAVIRT */
934 # define default_banner x86_init_noop
935 #endif /* !CONFIG_PARAVIRT */
938 #ifndef CONFIG_PARAVIRT_XXL
939 static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
940 struct mm_struct *mm)
945 #ifndef CONFIG_PARAVIRT
946 static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
950 #endif /* __ASSEMBLY__ */
951 #endif /* _ASM_X86_PARAVIRT_H */