1 /* SPDX-License-Identifier: GPL-2.0 */
3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
4 #define _ASM_X86_NOSPEC_BRANCH_H_
6 #include <asm/alternative.h>
7 #include <asm/alternative-asm.h>
8 #include <asm/cpufeatures.h>
9 #include <asm/msr-index.h>
12 * Fill the CPU return stack buffer.
14 * Each entry in the RSB, if used for a speculative 'ret', contains an
15 * infinite 'pause; lfence; jmp' loop to capture speculative execution.
17 * This is required in various cases for retpoline and IBRS-based
18 * mitigations for the Spectre variant 2 vulnerability. Sometimes to
19 * eliminate potentially bogus entries from the RSB, and sometimes
20 * purely to ensure that it doesn't get empty, which on some CPUs would
21 * allow predictions from other (unwanted!) sources to be used.
23 * We define a CPP macro such that it can be used from both .S files and
24 * inline assembly. It's possible to do a .macro and then include that
25 * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
28 #define RSB_CLEAR_LOOPS 32 /* To forcibly overwrite all entries */
29 #define RSB_FILL_LOOPS 16 /* To avoid underflow */
32 * Google experimented with loop-unrolling and this turned out to be
33 * the optimal version — two calls, each with their own speculation
34 * trap should their return address end up getting used, in a loop.
36 #define __FILL_RETURN_BUFFER(reg, nr, sp) \
40 773: /* speculation trap */ \
46 775: /* speculation trap */ \
53 add $(BITS_PER_LONG/8) * nr, sp;
58 * This should be used immediately before a retpoline alternative. It tells
59 * objtool where the retpolines are so that it can make sense of the control
60 * flow by just reading the original instruction(s) and ignoring the
63 .macro ANNOTATE_NOSPEC_ALTERNATIVE
65 .pushsection .discard.nospec
66 .long .Lannotate_\@ - .
71 * This should be used immediately before an indirect jump/call. It tells
72 * objtool the subsequent indirect jump/call is vouched safe for retpoline
75 .macro ANNOTATE_RETPOLINE_SAFE
77 .pushsection .discard.retpoline_safe
78 _ASM_PTR .Lannotate_\@
83 * These are the bare retpoline primitives for indirect jmp and call.
84 * Do not use these directly; they only exist to make the ALTERNATIVE
85 * invocation below less ugly.
87 .macro RETPOLINE_JMP reg:req
99 * This is a wrapper around RETPOLINE_JMP so the called function in reg
100 * returns to the instruction after the macro.
102 .macro RETPOLINE_CALL reg:req
104 .Ldo_retpoline_jmp_\@:
107 call .Ldo_retpoline_jmp_\@
111 * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
112 * indirect jmp/call which may be susceptible to the Spectre variant 2
115 .macro JMP_NOSPEC reg:req
116 #ifdef CONFIG_RETPOLINE
117 ANNOTATE_NOSPEC_ALTERNATIVE
118 ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *\reg), \
119 __stringify(RETPOLINE_JMP \reg), X86_FEATURE_RETPOLINE, \
120 __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *\reg), X86_FEATURE_RETPOLINE_AMD
126 .macro CALL_NOSPEC reg:req
127 #ifdef CONFIG_RETPOLINE
128 ANNOTATE_NOSPEC_ALTERNATIVE
129 ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; call *\reg), \
130 __stringify(RETPOLINE_CALL \reg), X86_FEATURE_RETPOLINE,\
131 __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *\reg), X86_FEATURE_RETPOLINE_AMD
138 * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
139 * monstrosity above, manually.
141 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req
142 #ifdef CONFIG_RETPOLINE
143 ANNOTATE_NOSPEC_ALTERNATIVE
144 ALTERNATIVE "jmp .Lskip_rsb_\@", \
145 __stringify(__FILL_RETURN_BUFFER(\reg,\nr,%_ASM_SP)) \
151 #else /* __ASSEMBLY__ */
153 #define ANNOTATE_NOSPEC_ALTERNATIVE \
155 ".pushsection .discard.nospec\n\t" \
156 ".long 999b - .\n\t" \
159 #define ANNOTATE_RETPOLINE_SAFE \
161 ".pushsection .discard.retpoline_safe\n\t" \
162 _ASM_PTR " 999b\n\t" \
165 #if defined(CONFIG_X86_64) && defined(RETPOLINE)
168 * Since the inline asm uses the %V modifier which is only in newer GCC,
169 * the 64-bit one is dependent on RETPOLINE not CONFIG_RETPOLINE.
171 # define CALL_NOSPEC \
172 ANNOTATE_NOSPEC_ALTERNATIVE \
174 ANNOTATE_RETPOLINE_SAFE \
175 "call *%[thunk_target]\n", \
176 "call __x86_indirect_thunk_%V[thunk_target]\n", \
177 X86_FEATURE_RETPOLINE)
178 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
180 #elif defined(CONFIG_X86_32) && defined(CONFIG_RETPOLINE)
182 * For i386 we use the original ret-equivalent retpoline, because
183 * otherwise we'll run out of registers. We don't care about CET
186 # define CALL_NOSPEC \
188 ANNOTATE_RETPOLINE_SAFE \
189 "call *%[thunk_target]\n", \
192 "901: call 903f;\n" \
197 "903: addl $4, %%esp;\n" \
198 " pushl %[thunk_target];\n" \
201 "904: call 901b;\n", \
202 X86_FEATURE_RETPOLINE)
204 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
205 #else /* No retpoline for C / inline asm */
206 # define CALL_NOSPEC "call *%[thunk_target]\n"
207 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
210 /* The Spectre V2 mitigation variants */
211 enum spectre_v2_mitigation {
213 SPECTRE_V2_RETPOLINE_MINIMAL,
214 SPECTRE_V2_RETPOLINE_MINIMAL_AMD,
215 SPECTRE_V2_RETPOLINE_GENERIC,
216 SPECTRE_V2_RETPOLINE_AMD,
221 * The Intel specification for the SPEC_CTRL MSR requires that we
222 * preserve any already set reserved bits at boot time (e.g. for
223 * future additions that this kernel is not currently aware of).
224 * We then set any additional mitigation bits that we want
225 * ourselves and always use this as the base for SPEC_CTRL.
226 * We also use this when handling guest entry/exit as below.
228 extern void x86_spec_ctrl_set(u64);
229 extern u64 x86_spec_ctrl_get_default(void);
231 /* The Speculative Store Bypass disable variants */
232 enum ssb_mitigation {
233 SPEC_STORE_BYPASS_NONE,
234 SPEC_STORE_BYPASS_DISABLE,
235 SPEC_STORE_BYPASS_PRCTL,
236 SPEC_STORE_BYPASS_SECCOMP,
239 extern char __indirect_thunk_start[];
240 extern char __indirect_thunk_end[];
243 * On VMEXIT we must ensure that no RSB predictions learned in the guest
244 * can be followed in the host, by overwriting the RSB completely. Both
245 * retpoline and IBRS mitigations for Spectre v2 need this; only on future
246 * CPUs with IBRS_ALL *might* it be avoided.
248 static inline void vmexit_fill_RSB(void)
250 #ifdef CONFIG_RETPOLINE
253 asm volatile (ANNOTATE_NOSPEC_ALTERNATIVE
254 ALTERNATIVE("jmp 910f",
255 __stringify(__FILL_RETURN_BUFFER(%0, RSB_CLEAR_LOOPS, %1)),
256 X86_FEATURE_RETPOLINE)
258 : "=r" (loops), ASM_CALL_CONSTRAINT
263 static __always_inline
264 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
266 asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
269 "d" ((u32)(val >> 32)),
270 [feature] "i" (feature)
274 static inline void indirect_branch_prediction_barrier(void)
276 u64 val = PRED_CMD_IBPB;
278 alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
282 * With retpoline, we must use IBRS to restrict branch prediction
283 * before calling into firmware.
285 * (Implemented as CPP macros due to header hell.)
287 #define firmware_restrict_branch_speculation_start() \
289 u64 val = x86_spec_ctrl_get_default() | SPEC_CTRL_IBRS; \
292 alternative_msr_write(MSR_IA32_SPEC_CTRL, val, \
293 X86_FEATURE_USE_IBRS_FW); \
296 #define firmware_restrict_branch_speculation_end() \
298 u64 val = x86_spec_ctrl_get_default(); \
300 alternative_msr_write(MSR_IA32_SPEC_CTRL, val, \
301 X86_FEATURE_USE_IBRS_FW); \
305 #endif /* __ASSEMBLY__ */
308 * Below is used in the eBPF JIT compiler and emits the byte sequence
309 * for the following assembly:
311 * With retpolines configured:
322 * Without retpolines configured:
326 #ifdef CONFIG_RETPOLINE
327 # define RETPOLINE_RAX_BPF_JIT_SIZE 17
328 # define RETPOLINE_RAX_BPF_JIT() \
329 EMIT1_off32(0xE8, 7); /* callq do_rop */ \
331 EMIT2(0xF3, 0x90); /* pause */ \
332 EMIT3(0x0F, 0xAE, 0xE8); /* lfence */ \
333 EMIT2(0xEB, 0xF9); /* jmp spec_trap */ \
335 EMIT4(0x48, 0x89, 0x04, 0x24); /* mov %rax,(%rsp) */ \
336 EMIT1(0xC3); /* retq */
338 # define RETPOLINE_RAX_BPF_JIT_SIZE 2
339 # define RETPOLINE_RAX_BPF_JIT() \
340 EMIT2(0xFF, 0xE0); /* jmp *%rax */
343 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */