1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_MSR_INDEX_H
3 #define _ASM_X86_MSR_INDEX_H
5 #include <linux/bits.h>
8 * CPU model specific register (MSR) numbers.
10 * Do not add new entries to this file unless the definitions are shared
11 * between multiple compilation units.
14 /* x86-64 specific MSRs */
15 #define MSR_EFER 0xc0000080 /* extended feature register */
16 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
17 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
18 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
19 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
20 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
21 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
22 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
23 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
26 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
27 #define _EFER_LME 8 /* Long mode enable */
28 #define _EFER_LMA 10 /* Long mode active (read-only) */
29 #define _EFER_NX 11 /* No execute enable */
30 #define _EFER_SVME 12 /* Enable virtualization */
31 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
32 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
34 #define EFER_SCE (1<<_EFER_SCE)
35 #define EFER_LME (1<<_EFER_LME)
36 #define EFER_LMA (1<<_EFER_LMA)
37 #define EFER_NX (1<<_EFER_NX)
38 #define EFER_SVME (1<<_EFER_SVME)
39 #define EFER_LMSLE (1<<_EFER_LMSLE)
40 #define EFER_FFXSR (1<<_EFER_FFXSR)
42 /* Intel MSRs. Some also available on other CPUs */
44 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
45 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */
46 #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */
47 #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */
48 #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */
49 #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
51 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
52 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
54 #define MSR_PPIN_CTL 0x0000004e
55 #define MSR_PPIN 0x0000004f
57 #define MSR_IA32_PERFCTR0 0x000000c1
58 #define MSR_IA32_PERFCTR1 0x000000c2
59 #define MSR_FSB_FREQ 0x000000cd
60 #define MSR_PLATFORM_INFO 0x000000ce
61 #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31
62 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
64 #define MSR_IA32_UMWAIT_CONTROL 0xe1
65 #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0)
66 #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1)
68 * The time field is bit[31:2], but representing a 32bit value with
71 #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U)
73 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
74 #define NHM_C3_AUTO_DEMOTE (1UL << 25)
75 #define NHM_C1_AUTO_DEMOTE (1UL << 26)
76 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
77 #define SNB_C3_AUTO_UNDEMOTE (1UL << 27)
78 #define SNB_C1_AUTO_UNDEMOTE (1UL << 28)
80 #define MSR_MTRRcap 0x000000fe
82 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
83 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */
84 #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */
85 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */
86 #define ARCH_CAP_SSB_NO BIT(4) /*
87 * Not susceptible to Speculative Store Bypass
88 * attack, so no Speculative Store Bypass
91 #define ARCH_CAP_MDS_NO BIT(5) /*
93 * Microarchitectural Data
94 * Sampling (MDS) vulnerabilities.
97 #define MSR_IA32_FLUSH_CMD 0x0000010b
98 #define L1D_FLUSH BIT(0) /*
99 * Writeback and invalidate the
103 #define MSR_IA32_BBL_CR_CTL 0x00000119
104 #define MSR_IA32_BBL_CR_CTL3 0x0000011e
106 #define MSR_IA32_SYSENTER_CS 0x00000174
107 #define MSR_IA32_SYSENTER_ESP 0x00000175
108 #define MSR_IA32_SYSENTER_EIP 0x00000176
110 #define MSR_IA32_MCG_CAP 0x00000179
111 #define MSR_IA32_MCG_STATUS 0x0000017a
112 #define MSR_IA32_MCG_CTL 0x0000017b
113 #define MSR_IA32_MCG_EXT_CTL 0x000004d0
115 #define MSR_OFFCORE_RSP_0 0x000001a6
116 #define MSR_OFFCORE_RSP_1 0x000001a7
117 #define MSR_TURBO_RATIO_LIMIT 0x000001ad
118 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae
119 #define MSR_TURBO_RATIO_LIMIT2 0x000001af
121 #define MSR_LBR_SELECT 0x000001c8
122 #define MSR_LBR_TOS 0x000001c9
123 #define MSR_LBR_NHM_FROM 0x00000680
124 #define MSR_LBR_NHM_TO 0x000006c0
125 #define MSR_LBR_CORE_FROM 0x00000040
126 #define MSR_LBR_CORE_TO 0x00000060
128 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
129 #define LBR_INFO_MISPRED BIT_ULL(63)
130 #define LBR_INFO_IN_TX BIT_ULL(62)
131 #define LBR_INFO_ABORT BIT_ULL(61)
132 #define LBR_INFO_CYCLES 0xffff
134 #define MSR_IA32_PEBS_ENABLE 0x000003f1
135 #define MSR_PEBS_DATA_CFG 0x000003f2
136 #define MSR_IA32_DS_AREA 0x00000600
137 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
138 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
140 #define MSR_IA32_RTIT_CTL 0x00000570
141 #define RTIT_CTL_TRACEEN BIT(0)
142 #define RTIT_CTL_CYCLEACC BIT(1)
143 #define RTIT_CTL_OS BIT(2)
144 #define RTIT_CTL_USR BIT(3)
145 #define RTIT_CTL_PWR_EVT_EN BIT(4)
146 #define RTIT_CTL_FUP_ON_PTW BIT(5)
147 #define RTIT_CTL_FABRIC_EN BIT(6)
148 #define RTIT_CTL_CR3EN BIT(7)
149 #define RTIT_CTL_TOPA BIT(8)
150 #define RTIT_CTL_MTC_EN BIT(9)
151 #define RTIT_CTL_TSC_EN BIT(10)
152 #define RTIT_CTL_DISRETC BIT(11)
153 #define RTIT_CTL_PTW_EN BIT(12)
154 #define RTIT_CTL_BRANCH_EN BIT(13)
155 #define RTIT_CTL_MTC_RANGE_OFFSET 14
156 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
157 #define RTIT_CTL_CYC_THRESH_OFFSET 19
158 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
159 #define RTIT_CTL_PSB_FREQ_OFFSET 24
160 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
161 #define RTIT_CTL_ADDR0_OFFSET 32
162 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET)
163 #define RTIT_CTL_ADDR1_OFFSET 36
164 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET)
165 #define RTIT_CTL_ADDR2_OFFSET 40
166 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET)
167 #define RTIT_CTL_ADDR3_OFFSET 44
168 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET)
169 #define MSR_IA32_RTIT_STATUS 0x00000571
170 #define RTIT_STATUS_FILTEREN BIT(0)
171 #define RTIT_STATUS_CONTEXTEN BIT(1)
172 #define RTIT_STATUS_TRIGGEREN BIT(2)
173 #define RTIT_STATUS_BUFFOVF BIT(3)
174 #define RTIT_STATUS_ERROR BIT(4)
175 #define RTIT_STATUS_STOPPED BIT(5)
176 #define RTIT_STATUS_BYTECNT_OFFSET 32
177 #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET)
178 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
179 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
180 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
181 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
182 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
183 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
184 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
185 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
186 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
187 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
188 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
190 #define MSR_MTRRfix64K_00000 0x00000250
191 #define MSR_MTRRfix16K_80000 0x00000258
192 #define MSR_MTRRfix16K_A0000 0x00000259
193 #define MSR_MTRRfix4K_C0000 0x00000268
194 #define MSR_MTRRfix4K_C8000 0x00000269
195 #define MSR_MTRRfix4K_D0000 0x0000026a
196 #define MSR_MTRRfix4K_D8000 0x0000026b
197 #define MSR_MTRRfix4K_E0000 0x0000026c
198 #define MSR_MTRRfix4K_E8000 0x0000026d
199 #define MSR_MTRRfix4K_F0000 0x0000026e
200 #define MSR_MTRRfix4K_F8000 0x0000026f
201 #define MSR_MTRRdefType 0x000002ff
203 #define MSR_IA32_CR_PAT 0x00000277
205 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
206 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
207 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
208 #define MSR_IA32_LASTINTFROMIP 0x000001dd
209 #define MSR_IA32_LASTINTTOIP 0x000001de
211 /* DEBUGCTLMSR bits (others vary by model): */
212 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
213 #define DEBUGCTLMSR_BTF_SHIFT 1
214 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
215 #define DEBUGCTLMSR_TR (1UL << 6)
216 #define DEBUGCTLMSR_BTS (1UL << 7)
217 #define DEBUGCTLMSR_BTINT (1UL << 8)
218 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
219 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
220 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
221 #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12)
222 #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14
223 #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT)
225 #define MSR_PEBS_FRONTEND 0x000003f7
227 #define MSR_IA32_POWER_CTL 0x000001fc
229 #define MSR_IA32_MC0_CTL 0x00000400
230 #define MSR_IA32_MC0_STATUS 0x00000401
231 #define MSR_IA32_MC0_ADDR 0x00000402
232 #define MSR_IA32_MC0_MISC 0x00000403
234 /* C-state Residency Counters */
235 #define MSR_PKG_C3_RESIDENCY 0x000003f8
236 #define MSR_PKG_C6_RESIDENCY 0x000003f9
237 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
238 #define MSR_PKG_C7_RESIDENCY 0x000003fa
239 #define MSR_CORE_C3_RESIDENCY 0x000003fc
240 #define MSR_CORE_C6_RESIDENCY 0x000003fd
241 #define MSR_CORE_C7_RESIDENCY 0x000003fe
242 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
243 #define MSR_PKG_C2_RESIDENCY 0x0000060d
244 #define MSR_PKG_C8_RESIDENCY 0x00000630
245 #define MSR_PKG_C9_RESIDENCY 0x00000631
246 #define MSR_PKG_C10_RESIDENCY 0x00000632
248 /* Interrupt Response Limit */
249 #define MSR_PKGC3_IRTL 0x0000060a
250 #define MSR_PKGC6_IRTL 0x0000060b
251 #define MSR_PKGC7_IRTL 0x0000060c
252 #define MSR_PKGC8_IRTL 0x00000633
253 #define MSR_PKGC9_IRTL 0x00000634
254 #define MSR_PKGC10_IRTL 0x00000635
256 /* Run Time Average Power Limiting (RAPL) Interface */
258 #define MSR_RAPL_POWER_UNIT 0x00000606
260 #define MSR_PKG_POWER_LIMIT 0x00000610
261 #define MSR_PKG_ENERGY_STATUS 0x00000611
262 #define MSR_PKG_PERF_STATUS 0x00000613
263 #define MSR_PKG_POWER_INFO 0x00000614
265 #define MSR_DRAM_POWER_LIMIT 0x00000618
266 #define MSR_DRAM_ENERGY_STATUS 0x00000619
267 #define MSR_DRAM_PERF_STATUS 0x0000061b
268 #define MSR_DRAM_POWER_INFO 0x0000061c
270 #define MSR_PP0_POWER_LIMIT 0x00000638
271 #define MSR_PP0_ENERGY_STATUS 0x00000639
272 #define MSR_PP0_POLICY 0x0000063a
273 #define MSR_PP0_PERF_STATUS 0x0000063b
275 #define MSR_PP1_POWER_LIMIT 0x00000640
276 #define MSR_PP1_ENERGY_STATUS 0x00000641
277 #define MSR_PP1_POLICY 0x00000642
279 /* Config TDP MSRs */
280 #define MSR_CONFIG_TDP_NOMINAL 0x00000648
281 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649
282 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
283 #define MSR_CONFIG_TDP_CONTROL 0x0000064B
284 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
286 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D
288 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
289 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659
290 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
291 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
293 #define MSR_CORE_C1_RES 0x00000660
294 #define MSR_MODULE_C6_RES_MS 0x00000664
296 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
297 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
299 #define MSR_ATOM_CORE_RATIOS 0x0000066a
300 #define MSR_ATOM_CORE_VIDS 0x0000066b
301 #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c
302 #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d
305 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
306 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
307 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
309 /* Hardware P state interface */
310 #define MSR_PPERF 0x0000064e
311 #define MSR_PERF_LIMIT_REASONS 0x0000064f
312 #define MSR_PM_ENABLE 0x00000770
313 #define MSR_HWP_CAPABILITIES 0x00000771
314 #define MSR_HWP_REQUEST_PKG 0x00000772
315 #define MSR_HWP_INTERRUPT 0x00000773
316 #define MSR_HWP_REQUEST 0x00000774
317 #define MSR_HWP_STATUS 0x00000777
320 #define HWP_BASE_BIT (1<<7)
321 #define HWP_NOTIFICATIONS_BIT (1<<8)
322 #define HWP_ACTIVITY_WINDOW_BIT (1<<9)
323 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10)
324 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11)
326 /* IA32_HWP_CAPABILITIES */
327 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff)
328 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff)
329 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff)
330 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff)
332 /* IA32_HWP_REQUEST */
333 #define HWP_MIN_PERF(x) (x & 0xff)
334 #define HWP_MAX_PERF(x) ((x & 0xff) << 8)
335 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
336 #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24)
337 #define HWP_EPP_PERFORMANCE 0x00
338 #define HWP_EPP_BALANCE_PERFORMANCE 0x80
339 #define HWP_EPP_BALANCE_POWERSAVE 0xC0
340 #define HWP_EPP_POWERSAVE 0xFF
341 #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32)
342 #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42)
344 /* IA32_HWP_STATUS */
345 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
346 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
348 /* IA32_HWP_INTERRUPT */
349 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
350 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
352 #define MSR_AMD64_MC0_MASK 0xc0010044
354 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
355 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
356 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
357 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
359 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
361 /* These are consecutive and not in the normal 4er MCE bank block */
362 #define MSR_IA32_MC0_CTL2 0x00000280
363 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
365 #define MSR_P6_PERFCTR0 0x000000c1
366 #define MSR_P6_PERFCTR1 0x000000c2
367 #define MSR_P6_EVNTSEL0 0x00000186
368 #define MSR_P6_EVNTSEL1 0x00000187
370 #define MSR_KNC_PERFCTR0 0x00000020
371 #define MSR_KNC_PERFCTR1 0x00000021
372 #define MSR_KNC_EVNTSEL0 0x00000028
373 #define MSR_KNC_EVNTSEL1 0x00000029
375 /* Alternative perfctr range with full access. */
376 #define MSR_IA32_PMC0 0x000004c1
378 /* AMD64 MSRs. Not complete. See the architecture manual for a more
381 #define MSR_AMD64_PATCH_LEVEL 0x0000008b
382 #define MSR_AMD64_TSC_RATIO 0xc0000104
383 #define MSR_AMD64_NB_CFG 0xc001001f
384 #define MSR_AMD64_CPUID_FN_1 0xc0011004
385 #define MSR_AMD64_PATCH_LOADER 0xc0010020
386 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
387 #define MSR_AMD64_OSVW_STATUS 0xc0010141
388 #define MSR_AMD64_LS_CFG 0xc0011020
389 #define MSR_AMD64_DC_CFG 0xc0011022
390 #define MSR_AMD64_BU_CFG2 0xc001102a
391 #define MSR_AMD64_IBSFETCHCTL 0xc0011030
392 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031
393 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
394 #define MSR_AMD64_IBSFETCH_REG_COUNT 3
395 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
396 #define MSR_AMD64_IBSOPCTL 0xc0011033
397 #define MSR_AMD64_IBSOPRIP 0xc0011034
398 #define MSR_AMD64_IBSOPDATA 0xc0011035
399 #define MSR_AMD64_IBSOPDATA2 0xc0011036
400 #define MSR_AMD64_IBSOPDATA3 0xc0011037
401 #define MSR_AMD64_IBSDCLINAD 0xc0011038
402 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039
403 #define MSR_AMD64_IBSOP_REG_COUNT 7
404 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
405 #define MSR_AMD64_IBSCTL 0xc001103a
406 #define MSR_AMD64_IBSBRTARGET 0xc001103b
407 #define MSR_AMD64_IBSOPDATA4 0xc001103d
408 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
409 #define MSR_AMD64_SEV 0xc0010131
410 #define MSR_AMD64_SEV_ENABLED_BIT 0
411 #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
413 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
416 #define MSR_F17H_IRPERF 0xc00000e9
419 #define MSR_F16H_L2I_PERF_CTL 0xc0010230
420 #define MSR_F16H_L2I_PERF_CTR 0xc0010231
421 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019
422 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a
423 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b
424 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027
427 #define MSR_F15H_PERF_CTL 0xc0010200
428 #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
429 #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
430 #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4)
431 #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6)
432 #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8)
433 #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10)
435 #define MSR_F15H_PERF_CTR 0xc0010201
436 #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR
437 #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2)
438 #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4)
439 #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6)
440 #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8)
441 #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10)
443 #define MSR_F15H_NB_PERF_CTL 0xc0010240
444 #define MSR_F15H_NB_PERF_CTR 0xc0010241
445 #define MSR_F15H_PTSC 0xc0010280
446 #define MSR_F15H_IC_CFG 0xc0011021
447 #define MSR_F15H_EX_CFG 0xc001102c
450 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
451 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
452 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
453 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
454 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
455 #define FAM10H_MMIO_CONF_BASE_SHIFT 20
456 #define MSR_FAM10H_NODE_ID 0xc001100c
457 #define MSR_F10H_DECFG 0xc0011029
458 #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1
459 #define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
462 #define MSR_K8_TOP_MEM1 0xc001001a
463 #define MSR_K8_TOP_MEM2 0xc001001d
464 #define MSR_K8_SYSCFG 0xc0010010
465 #define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23
466 #define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT)
467 #define MSR_K8_INT_PENDING_MSG 0xc0010055
468 /* C1E active bits in int pending message */
469 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000
470 #define MSR_K8_TSEG_ADDR 0xc0010112
471 #define MSR_K8_TSEG_MASK 0xc0010113
472 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
473 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
474 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
477 #define MSR_K7_EVNTSEL0 0xc0010000
478 #define MSR_K7_PERFCTR0 0xc0010004
479 #define MSR_K7_EVNTSEL1 0xc0010001
480 #define MSR_K7_PERFCTR1 0xc0010005
481 #define MSR_K7_EVNTSEL2 0xc0010002
482 #define MSR_K7_PERFCTR2 0xc0010006
483 #define MSR_K7_EVNTSEL3 0xc0010003
484 #define MSR_K7_PERFCTR3 0xc0010007
485 #define MSR_K7_CLK_CTL 0xc001001b
486 #define MSR_K7_HWCR 0xc0010015
487 #define MSR_K7_HWCR_SMMLOCK_BIT 0
488 #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)
489 #define MSR_K7_FID_VID_CTL 0xc0010041
490 #define MSR_K7_FID_VID_STATUS 0xc0010042
493 #define MSR_K6_WHCR 0xc0000082
494 #define MSR_K6_UWCCR 0xc0000085
495 #define MSR_K6_EPMR 0xc0000086
496 #define MSR_K6_PSOR 0xc0000087
497 #define MSR_K6_PFIR 0xc0000088
499 /* Centaur-Hauls/IDT defined MSRs. */
500 #define MSR_IDT_FCR1 0x00000107
501 #define MSR_IDT_FCR2 0x00000108
502 #define MSR_IDT_FCR3 0x00000109
503 #define MSR_IDT_FCR4 0x0000010a
505 #define MSR_IDT_MCR0 0x00000110
506 #define MSR_IDT_MCR1 0x00000111
507 #define MSR_IDT_MCR2 0x00000112
508 #define MSR_IDT_MCR3 0x00000113
509 #define MSR_IDT_MCR4 0x00000114
510 #define MSR_IDT_MCR5 0x00000115
511 #define MSR_IDT_MCR6 0x00000116
512 #define MSR_IDT_MCR7 0x00000117
513 #define MSR_IDT_MCR_CTRL 0x00000120
515 /* VIA Cyrix defined MSRs*/
516 #define MSR_VIA_FCR 0x00001107
517 #define MSR_VIA_LONGHAUL 0x0000110a
518 #define MSR_VIA_RNG 0x0000110b
519 #define MSR_VIA_BCR2 0x00001147
521 /* Transmeta defined MSRs */
522 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
523 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
524 #define MSR_TMTA_LRTI_READOUT 0x80868018
525 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
527 /* Intel defined MSRs. */
528 #define MSR_IA32_P5_MC_ADDR 0x00000000
529 #define MSR_IA32_P5_MC_TYPE 0x00000001
530 #define MSR_IA32_TSC 0x00000010
531 #define MSR_IA32_PLATFORM_ID 0x00000017
532 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
533 #define MSR_EBC_FREQUENCY_ID 0x0000002c
534 #define MSR_SMI_COUNT 0x00000034
535 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
536 #define MSR_IA32_TSC_ADJUST 0x0000003b
537 #define MSR_IA32_BNDCFGS 0x00000d90
539 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc
541 #define MSR_IA32_XSS 0x00000da0
543 #define FEATURE_CONTROL_LOCKED (1<<0)
544 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
545 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
546 #define FEATURE_CONTROL_LMCE (1<<20)
548 #define MSR_IA32_APICBASE 0x0000001b
549 #define MSR_IA32_APICBASE_BSP (1<<8)
550 #define MSR_IA32_APICBASE_ENABLE (1<<11)
551 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
553 #define MSR_IA32_TSCDEADLINE 0x000006e0
555 #define MSR_IA32_UCODE_WRITE 0x00000079
556 #define MSR_IA32_UCODE_REV 0x0000008b
558 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
559 #define MSR_IA32_SMBASE 0x0000009e
561 #define MSR_IA32_PERF_STATUS 0x00000198
562 #define MSR_IA32_PERF_CTL 0x00000199
563 #define INTEL_PERF_CTL_MASK 0xffff
564 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
565 #define MSR_AMD_PERF_STATUS 0xc0010063
566 #define MSR_AMD_PERF_CTL 0xc0010062
568 #define MSR_IA32_MPERF 0x000000e7
569 #define MSR_IA32_APERF 0x000000e8
571 #define MSR_IA32_THERM_CONTROL 0x0000019a
572 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
574 #define THERM_INT_HIGH_ENABLE (1 << 0)
575 #define THERM_INT_LOW_ENABLE (1 << 1)
576 #define THERM_INT_PLN_ENABLE (1 << 24)
578 #define MSR_IA32_THERM_STATUS 0x0000019c
580 #define THERM_STATUS_PROCHOT (1 << 0)
581 #define THERM_STATUS_POWER_LIMIT (1 << 10)
583 #define MSR_THERM2_CTL 0x0000019d
585 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
587 #define MSR_IA32_MISC_ENABLE 0x000001a0
589 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
591 #define MSR_MISC_FEATURE_CONTROL 0x000001a4
592 #define MSR_MISC_PWR_MGMT 0x000001aa
594 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
595 #define ENERGY_PERF_BIAS_PERFORMANCE 0
596 #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4
597 #define ENERGY_PERF_BIAS_NORMAL 6
598 #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8
599 #define ENERGY_PERF_BIAS_POWERSAVE 15
601 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
603 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
604 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
606 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
608 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
609 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
610 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
612 /* Thermal Thresholds Support */
613 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
614 #define THERM_SHIFT_THRESHOLD0 8
615 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
616 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
617 #define THERM_SHIFT_THRESHOLD1 16
618 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
619 #define THERM_STATUS_THRESHOLD0 (1 << 6)
620 #define THERM_LOG_THRESHOLD0 (1 << 7)
621 #define THERM_STATUS_THRESHOLD1 (1 << 8)
622 #define THERM_LOG_THRESHOLD1 (1 << 9)
624 /* MISC_ENABLE bits: architectural */
625 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
626 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
627 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1
628 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
629 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7
630 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
631 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
632 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
633 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
634 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
635 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
636 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
637 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
638 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
639 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
640 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
641 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
642 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
643 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
644 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
646 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
647 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
648 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
649 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3
650 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
651 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
652 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
653 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
654 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
655 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
656 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
657 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
658 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
659 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10
660 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
661 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
662 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
663 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13
664 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
665 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
666 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
667 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
668 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
669 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
670 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
671 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
672 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
673 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
674 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
675 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
676 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
678 /* MISC_FEATURES_ENABLES non-architectural features */
679 #define MSR_MISC_FEATURES_ENABLES 0x00000140
681 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0
682 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT)
683 #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1
685 #define MSR_IA32_TSC_DEADLINE 0x000006E0
688 #define MSR_TSX_FORCE_ABORT 0x0000010F
690 #define MSR_TFA_RTM_FORCE_ABORT_BIT 0
691 #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
693 /* P4/Xeon+ specific */
694 #define MSR_IA32_MCG_EAX 0x00000180
695 #define MSR_IA32_MCG_EBX 0x00000181
696 #define MSR_IA32_MCG_ECX 0x00000182
697 #define MSR_IA32_MCG_EDX 0x00000183
698 #define MSR_IA32_MCG_ESI 0x00000184
699 #define MSR_IA32_MCG_EDI 0x00000185
700 #define MSR_IA32_MCG_EBP 0x00000186
701 #define MSR_IA32_MCG_ESP 0x00000187
702 #define MSR_IA32_MCG_EFLAGS 0x00000188
703 #define MSR_IA32_MCG_EIP 0x00000189
704 #define MSR_IA32_MCG_RESERVED 0x0000018a
706 /* Pentium IV performance counter MSRs */
707 #define MSR_P4_BPU_PERFCTR0 0x00000300
708 #define MSR_P4_BPU_PERFCTR1 0x00000301
709 #define MSR_P4_BPU_PERFCTR2 0x00000302
710 #define MSR_P4_BPU_PERFCTR3 0x00000303
711 #define MSR_P4_MS_PERFCTR0 0x00000304
712 #define MSR_P4_MS_PERFCTR1 0x00000305
713 #define MSR_P4_MS_PERFCTR2 0x00000306
714 #define MSR_P4_MS_PERFCTR3 0x00000307
715 #define MSR_P4_FLAME_PERFCTR0 0x00000308
716 #define MSR_P4_FLAME_PERFCTR1 0x00000309
717 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
718 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
719 #define MSR_P4_IQ_PERFCTR0 0x0000030c
720 #define MSR_P4_IQ_PERFCTR1 0x0000030d
721 #define MSR_P4_IQ_PERFCTR2 0x0000030e
722 #define MSR_P4_IQ_PERFCTR3 0x0000030f
723 #define MSR_P4_IQ_PERFCTR4 0x00000310
724 #define MSR_P4_IQ_PERFCTR5 0x00000311
725 #define MSR_P4_BPU_CCCR0 0x00000360
726 #define MSR_P4_BPU_CCCR1 0x00000361
727 #define MSR_P4_BPU_CCCR2 0x00000362
728 #define MSR_P4_BPU_CCCR3 0x00000363
729 #define MSR_P4_MS_CCCR0 0x00000364
730 #define MSR_P4_MS_CCCR1 0x00000365
731 #define MSR_P4_MS_CCCR2 0x00000366
732 #define MSR_P4_MS_CCCR3 0x00000367
733 #define MSR_P4_FLAME_CCCR0 0x00000368
734 #define MSR_P4_FLAME_CCCR1 0x00000369
735 #define MSR_P4_FLAME_CCCR2 0x0000036a
736 #define MSR_P4_FLAME_CCCR3 0x0000036b
737 #define MSR_P4_IQ_CCCR0 0x0000036c
738 #define MSR_P4_IQ_CCCR1 0x0000036d
739 #define MSR_P4_IQ_CCCR2 0x0000036e
740 #define MSR_P4_IQ_CCCR3 0x0000036f
741 #define MSR_P4_IQ_CCCR4 0x00000370
742 #define MSR_P4_IQ_CCCR5 0x00000371
743 #define MSR_P4_ALF_ESCR0 0x000003ca
744 #define MSR_P4_ALF_ESCR1 0x000003cb
745 #define MSR_P4_BPU_ESCR0 0x000003b2
746 #define MSR_P4_BPU_ESCR1 0x000003b3
747 #define MSR_P4_BSU_ESCR0 0x000003a0
748 #define MSR_P4_BSU_ESCR1 0x000003a1
749 #define MSR_P4_CRU_ESCR0 0x000003b8
750 #define MSR_P4_CRU_ESCR1 0x000003b9
751 #define MSR_P4_CRU_ESCR2 0x000003cc
752 #define MSR_P4_CRU_ESCR3 0x000003cd
753 #define MSR_P4_CRU_ESCR4 0x000003e0
754 #define MSR_P4_CRU_ESCR5 0x000003e1
755 #define MSR_P4_DAC_ESCR0 0x000003a8
756 #define MSR_P4_DAC_ESCR1 0x000003a9
757 #define MSR_P4_FIRM_ESCR0 0x000003a4
758 #define MSR_P4_FIRM_ESCR1 0x000003a5
759 #define MSR_P4_FLAME_ESCR0 0x000003a6
760 #define MSR_P4_FLAME_ESCR1 0x000003a7
761 #define MSR_P4_FSB_ESCR0 0x000003a2
762 #define MSR_P4_FSB_ESCR1 0x000003a3
763 #define MSR_P4_IQ_ESCR0 0x000003ba
764 #define MSR_P4_IQ_ESCR1 0x000003bb
765 #define MSR_P4_IS_ESCR0 0x000003b4
766 #define MSR_P4_IS_ESCR1 0x000003b5
767 #define MSR_P4_ITLB_ESCR0 0x000003b6
768 #define MSR_P4_ITLB_ESCR1 0x000003b7
769 #define MSR_P4_IX_ESCR0 0x000003c8
770 #define MSR_P4_IX_ESCR1 0x000003c9
771 #define MSR_P4_MOB_ESCR0 0x000003aa
772 #define MSR_P4_MOB_ESCR1 0x000003ab
773 #define MSR_P4_MS_ESCR0 0x000003c0
774 #define MSR_P4_MS_ESCR1 0x000003c1
775 #define MSR_P4_PMH_ESCR0 0x000003ac
776 #define MSR_P4_PMH_ESCR1 0x000003ad
777 #define MSR_P4_RAT_ESCR0 0x000003bc
778 #define MSR_P4_RAT_ESCR1 0x000003bd
779 #define MSR_P4_SAAT_ESCR0 0x000003ae
780 #define MSR_P4_SAAT_ESCR1 0x000003af
781 #define MSR_P4_SSU_ESCR0 0x000003be
782 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
784 #define MSR_P4_TBPU_ESCR0 0x000003c2
785 #define MSR_P4_TBPU_ESCR1 0x000003c3
786 #define MSR_P4_TC_ESCR0 0x000003c4
787 #define MSR_P4_TC_ESCR1 0x000003c5
788 #define MSR_P4_U2L_ESCR0 0x000003b0
789 #define MSR_P4_U2L_ESCR1 0x000003b1
791 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
793 /* Intel Core-based CPU performance counters */
794 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
795 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
796 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
797 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
798 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
799 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
800 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
802 /* PERF_GLOBAL_OVF_CTL bits */
803 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55
804 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)
805 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62
806 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT)
807 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63
808 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT)
810 /* Geode defined MSRs */
811 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
814 #define MSR_IA32_VMX_BASIC 0x00000480
815 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
816 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
817 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
818 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
819 #define MSR_IA32_VMX_MISC 0x00000485
820 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
821 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
822 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
823 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
824 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
825 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
826 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
827 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
828 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
829 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
830 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
831 #define MSR_IA32_VMX_VMFUNC 0x00000491
833 /* VMX_BASIC bits and bitmasks */
834 #define VMX_BASIC_VMCS_SIZE_SHIFT 32
835 #define VMX_BASIC_TRUE_CTLS (1ULL << 55)
836 #define VMX_BASIC_64 0x0001000000000000LLU
837 #define VMX_BASIC_MEM_TYPE_SHIFT 50
838 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
839 #define VMX_BASIC_MEM_TYPE_WB 6LLU
840 #define VMX_BASIC_INOUT 0x0040000000000000LLU
842 /* MSR_IA32_VMX_MISC bits */
843 #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
844 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
845 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
848 #define MSR_VM_CR 0xc0010114
849 #define MSR_VM_IGNNE 0xc0010115
850 #define MSR_VM_HSAVE_PA 0xc0010117
852 #endif /* _ASM_X86_MSR_INDEX_H */