1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_MSR_INDEX_H
3 #define _ASM_X86_MSR_INDEX_H
5 #include <linux/bits.h>
8 * CPU model specific register (MSR) numbers.
10 * Do not add new entries to this file unless the definitions are shared
11 * between multiple compilation units.
14 /* x86-64 specific MSRs */
15 #define MSR_EFER 0xc0000080 /* extended feature register */
16 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
17 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
18 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
19 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
20 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
21 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
22 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
23 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
26 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
27 #define _EFER_LME 8 /* Long mode enable */
28 #define _EFER_LMA 10 /* Long mode active (read-only) */
29 #define _EFER_NX 11 /* No execute enable */
30 #define _EFER_SVME 12 /* Enable virtualization */
31 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
32 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
34 #define EFER_SCE (1<<_EFER_SCE)
35 #define EFER_LME (1<<_EFER_LME)
36 #define EFER_LMA (1<<_EFER_LMA)
37 #define EFER_NX (1<<_EFER_NX)
38 #define EFER_SVME (1<<_EFER_SVME)
39 #define EFER_LMSLE (1<<_EFER_LMSLE)
40 #define EFER_FFXSR (1<<_EFER_FFXSR)
42 /* Intel MSRs. Some also available on other CPUs */
44 #define MSR_TEST_CTRL 0x00000033
45 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29
46 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
48 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
49 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */
50 #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */
51 #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */
52 #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */
53 #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
55 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
56 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
58 #define MSR_PPIN_CTL 0x0000004e
59 #define MSR_PPIN 0x0000004f
61 #define MSR_IA32_PERFCTR0 0x000000c1
62 #define MSR_IA32_PERFCTR1 0x000000c2
63 #define MSR_FSB_FREQ 0x000000cd
64 #define MSR_PLATFORM_INFO 0x000000ce
65 #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31
66 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
68 #define MSR_IA32_UMWAIT_CONTROL 0xe1
69 #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0)
70 #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1)
72 * The time field is bit[31:2], but representing a 32bit value with
75 #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U)
77 /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
78 #define MSR_IA32_CORE_CAPS 0x000000cf
79 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5
80 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
82 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
83 #define NHM_C3_AUTO_DEMOTE (1UL << 25)
84 #define NHM_C1_AUTO_DEMOTE (1UL << 26)
85 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
86 #define SNB_C3_AUTO_UNDEMOTE (1UL << 27)
87 #define SNB_C1_AUTO_UNDEMOTE (1UL << 28)
89 #define MSR_MTRRcap 0x000000fe
91 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
92 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */
93 #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */
94 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */
95 #define ARCH_CAP_SSB_NO BIT(4) /*
96 * Not susceptible to Speculative Store Bypass
97 * attack, so no Speculative Store Bypass
100 #define ARCH_CAP_MDS_NO BIT(5) /*
102 * Microarchitectural Data
103 * Sampling (MDS) vulnerabilities.
105 #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /*
106 * The processor is not susceptible to a
107 * machine check error due to modifying the
108 * code page size along with either the
109 * physical address or cache type
110 * without TLB invalidation.
112 #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */
113 #define ARCH_CAP_TAA_NO BIT(8) /*
115 * TSX Async Abort (TAA) vulnerabilities.
118 #define MSR_IA32_FLUSH_CMD 0x0000010b
119 #define L1D_FLUSH BIT(0) /*
120 * Writeback and invalidate the
124 #define MSR_IA32_BBL_CR_CTL 0x00000119
125 #define MSR_IA32_BBL_CR_CTL3 0x0000011e
127 #define MSR_IA32_TSX_CTRL 0x00000122
128 #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
129 #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */
131 #define MSR_IA32_MCU_OPT_CTRL 0x00000123
132 #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */
133 #define RTM_ALLOW BIT(1) /* TSX development mode */
135 #define MSR_IA32_SYSENTER_CS 0x00000174
136 #define MSR_IA32_SYSENTER_ESP 0x00000175
137 #define MSR_IA32_SYSENTER_EIP 0x00000176
139 #define MSR_IA32_MCG_CAP 0x00000179
140 #define MSR_IA32_MCG_STATUS 0x0000017a
141 #define MSR_IA32_MCG_CTL 0x0000017b
142 #define MSR_ERROR_CONTROL 0x0000017f
143 #define MSR_IA32_MCG_EXT_CTL 0x000004d0
145 #define MSR_OFFCORE_RSP_0 0x000001a6
146 #define MSR_OFFCORE_RSP_1 0x000001a7
147 #define MSR_TURBO_RATIO_LIMIT 0x000001ad
148 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae
149 #define MSR_TURBO_RATIO_LIMIT2 0x000001af
151 #define MSR_LBR_SELECT 0x000001c8
152 #define MSR_LBR_TOS 0x000001c9
154 #define MSR_IA32_POWER_CTL 0x000001fc
155 #define MSR_IA32_POWER_CTL_BIT_EE 19
157 #define MSR_LBR_NHM_FROM 0x00000680
158 #define MSR_LBR_NHM_TO 0x000006c0
159 #define MSR_LBR_CORE_FROM 0x00000040
160 #define MSR_LBR_CORE_TO 0x00000060
162 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
163 #define LBR_INFO_MISPRED BIT_ULL(63)
164 #define LBR_INFO_IN_TX BIT_ULL(62)
165 #define LBR_INFO_ABORT BIT_ULL(61)
166 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
167 #define LBR_INFO_CYCLES 0xffff
168 #define LBR_INFO_BR_TYPE_OFFSET 56
169 #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET)
171 #define MSR_ARCH_LBR_CTL 0x000014ce
172 #define ARCH_LBR_CTL_LBREN BIT(0)
173 #define ARCH_LBR_CTL_CPL_OFFSET 1
174 #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
175 #define ARCH_LBR_CTL_STACK_OFFSET 3
176 #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET)
177 #define ARCH_LBR_CTL_FILTER_OFFSET 16
178 #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET)
179 #define MSR_ARCH_LBR_DEPTH 0x000014cf
180 #define MSR_ARCH_LBR_FROM_0 0x00001500
181 #define MSR_ARCH_LBR_TO_0 0x00001600
182 #define MSR_ARCH_LBR_INFO_0 0x00001200
184 #define MSR_IA32_PEBS_ENABLE 0x000003f1
185 #define MSR_PEBS_DATA_CFG 0x000003f2
186 #define MSR_IA32_DS_AREA 0x00000600
187 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
188 #define PERF_CAP_METRICS_IDX 15
189 #define PERF_CAP_PT_IDX 16
191 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
193 #define MSR_IA32_RTIT_CTL 0x00000570
194 #define RTIT_CTL_TRACEEN BIT(0)
195 #define RTIT_CTL_CYCLEACC BIT(1)
196 #define RTIT_CTL_OS BIT(2)
197 #define RTIT_CTL_USR BIT(3)
198 #define RTIT_CTL_PWR_EVT_EN BIT(4)
199 #define RTIT_CTL_FUP_ON_PTW BIT(5)
200 #define RTIT_CTL_FABRIC_EN BIT(6)
201 #define RTIT_CTL_CR3EN BIT(7)
202 #define RTIT_CTL_TOPA BIT(8)
203 #define RTIT_CTL_MTC_EN BIT(9)
204 #define RTIT_CTL_TSC_EN BIT(10)
205 #define RTIT_CTL_DISRETC BIT(11)
206 #define RTIT_CTL_PTW_EN BIT(12)
207 #define RTIT_CTL_BRANCH_EN BIT(13)
208 #define RTIT_CTL_EVENT_EN BIT(31)
209 #define RTIT_CTL_NOTNT BIT_ULL(55)
210 #define RTIT_CTL_MTC_RANGE_OFFSET 14
211 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
212 #define RTIT_CTL_CYC_THRESH_OFFSET 19
213 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
214 #define RTIT_CTL_PSB_FREQ_OFFSET 24
215 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
216 #define RTIT_CTL_ADDR0_OFFSET 32
217 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET)
218 #define RTIT_CTL_ADDR1_OFFSET 36
219 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET)
220 #define RTIT_CTL_ADDR2_OFFSET 40
221 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET)
222 #define RTIT_CTL_ADDR3_OFFSET 44
223 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET)
224 #define MSR_IA32_RTIT_STATUS 0x00000571
225 #define RTIT_STATUS_FILTEREN BIT(0)
226 #define RTIT_STATUS_CONTEXTEN BIT(1)
227 #define RTIT_STATUS_TRIGGEREN BIT(2)
228 #define RTIT_STATUS_BUFFOVF BIT(3)
229 #define RTIT_STATUS_ERROR BIT(4)
230 #define RTIT_STATUS_STOPPED BIT(5)
231 #define RTIT_STATUS_BYTECNT_OFFSET 32
232 #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET)
233 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
234 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
235 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
236 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
237 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
238 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
239 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
240 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
241 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
242 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
243 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
245 #define MSR_MTRRfix64K_00000 0x00000250
246 #define MSR_MTRRfix16K_80000 0x00000258
247 #define MSR_MTRRfix16K_A0000 0x00000259
248 #define MSR_MTRRfix4K_C0000 0x00000268
249 #define MSR_MTRRfix4K_C8000 0x00000269
250 #define MSR_MTRRfix4K_D0000 0x0000026a
251 #define MSR_MTRRfix4K_D8000 0x0000026b
252 #define MSR_MTRRfix4K_E0000 0x0000026c
253 #define MSR_MTRRfix4K_E8000 0x0000026d
254 #define MSR_MTRRfix4K_F0000 0x0000026e
255 #define MSR_MTRRfix4K_F8000 0x0000026f
256 #define MSR_MTRRdefType 0x000002ff
258 #define MSR_IA32_CR_PAT 0x00000277
260 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
261 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
262 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
263 #define MSR_IA32_LASTINTFROMIP 0x000001dd
264 #define MSR_IA32_LASTINTTOIP 0x000001de
266 #define MSR_IA32_PASID 0x00000d93
267 #define MSR_IA32_PASID_VALID BIT_ULL(31)
269 /* DEBUGCTLMSR bits (others vary by model): */
270 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
271 #define DEBUGCTLMSR_BTF_SHIFT 1
272 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
273 #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2)
274 #define DEBUGCTLMSR_TR (1UL << 6)
275 #define DEBUGCTLMSR_BTS (1UL << 7)
276 #define DEBUGCTLMSR_BTINT (1UL << 8)
277 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
278 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
279 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
280 #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12)
281 #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14
282 #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT)
284 #define MSR_PEBS_FRONTEND 0x000003f7
286 #define MSR_IA32_MC0_CTL 0x00000400
287 #define MSR_IA32_MC0_STATUS 0x00000401
288 #define MSR_IA32_MC0_ADDR 0x00000402
289 #define MSR_IA32_MC0_MISC 0x00000403
291 /* C-state Residency Counters */
292 #define MSR_PKG_C3_RESIDENCY 0x000003f8
293 #define MSR_PKG_C6_RESIDENCY 0x000003f9
294 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
295 #define MSR_PKG_C7_RESIDENCY 0x000003fa
296 #define MSR_CORE_C3_RESIDENCY 0x000003fc
297 #define MSR_CORE_C6_RESIDENCY 0x000003fd
298 #define MSR_CORE_C7_RESIDENCY 0x000003fe
299 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
300 #define MSR_PKG_C2_RESIDENCY 0x0000060d
301 #define MSR_PKG_C8_RESIDENCY 0x00000630
302 #define MSR_PKG_C9_RESIDENCY 0x00000631
303 #define MSR_PKG_C10_RESIDENCY 0x00000632
305 /* Interrupt Response Limit */
306 #define MSR_PKGC3_IRTL 0x0000060a
307 #define MSR_PKGC6_IRTL 0x0000060b
308 #define MSR_PKGC7_IRTL 0x0000060c
309 #define MSR_PKGC8_IRTL 0x00000633
310 #define MSR_PKGC9_IRTL 0x00000634
311 #define MSR_PKGC10_IRTL 0x00000635
313 /* Run Time Average Power Limiting (RAPL) Interface */
315 #define MSR_VR_CURRENT_CONFIG 0x00000601
316 #define MSR_RAPL_POWER_UNIT 0x00000606
318 #define MSR_PKG_POWER_LIMIT 0x00000610
319 #define MSR_PKG_ENERGY_STATUS 0x00000611
320 #define MSR_PKG_PERF_STATUS 0x00000613
321 #define MSR_PKG_POWER_INFO 0x00000614
323 #define MSR_DRAM_POWER_LIMIT 0x00000618
324 #define MSR_DRAM_ENERGY_STATUS 0x00000619
325 #define MSR_DRAM_PERF_STATUS 0x0000061b
326 #define MSR_DRAM_POWER_INFO 0x0000061c
328 #define MSR_PP0_POWER_LIMIT 0x00000638
329 #define MSR_PP0_ENERGY_STATUS 0x00000639
330 #define MSR_PP0_POLICY 0x0000063a
331 #define MSR_PP0_PERF_STATUS 0x0000063b
333 #define MSR_PP1_POWER_LIMIT 0x00000640
334 #define MSR_PP1_ENERGY_STATUS 0x00000641
335 #define MSR_PP1_POLICY 0x00000642
337 #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299
338 #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a
339 #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b
341 /* Config TDP MSRs */
342 #define MSR_CONFIG_TDP_NOMINAL 0x00000648
343 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649
344 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
345 #define MSR_CONFIG_TDP_CONTROL 0x0000064B
346 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
348 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D
350 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
351 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659
352 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
353 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
355 #define MSR_CORE_C1_RES 0x00000660
356 #define MSR_MODULE_C6_RES_MS 0x00000664
358 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
359 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
361 #define MSR_ATOM_CORE_RATIOS 0x0000066a
362 #define MSR_ATOM_CORE_VIDS 0x0000066b
363 #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c
364 #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d
366 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
367 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
368 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
370 /* Control-flow Enforcement Technology MSRs */
371 #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */
372 #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */
373 #define CET_SHSTK_EN BIT_ULL(0)
374 #define CET_WRSS_EN BIT_ULL(1)
375 #define CET_ENDBR_EN BIT_ULL(2)
376 #define CET_LEG_IW_EN BIT_ULL(3)
377 #define CET_NO_TRACK_EN BIT_ULL(4)
378 #define CET_SUPPRESS_DISABLE BIT_ULL(5)
379 #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))
380 #define CET_SUPPRESS BIT_ULL(10)
381 #define CET_WAIT_ENDBR BIT_ULL(11)
383 #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */
384 #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */
385 #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */
386 #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */
387 #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */
389 /* Hardware P state interface */
390 #define MSR_PPERF 0x0000064e
391 #define MSR_PERF_LIMIT_REASONS 0x0000064f
392 #define MSR_PM_ENABLE 0x00000770
393 #define MSR_HWP_CAPABILITIES 0x00000771
394 #define MSR_HWP_REQUEST_PKG 0x00000772
395 #define MSR_HWP_INTERRUPT 0x00000773
396 #define MSR_HWP_REQUEST 0x00000774
397 #define MSR_HWP_STATUS 0x00000777
400 #define HWP_BASE_BIT (1<<7)
401 #define HWP_NOTIFICATIONS_BIT (1<<8)
402 #define HWP_ACTIVITY_WINDOW_BIT (1<<9)
403 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10)
404 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11)
406 /* IA32_HWP_CAPABILITIES */
407 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff)
408 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff)
409 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff)
410 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff)
412 /* IA32_HWP_REQUEST */
413 #define HWP_MIN_PERF(x) (x & 0xff)
414 #define HWP_MAX_PERF(x) ((x & 0xff) << 8)
415 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
416 #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24)
417 #define HWP_EPP_PERFORMANCE 0x00
418 #define HWP_EPP_BALANCE_PERFORMANCE 0x80
419 #define HWP_EPP_BALANCE_POWERSAVE 0xC0
420 #define HWP_EPP_POWERSAVE 0xFF
421 #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32)
422 #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42)
424 /* IA32_HWP_STATUS */
425 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
426 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
428 /* IA32_HWP_INTERRUPT */
429 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
430 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
432 #define MSR_AMD64_MC0_MASK 0xc0010044
434 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
435 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
436 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
437 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
439 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
441 /* These are consecutive and not in the normal 4er MCE bank block */
442 #define MSR_IA32_MC0_CTL2 0x00000280
443 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
445 #define MSR_P6_PERFCTR0 0x000000c1
446 #define MSR_P6_PERFCTR1 0x000000c2
447 #define MSR_P6_EVNTSEL0 0x00000186
448 #define MSR_P6_EVNTSEL1 0x00000187
450 #define MSR_KNC_PERFCTR0 0x00000020
451 #define MSR_KNC_PERFCTR1 0x00000021
452 #define MSR_KNC_EVNTSEL0 0x00000028
453 #define MSR_KNC_EVNTSEL1 0x00000029
455 /* Alternative perfctr range with full access. */
456 #define MSR_IA32_PMC0 0x000004c1
458 /* Auto-reload via MSR instead of DS area */
459 #define MSR_RELOAD_PMC0 0x000014c1
460 #define MSR_RELOAD_FIXED_CTR0 0x00001309
463 * AMD64 MSRs. Not complete. See the architecture manual for a more
466 #define MSR_AMD64_PATCH_LEVEL 0x0000008b
467 #define MSR_AMD64_TSC_RATIO 0xc0000104
468 #define MSR_AMD64_NB_CFG 0xc001001f
469 #define MSR_AMD64_PATCH_LOADER 0xc0010020
470 #define MSR_AMD_PERF_CTL 0xc0010062
471 #define MSR_AMD_PERF_STATUS 0xc0010063
472 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
473 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
474 #define MSR_AMD64_OSVW_STATUS 0xc0010141
475 #define MSR_AMD_PPIN_CTL 0xc00102f0
476 #define MSR_AMD_PPIN 0xc00102f1
477 #define MSR_AMD64_CPUID_FN_1 0xc0011004
478 #define MSR_AMD64_LS_CFG 0xc0011020
479 #define MSR_AMD64_DC_CFG 0xc0011022
480 #define MSR_AMD64_BU_CFG2 0xc001102a
481 #define MSR_AMD64_IBSFETCHCTL 0xc0011030
482 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031
483 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
484 #define MSR_AMD64_IBSFETCH_REG_COUNT 3
485 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
486 #define MSR_AMD64_IBSOPCTL 0xc0011033
487 #define MSR_AMD64_IBSOPRIP 0xc0011034
488 #define MSR_AMD64_IBSOPDATA 0xc0011035
489 #define MSR_AMD64_IBSOPDATA2 0xc0011036
490 #define MSR_AMD64_IBSOPDATA3 0xc0011037
491 #define MSR_AMD64_IBSDCLINAD 0xc0011038
492 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039
493 #define MSR_AMD64_IBSOP_REG_COUNT 7
494 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
495 #define MSR_AMD64_IBSCTL 0xc001103a
496 #define MSR_AMD64_IBSBRTARGET 0xc001103b
497 #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c
498 #define MSR_AMD64_IBSOPDATA4 0xc001103d
499 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
500 #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b
501 #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e
502 #define MSR_AMD64_SEV_ES_GHCB 0xc0010130
503 #define MSR_AMD64_SEV 0xc0010131
504 #define MSR_AMD64_SEV_ENABLED_BIT 0
505 #define MSR_AMD64_SEV_ES_ENABLED_BIT 1
506 #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
507 #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
509 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
511 /* AMD Collaborative Processor Performance Control MSRs */
512 #define MSR_AMD_CPPC_CAP1 0xc00102b0
513 #define MSR_AMD_CPPC_ENABLE 0xc00102b1
514 #define MSR_AMD_CPPC_CAP2 0xc00102b2
515 #define MSR_AMD_CPPC_REQ 0xc00102b3
516 #define MSR_AMD_CPPC_STATUS 0xc00102b4
518 #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff)
519 #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff)
520 #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff)
521 #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff)
523 #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0)
524 #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8)
525 #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16)
526 #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24)
529 #define MSR_F17H_IRPERF 0xc00000e9
532 #define MSR_F16H_L2I_PERF_CTL 0xc0010230
533 #define MSR_F16H_L2I_PERF_CTR 0xc0010231
534 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019
535 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a
536 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b
537 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027
540 #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
541 #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
542 #define MSR_F15H_PERF_CTL 0xc0010200
543 #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
544 #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
545 #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4)
546 #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6)
547 #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8)
548 #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10)
550 #define MSR_F15H_PERF_CTR 0xc0010201
551 #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR
552 #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2)
553 #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4)
554 #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6)
555 #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8)
556 #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10)
558 #define MSR_F15H_NB_PERF_CTL 0xc0010240
559 #define MSR_F15H_NB_PERF_CTR 0xc0010241
560 #define MSR_F15H_PTSC 0xc0010280
561 #define MSR_F15H_IC_CFG 0xc0011021
562 #define MSR_F15H_EX_CFG 0xc001102c
565 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
566 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
567 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
568 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
569 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
570 #define FAM10H_MMIO_CONF_BASE_SHIFT 20
571 #define MSR_FAM10H_NODE_ID 0xc001100c
572 #define MSR_F10H_DECFG 0xc0011029
573 #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1
574 #define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
577 #define MSR_K8_TOP_MEM1 0xc001001a
578 #define MSR_K8_TOP_MEM2 0xc001001d
579 #define MSR_AMD64_SYSCFG 0xc0010010
580 #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23
581 #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT)
582 #define MSR_K8_INT_PENDING_MSG 0xc0010055
583 /* C1E active bits in int pending message */
584 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000
585 #define MSR_K8_TSEG_ADDR 0xc0010112
586 #define MSR_K8_TSEG_MASK 0xc0010113
587 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
588 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
589 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
592 #define MSR_K7_EVNTSEL0 0xc0010000
593 #define MSR_K7_PERFCTR0 0xc0010004
594 #define MSR_K7_EVNTSEL1 0xc0010001
595 #define MSR_K7_PERFCTR1 0xc0010005
596 #define MSR_K7_EVNTSEL2 0xc0010002
597 #define MSR_K7_PERFCTR2 0xc0010006
598 #define MSR_K7_EVNTSEL3 0xc0010003
599 #define MSR_K7_PERFCTR3 0xc0010007
600 #define MSR_K7_CLK_CTL 0xc001001b
601 #define MSR_K7_HWCR 0xc0010015
602 #define MSR_K7_HWCR_SMMLOCK_BIT 0
603 #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)
604 #define MSR_K7_HWCR_IRPERF_EN_BIT 30
605 #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
606 #define MSR_K7_FID_VID_CTL 0xc0010041
607 #define MSR_K7_FID_VID_STATUS 0xc0010042
610 #define MSR_K6_WHCR 0xc0000082
611 #define MSR_K6_UWCCR 0xc0000085
612 #define MSR_K6_EPMR 0xc0000086
613 #define MSR_K6_PSOR 0xc0000087
614 #define MSR_K6_PFIR 0xc0000088
616 /* Centaur-Hauls/IDT defined MSRs. */
617 #define MSR_IDT_FCR1 0x00000107
618 #define MSR_IDT_FCR2 0x00000108
619 #define MSR_IDT_FCR3 0x00000109
620 #define MSR_IDT_FCR4 0x0000010a
622 #define MSR_IDT_MCR0 0x00000110
623 #define MSR_IDT_MCR1 0x00000111
624 #define MSR_IDT_MCR2 0x00000112
625 #define MSR_IDT_MCR3 0x00000113
626 #define MSR_IDT_MCR4 0x00000114
627 #define MSR_IDT_MCR5 0x00000115
628 #define MSR_IDT_MCR6 0x00000116
629 #define MSR_IDT_MCR7 0x00000117
630 #define MSR_IDT_MCR_CTRL 0x00000120
632 /* VIA Cyrix defined MSRs*/
633 #define MSR_VIA_FCR 0x00001107
634 #define MSR_VIA_LONGHAUL 0x0000110a
635 #define MSR_VIA_RNG 0x0000110b
636 #define MSR_VIA_BCR2 0x00001147
638 /* Transmeta defined MSRs */
639 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
640 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
641 #define MSR_TMTA_LRTI_READOUT 0x80868018
642 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
644 /* Intel defined MSRs. */
645 #define MSR_IA32_P5_MC_ADDR 0x00000000
646 #define MSR_IA32_P5_MC_TYPE 0x00000001
647 #define MSR_IA32_TSC 0x00000010
648 #define MSR_IA32_PLATFORM_ID 0x00000017
649 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
650 #define MSR_EBC_FREQUENCY_ID 0x0000002c
651 #define MSR_SMI_COUNT 0x00000034
653 /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */
654 #define MSR_IA32_FEAT_CTL 0x0000003a
655 #define FEAT_CTL_LOCKED BIT(0)
656 #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1)
657 #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2)
658 #define FEAT_CTL_SGX_LC_ENABLED BIT(17)
659 #define FEAT_CTL_SGX_ENABLED BIT(18)
660 #define FEAT_CTL_LMCE_ENABLED BIT(20)
662 #define MSR_IA32_TSC_ADJUST 0x0000003b
663 #define MSR_IA32_BNDCFGS 0x00000d90
665 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc
667 #define MSR_IA32_XFD 0x000001c4
668 #define MSR_IA32_XFD_ERR 0x000001c5
669 #define MSR_IA32_XSS 0x00000da0
671 #define MSR_IA32_APICBASE 0x0000001b
672 #define MSR_IA32_APICBASE_BSP (1<<8)
673 #define MSR_IA32_APICBASE_ENABLE (1<<11)
674 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
676 #define MSR_IA32_UCODE_WRITE 0x00000079
677 #define MSR_IA32_UCODE_REV 0x0000008b
679 /* Intel SGX Launch Enclave Public Key Hash MSRs */
680 #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
681 #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
682 #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
683 #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
685 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
686 #define MSR_IA32_SMBASE 0x0000009e
688 #define MSR_IA32_PERF_STATUS 0x00000198
689 #define MSR_IA32_PERF_CTL 0x00000199
690 #define INTEL_PERF_CTL_MASK 0xffff
692 #define MSR_IA32_MPERF 0x000000e7
693 #define MSR_IA32_APERF 0x000000e8
695 #define MSR_IA32_THERM_CONTROL 0x0000019a
696 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
698 #define THERM_INT_HIGH_ENABLE (1 << 0)
699 #define THERM_INT_LOW_ENABLE (1 << 1)
700 #define THERM_INT_PLN_ENABLE (1 << 24)
702 #define MSR_IA32_THERM_STATUS 0x0000019c
704 #define THERM_STATUS_PROCHOT (1 << 0)
705 #define THERM_STATUS_POWER_LIMIT (1 << 10)
707 #define MSR_THERM2_CTL 0x0000019d
709 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
711 #define MSR_IA32_MISC_ENABLE 0x000001a0
713 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
715 #define MSR_MISC_FEATURE_CONTROL 0x000001a4
716 #define MSR_MISC_PWR_MGMT 0x000001aa
718 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
719 #define ENERGY_PERF_BIAS_PERFORMANCE 0
720 #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4
721 #define ENERGY_PERF_BIAS_NORMAL 6
722 #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8
723 #define ENERGY_PERF_BIAS_POWERSAVE 15
725 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
727 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
728 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
729 #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26)
731 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
733 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
734 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
735 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
736 #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25)
738 /* Thermal Thresholds Support */
739 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
740 #define THERM_SHIFT_THRESHOLD0 8
741 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
742 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
743 #define THERM_SHIFT_THRESHOLD1 16
744 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
745 #define THERM_STATUS_THRESHOLD0 (1 << 6)
746 #define THERM_LOG_THRESHOLD0 (1 << 7)
747 #define THERM_STATUS_THRESHOLD1 (1 << 8)
748 #define THERM_LOG_THRESHOLD1 (1 << 9)
750 /* MISC_ENABLE bits: architectural */
751 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
752 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
753 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1
754 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
755 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7
756 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
757 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
758 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
759 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
760 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
761 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
762 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
763 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
764 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
765 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
766 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
767 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
768 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
769 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
770 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
772 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
773 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
774 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
775 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3
776 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
777 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
778 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
779 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
780 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
781 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
782 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
783 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
784 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
785 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10
786 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
787 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
788 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
789 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13
790 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
791 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
792 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
793 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
794 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
795 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
796 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
797 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
798 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
799 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
800 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
801 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
802 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
804 /* MISC_FEATURES_ENABLES non-architectural features */
805 #define MSR_MISC_FEATURES_ENABLES 0x00000140
807 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0
808 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT)
809 #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1
811 #define MSR_IA32_TSC_DEADLINE 0x000006E0
814 #define MSR_TSX_FORCE_ABORT 0x0000010F
816 #define MSR_TFA_RTM_FORCE_ABORT_BIT 0
817 #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
818 #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1
819 #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT)
820 #define MSR_TFA_SDV_ENABLE_RTM_BIT 2
821 #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT)
823 /* P4/Xeon+ specific */
824 #define MSR_IA32_MCG_EAX 0x00000180
825 #define MSR_IA32_MCG_EBX 0x00000181
826 #define MSR_IA32_MCG_ECX 0x00000182
827 #define MSR_IA32_MCG_EDX 0x00000183
828 #define MSR_IA32_MCG_ESI 0x00000184
829 #define MSR_IA32_MCG_EDI 0x00000185
830 #define MSR_IA32_MCG_EBP 0x00000186
831 #define MSR_IA32_MCG_ESP 0x00000187
832 #define MSR_IA32_MCG_EFLAGS 0x00000188
833 #define MSR_IA32_MCG_EIP 0x00000189
834 #define MSR_IA32_MCG_RESERVED 0x0000018a
836 /* Pentium IV performance counter MSRs */
837 #define MSR_P4_BPU_PERFCTR0 0x00000300
838 #define MSR_P4_BPU_PERFCTR1 0x00000301
839 #define MSR_P4_BPU_PERFCTR2 0x00000302
840 #define MSR_P4_BPU_PERFCTR3 0x00000303
841 #define MSR_P4_MS_PERFCTR0 0x00000304
842 #define MSR_P4_MS_PERFCTR1 0x00000305
843 #define MSR_P4_MS_PERFCTR2 0x00000306
844 #define MSR_P4_MS_PERFCTR3 0x00000307
845 #define MSR_P4_FLAME_PERFCTR0 0x00000308
846 #define MSR_P4_FLAME_PERFCTR1 0x00000309
847 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
848 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
849 #define MSR_P4_IQ_PERFCTR0 0x0000030c
850 #define MSR_P4_IQ_PERFCTR1 0x0000030d
851 #define MSR_P4_IQ_PERFCTR2 0x0000030e
852 #define MSR_P4_IQ_PERFCTR3 0x0000030f
853 #define MSR_P4_IQ_PERFCTR4 0x00000310
854 #define MSR_P4_IQ_PERFCTR5 0x00000311
855 #define MSR_P4_BPU_CCCR0 0x00000360
856 #define MSR_P4_BPU_CCCR1 0x00000361
857 #define MSR_P4_BPU_CCCR2 0x00000362
858 #define MSR_P4_BPU_CCCR3 0x00000363
859 #define MSR_P4_MS_CCCR0 0x00000364
860 #define MSR_P4_MS_CCCR1 0x00000365
861 #define MSR_P4_MS_CCCR2 0x00000366
862 #define MSR_P4_MS_CCCR3 0x00000367
863 #define MSR_P4_FLAME_CCCR0 0x00000368
864 #define MSR_P4_FLAME_CCCR1 0x00000369
865 #define MSR_P4_FLAME_CCCR2 0x0000036a
866 #define MSR_P4_FLAME_CCCR3 0x0000036b
867 #define MSR_P4_IQ_CCCR0 0x0000036c
868 #define MSR_P4_IQ_CCCR1 0x0000036d
869 #define MSR_P4_IQ_CCCR2 0x0000036e
870 #define MSR_P4_IQ_CCCR3 0x0000036f
871 #define MSR_P4_IQ_CCCR4 0x00000370
872 #define MSR_P4_IQ_CCCR5 0x00000371
873 #define MSR_P4_ALF_ESCR0 0x000003ca
874 #define MSR_P4_ALF_ESCR1 0x000003cb
875 #define MSR_P4_BPU_ESCR0 0x000003b2
876 #define MSR_P4_BPU_ESCR1 0x000003b3
877 #define MSR_P4_BSU_ESCR0 0x000003a0
878 #define MSR_P4_BSU_ESCR1 0x000003a1
879 #define MSR_P4_CRU_ESCR0 0x000003b8
880 #define MSR_P4_CRU_ESCR1 0x000003b9
881 #define MSR_P4_CRU_ESCR2 0x000003cc
882 #define MSR_P4_CRU_ESCR3 0x000003cd
883 #define MSR_P4_CRU_ESCR4 0x000003e0
884 #define MSR_P4_CRU_ESCR5 0x000003e1
885 #define MSR_P4_DAC_ESCR0 0x000003a8
886 #define MSR_P4_DAC_ESCR1 0x000003a9
887 #define MSR_P4_FIRM_ESCR0 0x000003a4
888 #define MSR_P4_FIRM_ESCR1 0x000003a5
889 #define MSR_P4_FLAME_ESCR0 0x000003a6
890 #define MSR_P4_FLAME_ESCR1 0x000003a7
891 #define MSR_P4_FSB_ESCR0 0x000003a2
892 #define MSR_P4_FSB_ESCR1 0x000003a3
893 #define MSR_P4_IQ_ESCR0 0x000003ba
894 #define MSR_P4_IQ_ESCR1 0x000003bb
895 #define MSR_P4_IS_ESCR0 0x000003b4
896 #define MSR_P4_IS_ESCR1 0x000003b5
897 #define MSR_P4_ITLB_ESCR0 0x000003b6
898 #define MSR_P4_ITLB_ESCR1 0x000003b7
899 #define MSR_P4_IX_ESCR0 0x000003c8
900 #define MSR_P4_IX_ESCR1 0x000003c9
901 #define MSR_P4_MOB_ESCR0 0x000003aa
902 #define MSR_P4_MOB_ESCR1 0x000003ab
903 #define MSR_P4_MS_ESCR0 0x000003c0
904 #define MSR_P4_MS_ESCR1 0x000003c1
905 #define MSR_P4_PMH_ESCR0 0x000003ac
906 #define MSR_P4_PMH_ESCR1 0x000003ad
907 #define MSR_P4_RAT_ESCR0 0x000003bc
908 #define MSR_P4_RAT_ESCR1 0x000003bd
909 #define MSR_P4_SAAT_ESCR0 0x000003ae
910 #define MSR_P4_SAAT_ESCR1 0x000003af
911 #define MSR_P4_SSU_ESCR0 0x000003be
912 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
914 #define MSR_P4_TBPU_ESCR0 0x000003c2
915 #define MSR_P4_TBPU_ESCR1 0x000003c3
916 #define MSR_P4_TC_ESCR0 0x000003c4
917 #define MSR_P4_TC_ESCR1 0x000003c5
918 #define MSR_P4_U2L_ESCR0 0x000003b0
919 #define MSR_P4_U2L_ESCR1 0x000003b1
921 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
923 /* Intel Core-based CPU performance counters */
924 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
925 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
926 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
927 #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c
928 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
929 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
930 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
931 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
933 #define MSR_PERF_METRICS 0x00000329
935 /* PERF_GLOBAL_OVF_CTL bits */
936 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55
937 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)
938 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62
939 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT)
940 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63
941 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT)
943 /* Geode defined MSRs */
944 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
947 #define MSR_IA32_VMX_BASIC 0x00000480
948 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
949 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
950 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
951 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
952 #define MSR_IA32_VMX_MISC 0x00000485
953 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
954 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
955 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
956 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
957 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
958 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
959 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
960 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
961 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
962 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
963 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
964 #define MSR_IA32_VMX_VMFUNC 0x00000491
966 /* VMX_BASIC bits and bitmasks */
967 #define VMX_BASIC_VMCS_SIZE_SHIFT 32
968 #define VMX_BASIC_TRUE_CTLS (1ULL << 55)
969 #define VMX_BASIC_64 0x0001000000000000LLU
970 #define VMX_BASIC_MEM_TYPE_SHIFT 50
971 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
972 #define VMX_BASIC_MEM_TYPE_WB 6LLU
973 #define VMX_BASIC_INOUT 0x0040000000000000LLU
975 /* MSR_IA32_VMX_MISC bits */
976 #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
977 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
978 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
981 #define MSR_VM_CR 0xc0010114
982 #define MSR_VM_IGNNE 0xc0010115
983 #define MSR_VM_HSAVE_PA 0xc0010117
985 /* Hardware Feedback Interface */
986 #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0
987 #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1
989 #endif /* _ASM_X86_MSR_INDEX_H */