1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_MSHYPER_H
3 #define _ASM_X86_MSHYPER_H
5 #include <linux/types.h>
6 #include <linux/atomic.h>
9 #include <asm/hyperv-tlfs.h>
10 #include <asm/nospec-branch.h>
12 #define VP_INVAL U32_MAX
14 struct ms_hyperv_info {
23 extern struct ms_hyperv_info ms_hyperv;
26 * Generate the guest ID.
29 static inline __u64 generate_guest_id(__u64 d_info1, __u64 kernel_version,
34 guest_id = (((__u64)HV_LINUX_VENDOR_ID) << 48);
35 guest_id |= (d_info1 << 48);
36 guest_id |= (kernel_version << 16);
43 /* Free the message slot and signal end-of-message if required */
44 static inline void vmbus_signal_eom(struct hv_message *msg, u32 old_msg_type)
47 * On crash we're reading some other CPU's message page and we need
48 * to be careful: this other CPU may already had cleared the header
49 * and the host may already had delivered some other message there.
50 * In case we blindly write msg->header.message_type we're going
51 * to lose it. We can still lose a message of the same type but
52 * we count on the fact that there can only be one
53 * CHANNELMSG_UNLOAD_RESPONSE and we don't care about other messages
56 if (cmpxchg(&msg->header.message_type, old_msg_type,
57 HVMSG_NONE) != old_msg_type)
61 * Make sure the write to MessageType (ie set to
62 * HVMSG_NONE) happens before we read the
63 * MessagePending and EOMing. Otherwise, the EOMing
64 * will not deliver any more messages since there is
69 if (msg->header.message_flags.msg_pending) {
71 * This will cause message queue rescan to
72 * possibly deliver another msg from the
75 wrmsrl(HV_X64_MSR_EOM, 0);
79 #define hv_init_timer(timer, tick) \
80 wrmsrl(HV_X64_MSR_STIMER0_COUNT + (2*timer), tick)
81 #define hv_init_timer_config(timer, val) \
82 wrmsrl(HV_X64_MSR_STIMER0_CONFIG + (2*timer), val)
84 #define hv_get_simp(val) rdmsrl(HV_X64_MSR_SIMP, val)
85 #define hv_set_simp(val) wrmsrl(HV_X64_MSR_SIMP, val)
87 #define hv_get_siefp(val) rdmsrl(HV_X64_MSR_SIEFP, val)
88 #define hv_set_siefp(val) wrmsrl(HV_X64_MSR_SIEFP, val)
90 #define hv_get_synic_state(val) rdmsrl(HV_X64_MSR_SCONTROL, val)
91 #define hv_set_synic_state(val) wrmsrl(HV_X64_MSR_SCONTROL, val)
93 #define hv_get_vp_index(index) rdmsrl(HV_X64_MSR_VP_INDEX, index)
95 #define hv_get_synint_state(int_num, val) \
96 rdmsrl(HV_X64_MSR_SINT0 + int_num, val)
97 #define hv_set_synint_state(int_num, val) \
98 wrmsrl(HV_X64_MSR_SINT0 + int_num, val)
100 #define hv_get_crash_ctl(val) \
101 rdmsrl(HV_X64_MSR_CRASH_CTL, val)
103 void hyperv_callback_vector(void);
104 void hyperv_reenlightenment_vector(void);
105 #ifdef CONFIG_TRACING
106 #define trace_hyperv_callback_vector hyperv_callback_vector
108 void hyperv_vector_handler(struct pt_regs *regs);
109 void hv_setup_vmbus_irq(void (*handler)(void));
110 void hv_remove_vmbus_irq(void);
112 void hv_setup_kexec_handler(void (*handler)(void));
113 void hv_remove_kexec_handler(void);
114 void hv_setup_crash_handler(void (*handler)(struct pt_regs *regs));
115 void hv_remove_crash_handler(void);
118 * Routines for stimer0 Direct Mode handling.
119 * On x86/x64, there are no percpu actions to take.
121 void hv_stimer0_vector_handler(struct pt_regs *regs);
122 void hv_stimer0_callback_vector(void);
123 int hv_setup_stimer0_irq(int *irq, int *vector, void (*handler)(void));
124 void hv_remove_stimer0_irq(int irq);
126 static inline void hv_enable_stimer0_percpu_irq(int irq) {}
127 static inline void hv_disable_stimer0_percpu_irq(int irq) {}
130 #if IS_ENABLED(CONFIG_HYPERV)
131 extern struct clocksource *hyperv_cs;
132 extern void *hv_hypercall_pg;
133 extern void __percpu **hyperv_pcpu_input_arg;
135 static inline u64 hv_do_hypercall(u64 control, void *input, void *output)
137 u64 input_address = input ? virt_to_phys(input) : 0;
138 u64 output_address = output ? virt_to_phys(output) : 0;
142 if (!hv_hypercall_pg)
145 __asm__ __volatile__("mov %4, %%r8\n"
147 : "=a" (hv_status), ASM_CALL_CONSTRAINT,
148 "+c" (control), "+d" (input_address)
149 : "r" (output_address),
150 THUNK_TARGET(hv_hypercall_pg)
151 : "cc", "memory", "r8", "r9", "r10", "r11");
153 u32 input_address_hi = upper_32_bits(input_address);
154 u32 input_address_lo = lower_32_bits(input_address);
155 u32 output_address_hi = upper_32_bits(output_address);
156 u32 output_address_lo = lower_32_bits(output_address);
158 if (!hv_hypercall_pg)
161 __asm__ __volatile__(CALL_NOSPEC
163 "+c" (input_address_lo), ASM_CALL_CONSTRAINT
165 "b" (input_address_hi),
166 "D"(output_address_hi), "S"(output_address_lo),
167 THUNK_TARGET(hv_hypercall_pg)
173 /* Fast hypercall with 8 bytes of input and no output */
174 static inline u64 hv_do_fast_hypercall8(u16 code, u64 input1)
176 u64 hv_status, control = (u64)code | HV_HYPERCALL_FAST_BIT;
180 __asm__ __volatile__(CALL_NOSPEC
181 : "=a" (hv_status), ASM_CALL_CONSTRAINT,
182 "+c" (control), "+d" (input1)
183 : THUNK_TARGET(hv_hypercall_pg)
184 : "cc", "r8", "r9", "r10", "r11");
188 u32 input1_hi = upper_32_bits(input1);
189 u32 input1_lo = lower_32_bits(input1);
191 __asm__ __volatile__ (CALL_NOSPEC
197 THUNK_TARGET(hv_hypercall_pg)
198 : "cc", "edi", "esi");
204 /* Fast hypercall with 16 bytes of input */
205 static inline u64 hv_do_fast_hypercall16(u16 code, u64 input1, u64 input2)
207 u64 hv_status, control = (u64)code | HV_HYPERCALL_FAST_BIT;
211 __asm__ __volatile__("mov %4, %%r8\n"
213 : "=a" (hv_status), ASM_CALL_CONSTRAINT,
214 "+c" (control), "+d" (input1)
216 THUNK_TARGET(hv_hypercall_pg)
217 : "cc", "r8", "r9", "r10", "r11");
221 u32 input1_hi = upper_32_bits(input1);
222 u32 input1_lo = lower_32_bits(input1);
223 u32 input2_hi = upper_32_bits(input2);
224 u32 input2_lo = lower_32_bits(input2);
226 __asm__ __volatile__ (CALL_NOSPEC
228 "+c"(input1_lo), ASM_CALL_CONSTRAINT
229 : "A" (control), "b" (input1_hi),
230 "D"(input2_hi), "S"(input2_lo),
231 THUNK_TARGET(hv_hypercall_pg)
239 * Rep hypercalls. Callers of this functions are supposed to ensure that
240 * rep_count and varhead_size comply with Hyper-V hypercall definition.
242 static inline u64 hv_do_rep_hypercall(u16 code, u16 rep_count, u16 varhead_size,
243 void *input, void *output)
249 control |= (u64)varhead_size << HV_HYPERCALL_VARHEAD_OFFSET;
250 control |= (u64)rep_count << HV_HYPERCALL_REP_COMP_OFFSET;
253 status = hv_do_hypercall(control, input, output);
254 if ((status & HV_HYPERCALL_RESULT_MASK) != HV_STATUS_SUCCESS)
257 /* Bits 32-43 of status have 'Reps completed' data. */
258 rep_comp = (status & HV_HYPERCALL_REP_COMP_MASK) >>
259 HV_HYPERCALL_REP_COMP_OFFSET;
261 control &= ~HV_HYPERCALL_REP_START_MASK;
262 control |= (u64)rep_comp << HV_HYPERCALL_REP_START_OFFSET;
264 touch_nmi_watchdog();
265 } while (rep_comp < rep_count);
271 * Hypervisor's notion of virtual processor ID is different from
272 * Linux' notion of CPU ID. This information can only be retrieved
273 * in the context of the calling CPU. Setup a map for easy access
274 * to this information.
276 extern u32 *hv_vp_index;
277 extern u32 hv_max_vp_index;
278 extern struct hv_vp_assist_page **hv_vp_assist_page;
280 static inline struct hv_vp_assist_page *hv_get_vp_assist_page(unsigned int cpu)
282 if (!hv_vp_assist_page)
285 return hv_vp_assist_page[cpu];
289 * hv_cpu_number_to_vp_number() - Map CPU to VP.
290 * @cpu_number: CPU number in Linux terms
292 * This function returns the mapping between the Linux processor
293 * number and the hypervisor's virtual processor number, useful
294 * in making hypercalls and such that talk about specific
297 * Return: Virtual processor number in Hyper-V terms
299 static inline int hv_cpu_number_to_vp_number(int cpu_number)
301 return hv_vp_index[cpu_number];
304 static inline int cpumask_to_vpset(struct hv_vpset *vpset,
305 const struct cpumask *cpus)
307 int cpu, vcpu, vcpu_bank, vcpu_offset, nr_bank = 1;
309 /* valid_bank_mask can represent up to 64 banks */
310 if (hv_max_vp_index / 64 >= 64)
314 * Clear all banks up to the maximum possible bank as hv_tlb_flush_ex
315 * structs are not cleared between calls, we risk flushing unneeded
318 for (vcpu_bank = 0; vcpu_bank <= hv_max_vp_index / 64; vcpu_bank++)
319 vpset->bank_contents[vcpu_bank] = 0;
322 * Some banks may end up being empty but this is acceptable.
324 for_each_cpu(cpu, cpus) {
325 vcpu = hv_cpu_number_to_vp_number(cpu);
326 if (vcpu == VP_INVAL)
328 vcpu_bank = vcpu / 64;
329 vcpu_offset = vcpu % 64;
330 __set_bit(vcpu_offset, (unsigned long *)
331 &vpset->bank_contents[vcpu_bank]);
332 if (vcpu_bank >= nr_bank)
333 nr_bank = vcpu_bank + 1;
335 vpset->valid_bank_mask = GENMASK_ULL(nr_bank - 1, 0);
339 void __init hyperv_init(void);
340 void hyperv_setup_mmu_ops(void);
341 void hyperv_report_panic(struct pt_regs *regs, long err);
342 void hyperv_report_panic_msg(phys_addr_t pa, size_t size);
343 bool hv_is_hyperv_initialized(void);
344 void hyperv_cleanup(void);
346 void hyperv_reenlightenment_intr(struct pt_regs *regs);
347 void set_hv_tscchange_cb(void (*cb)(void));
348 void clear_hv_tscchange_cb(void);
349 void hyperv_stop_tsc_emulation(void);
352 void hv_apic_init(void);
354 static inline void hv_apic_init(void) {}
357 #else /* CONFIG_HYPERV */
358 static inline void hyperv_init(void) {}
359 static inline bool hv_is_hyperv_initialized(void) { return false; }
360 static inline void hyperv_cleanup(void) {}
361 static inline void hyperv_setup_mmu_ops(void) {}
362 static inline void set_hv_tscchange_cb(void (*cb)(void)) {}
363 static inline void clear_hv_tscchange_cb(void) {}
364 static inline void hyperv_stop_tsc_emulation(void) {};
365 static inline struct hv_vp_assist_page *hv_get_vp_assist_page(unsigned int cpu)
369 #endif /* CONFIG_HYPERV */
371 #ifdef CONFIG_HYPERV_TSCPAGE
372 struct ms_hyperv_tsc_page *hv_get_tsc_page(void);
373 static inline u64 hv_read_tsc_page_tsc(const struct ms_hyperv_tsc_page *tsc_pg,
380 * The protocol for reading Hyper-V TSC page is specified in Hypervisor
381 * Top-Level Functional Specification ver. 3.0 and above. To get the
382 * reference time we must do the following:
383 * - READ ReferenceTscSequence
384 * A special '0' value indicates the time source is unreliable and we
385 * need to use something else. The currently published specification
386 * versions (up to 4.0b) contain a mistake and wrongly claim '-1'
387 * instead of '0' as the special value, see commit c35b82ef0294.
389 * ((RDTSC() * ReferenceTscScale) >> 64) + ReferenceTscOffset
390 * - READ ReferenceTscSequence again. In case its value has changed
391 * since our first reading we need to discard ReferenceTime and repeat
392 * the whole sequence as the hypervisor was updating the page in
396 sequence = READ_ONCE(tsc_pg->tsc_sequence);
400 * Make sure we read sequence before we read other values from
405 scale = READ_ONCE(tsc_pg->tsc_scale);
406 offset = READ_ONCE(tsc_pg->tsc_offset);
407 *cur_tsc = rdtsc_ordered();
410 * Make sure we read sequence after we read all other values
415 } while (READ_ONCE(tsc_pg->tsc_sequence) != sequence);
417 return mul_u64_u64_shr(*cur_tsc, scale, 64) + offset;
420 static inline u64 hv_read_tsc_page(const struct ms_hyperv_tsc_page *tsc_pg)
424 return hv_read_tsc_page_tsc(tsc_pg, &cur_tsc);
428 static inline struct ms_hyperv_tsc_page *hv_get_tsc_page(void)
433 static inline u64 hv_read_tsc_page_tsc(const struct ms_hyperv_tsc_page *tsc_pg,