5 * Copyright 2004 James Cleverdon, IBM.
6 * Subject to the GNU Public License, v.2
8 * Generic APIC InterProcessor Interrupt code.
10 * Moved to include file by James Cleverdon from
11 * arch/x86-64/kernel/smp.c
13 * Copyrights from kernel/smp.c:
15 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
16 * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
17 * (c) 2002,2003 Andi Kleen, SuSE Labs.
18 * Subject to the GNU Public License, v.2
21 #include <asm/hw_irq.h>
26 * the following functions deal with sending IPIs between CPUs.
28 * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
31 static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector,
34 unsigned int icr = shortcut | dest;
38 icr |= APIC_DM_FIXED | vector;
47 static inline int __prepare_ICR2(unsigned int mask)
49 return SET_APIC_DEST_FIELD(mask);
52 static inline void __xapic_wait_icr_idle(void)
54 while (native_apic_mem_read(APIC_ICR) & APIC_ICR_BUSY)
59 __default_send_IPI_shortcut(unsigned int shortcut,
60 int vector, unsigned int dest)
63 * Subtle. In the case of the 'never do double writes' workaround
64 * we have to lock out interrupts to be safe. As we don't care
65 * of the value read we use an atomic rmw access to avoid costly
66 * cli/sti. Otherwise we use an even cheaper single atomic write
74 __xapic_wait_icr_idle();
77 * No need to touch the target chip field
79 cfg = __prepare_ICR(shortcut, vector, dest);
82 * Send the IPI. The write to APIC_ICR fires this off.
84 native_apic_mem_write(APIC_ICR, cfg);
88 * This is used to send an IPI with no shorthand notation (the destination is
89 * specified in bits 56 to 63 of the ICR).
92 __default_send_IPI_dest_field(unsigned int mask, int vector, unsigned int dest)
99 if (unlikely(vector == NMI_VECTOR))
100 safe_apic_wait_icr_idle();
102 __xapic_wait_icr_idle();
105 * prepare target chip field
107 cfg = __prepare_ICR2(mask);
108 native_apic_mem_write(APIC_ICR2, cfg);
113 cfg = __prepare_ICR(0, vector, dest);
116 * Send the IPI. The write to APIC_ICR fires this off.
118 native_apic_mem_write(APIC_ICR, cfg);
122 default_send_IPI_mask_sequence(const struct cpumask *mask, int vector)
124 unsigned long query_cpu;
128 * Hack. The clustered APIC addressing mode doesn't allow us to send
129 * to an arbitrary mask, so I do a unicast to each CPU instead.
132 local_irq_save(flags);
133 for_each_cpu(query_cpu, mask) {
134 __default_send_IPI_dest_field(per_cpu(x86_cpu_to_apicid,
135 query_cpu), vector, APIC_DEST_PHYSICAL);
137 local_irq_restore(flags);
141 default_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
143 unsigned int this_cpu = smp_processor_id();
144 unsigned int query_cpu;
147 /* See Hack comment above */
149 local_irq_save(flags);
150 for_each_cpu(query_cpu, mask) {
151 if (query_cpu == this_cpu)
153 __default_send_IPI_dest_field(per_cpu(x86_cpu_to_apicid,
154 query_cpu), vector, APIC_DEST_PHYSICAL);
156 local_irq_restore(flags);
159 #endif /* _ASM_X86_IPI_H */