arch/x86/include/asm/hyperv-tlfs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 /*
   4  * This file contains definitions from Hyper-V Hypervisor Top-Level Functional
   5  * Specification (TLFS):
   6  * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
   7  */
   8
   9 #ifndef _ASM_X86_HYPERV_TLFS_H
  10 #define _ASM_X86_HYPERV_TLFS_H
  11
  12 #include <linux/types.h>
  13 #include <asm/page.h>
  14 /*
  15  * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
  16  * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
  17  */
  18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS   0x40000000
  19 #define HYPERV_CPUID_INTERFACE                  0x40000001
  20 #define HYPERV_CPUID_VERSION                    0x40000002
  21 #define HYPERV_CPUID_FEATURES                   0x40000003
  22 #define HYPERV_CPUID_ENLIGHTMENT_INFO           0x40000004
  23 #define HYPERV_CPUID_IMPLEMENT_LIMITS           0x40000005
  24 #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES    0x40000007
  25 #define HYPERV_CPUID_NESTED_FEATURES            0x4000000A
  26 #define HYPERV_CPUID_ISOLATION_CONFIG           0x4000000C
  27
  28 #define HYPERV_CPUID_VIRT_STACK_INTERFACE       0x40000081
  29 #define HYPERV_VS_INTERFACE_EAX_SIGNATURE       0x31235356  /* "VS#1" */
  30
  31 #define HYPERV_CPUID_VIRT_STACK_PROPERTIES      0x40000082
  32 /* Support for the extended IOAPIC RTE format */
  33 #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE    BIT(2)
  34
  35 #define HYPERV_HYPERVISOR_PRESENT_BIT           0x80000000
  36 #define HYPERV_CPUID_MIN                        0x40000005
  37 #define HYPERV_CPUID_MAX                        0x4000ffff
  38
  39 /*
  40  * Group D Features.  The bit assignments are custom to each architecture.
  41  * On x86/x64 these are HYPERV_CPUID_FEATURES.EDX bits.
  42  */
  43 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */
  44 #define HV_X64_MWAIT_AVAILABLE                          BIT(0)
  45 /* Guest debugging support is available */
  46 #define HV_X64_GUEST_DEBUGGING_AVAILABLE                BIT(1)
  47 /* Performance Monitor support is available*/
  48 #define HV_X64_PERF_MONITOR_AVAILABLE                   BIT(2)
  49 /* Support for physical CPU dynamic partitioning events is available*/
  50 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE       BIT(3)
  51 /*
  52  * Support for passing hypercall input parameter block via XMM
  53  * registers is available
  54  */
  55 #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE            BIT(4)
  56 /* Support for a virtual guest idle state is available */
  57 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE               BIT(5)
  58 /* Frequency MSRs available */
  59 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE             BIT(8)
  60 /* Crash MSR available */
  61 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE            BIT(10)
  62 /* Support for debug MSRs available */
  63 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE                 BIT(11)
  64 /* Support for extended gva ranges for flush hypercalls available */
  65 #define HV_FEATURE_EXT_GVA_RANGES_FLUSH                 BIT(14)
  66 /*
  67  * Support for returning hypercall output block via XMM
  68  * registers is available
  69  */
  70 #define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE           BIT(15)
  71 /* stimer Direct Mode is available */
  72 #define HV_STIMER_DIRECT_MODE_AVAILABLE                 BIT(19)
  73
  74 /*
  75  * Implementation recommendations. Indicates which behaviors the hypervisor
  76  * recommends the OS implement for optimal performance.
  77  * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits.
  78  */
  79 /*
  80  * Recommend using hypercall for address space switches rather
  81  * than MOV to CR3 instruction
  82  */
  83 #define HV_X64_AS_SWITCH_RECOMMENDED                    BIT(0)
  84 /* Recommend using hypercall for local TLB flushes rather
  85  * than INVLPG or MOV to CR3 instructions */
  86 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED              BIT(1)
  87 /*
  88  * Recommend using hypercall for remote TLB flushes rather
  89  * than inter-processor interrupts
  90  */
  91 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED             BIT(2)
  92 /*
  93  * Recommend using MSRs for accessing APIC registers
  94  * EOI, ICR and TPR rather than their memory-mapped counterparts
  95  */
  96 #define HV_X64_APIC_ACCESS_RECOMMENDED                  BIT(3)
  97 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
  98 #define HV_X64_SYSTEM_RESET_RECOMMENDED                 BIT(4)
  99 /*
 100  * Recommend using relaxed timing for this partition. If used,
 101  * the VM should disable any watchdog timeouts that rely on the
 102  * timely delivery of external interrupts
 103  */
 104 #define HV_X64_RELAXED_TIMING_RECOMMENDED               BIT(5)
 105
 106 /*
 107  * Recommend not using Auto End-Of-Interrupt feature
 108  */
 109 #define HV_DEPRECATING_AEOI_RECOMMENDED                 BIT(9)
 110
 111 /*
 112  * Recommend using cluster IPI hypercalls.
 113  */
 114 #define HV_X64_CLUSTER_IPI_RECOMMENDED                  BIT(10)
 115
 116 /* Recommend using the newer ExProcessorMasks interface */
 117 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED           BIT(11)
 118
 119 /* Recommend using enlightened VMCS */
 120 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED             BIT(14)
 121
 122 /*
 123  * CPU management features identification.
 124  * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits.
 125  */
 126 #define HV_X64_START_LOGICAL_PROCESSOR                  BIT(0)
 127 #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR            BIT(1)
 128 #define HV_X64_PERFORMANCE_COUNTER_SYNC                 BIT(2)
 129 #define HV_X64_RESERVED_IDENTITY_BIT                    BIT(31)
 130
 131 /*
 132  * Virtual processor will never share a physical core with another virtual
 133  * processor, except for virtual processors that are reported as sibling SMT
 134  * threads.
 135  */
 136 #define HV_X64_NO_NONARCH_CORESHARING                   BIT(18)
 137
 138 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */
 139 #define HV_X64_NESTED_DIRECT_FLUSH                      BIT(17)
 140 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH               BIT(18)
 141 #define HV_X64_NESTED_MSR_BITMAP                        BIT(19)
 142
 143 /* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */
 144 #define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL           BIT(0)
 145
 146 /*
 147  * This is specific to AMD and specifies that enlightened TLB flush is
 148  * supported. If guest opts in to this feature, ASID invalidations only
 149  * flushes gva -> hpa mapping entries. To flush the TLB entries derived
 150  * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace
 151  * or HvFlushGuestPhysicalAddressList).
 152  */
 153 #define HV_X64_NESTED_ENLIGHTENED_TLB                   BIT(22)
 154
 155 /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */
 156 #define HV_PARAVISOR_PRESENT                            BIT(0)
 157
 158 /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */
 159 #define HV_ISOLATION_TYPE                               GENMASK(3, 0)
 160 #define HV_SHARED_GPA_BOUNDARY_ACTIVE                   BIT(5)
 161 #define HV_SHARED_GPA_BOUNDARY_BITS                     GENMASK(11, 6)
 162
 163 enum hv_isolation_type {
 164         HV_ISOLATION_TYPE_NONE  = 0,
 165         HV_ISOLATION_TYPE_VBS   = 1,
 166         HV_ISOLATION_TYPE_SNP   = 2
 167 };
 168
 169 /* Hyper-V specific model specific registers (MSRs) */
 170
 171 /* MSR used to identify the guest OS. */
 172 #define HV_X64_MSR_GUEST_OS_ID                  0x40000000
 173
 174 /* MSR used to setup pages used to communicate with the hypervisor. */
 175 #define HV_X64_MSR_HYPERCALL                    0x40000001
 176
 177 /* MSR used to provide vcpu index */
 178 #define HV_REGISTER_VP_INDEX                    0x40000002
 179
 180 /* MSR used to reset the guest OS. */
 181 #define HV_X64_MSR_RESET                        0x40000003
 182
 183 /* MSR used to provide vcpu runtime in 100ns units */
 184 #define HV_X64_MSR_VP_RUNTIME                   0x40000010
 185
 186 /* MSR used to read the per-partition time reference counter */
 187 #define HV_REGISTER_TIME_REF_COUNT              0x40000020
 188
 189 /* A partition's reference time stamp counter (TSC) page */
 190 #define HV_REGISTER_REFERENCE_TSC               0x40000021
 191
 192 /* MSR used to retrieve the TSC frequency */
 193 #define HV_X64_MSR_TSC_FREQUENCY                0x40000022
 194
 195 /* MSR used to retrieve the local APIC timer frequency */
 196 #define HV_X64_MSR_APIC_FREQUENCY               0x40000023
 197
 198 /* Define the virtual APIC registers */
 199 #define HV_X64_MSR_EOI                          0x40000070
 200 #define HV_X64_MSR_ICR                          0x40000071
 201 #define HV_X64_MSR_TPR                          0x40000072
 202 #define HV_X64_MSR_VP_ASSIST_PAGE               0x40000073
 203
 204 /* Define synthetic interrupt controller model specific registers. */
 205 #define HV_REGISTER_SCONTROL                    0x40000080
 206 #define HV_REGISTER_SVERSION                    0x40000081
 207 #define HV_REGISTER_SIEFP                       0x40000082
 208 #define HV_REGISTER_SIMP                        0x40000083
 209 #define HV_REGISTER_EOM                         0x40000084
 210 #define HV_REGISTER_SINT0                       0x40000090
 211 #define HV_REGISTER_SINT1                       0x40000091
 212 #define HV_REGISTER_SINT2                       0x40000092
 213 #define HV_REGISTER_SINT3                       0x40000093
 214 #define HV_REGISTER_SINT4                       0x40000094
 215 #define HV_REGISTER_SINT5                       0x40000095
 216 #define HV_REGISTER_SINT6                       0x40000096
 217 #define HV_REGISTER_SINT7                       0x40000097
 218 #define HV_REGISTER_SINT8                       0x40000098
 219 #define HV_REGISTER_SINT9                       0x40000099
 220 #define HV_REGISTER_SINT10                      0x4000009A
 221 #define HV_REGISTER_SINT11                      0x4000009B
 222 #define HV_REGISTER_SINT12                      0x4000009C
 223 #define HV_REGISTER_SINT13                      0x4000009D
 224 #define HV_REGISTER_SINT14                      0x4000009E
 225 #define HV_REGISTER_SINT15                      0x4000009F
 226
 227 /*
 228  * Synthetic Timer MSRs. Four timers per vcpu.
 229  */
 230 #define HV_REGISTER_STIMER0_CONFIG              0x400000B0
 231 #define HV_REGISTER_STIMER0_COUNT               0x400000B1
 232 #define HV_REGISTER_STIMER1_CONFIG              0x400000B2
 233 #define HV_REGISTER_STIMER1_COUNT               0x400000B3
 234 #define HV_REGISTER_STIMER2_CONFIG              0x400000B4
 235 #define HV_REGISTER_STIMER2_COUNT               0x400000B5
 236 #define HV_REGISTER_STIMER3_CONFIG              0x400000B6
 237 #define HV_REGISTER_STIMER3_COUNT               0x400000B7
 238
 239 /* Hyper-V guest idle MSR */
 240 #define HV_X64_MSR_GUEST_IDLE                   0x400000F0
 241
 242 /* Hyper-V guest crash notification MSR's */
 243 #define HV_REGISTER_CRASH_P0                    0x40000100
 244 #define HV_REGISTER_CRASH_P1                    0x40000101
 245 #define HV_REGISTER_CRASH_P2                    0x40000102
 246 #define HV_REGISTER_CRASH_P3                    0x40000103
 247 #define HV_REGISTER_CRASH_P4                    0x40000104
 248 #define HV_REGISTER_CRASH_CTL                   0x40000105
 249
 250 /* TSC emulation after migration */
 251 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL      0x40000106
 252 #define HV_X64_MSR_TSC_EMULATION_CONTROL        0x40000107
 253 #define HV_X64_MSR_TSC_EMULATION_STATUS         0x40000108
 254
 255 /* TSC invariant control */
 256 #define HV_X64_MSR_TSC_INVARIANT_CONTROL        0x40000118
 257
 258 /* HV_X64_MSR_TSC_INVARIANT_CONTROL bits */
 259 #define HV_EXPOSE_INVARIANT_TSC         BIT_ULL(0)
 260
 261 /* Register name aliases for temporary compatibility */
 262 #define HV_X64_MSR_STIMER0_COUNT        HV_REGISTER_STIMER0_COUNT
 263 #define HV_X64_MSR_STIMER0_CONFIG       HV_REGISTER_STIMER0_CONFIG
 264 #define HV_X64_MSR_STIMER1_COUNT        HV_REGISTER_STIMER1_COUNT
 265 #define HV_X64_MSR_STIMER1_CONFIG       HV_REGISTER_STIMER1_CONFIG
 266 #define HV_X64_MSR_STIMER2_COUNT        HV_REGISTER_STIMER2_COUNT
 267 #define HV_X64_MSR_STIMER2_CONFIG       HV_REGISTER_STIMER2_CONFIG
 268 #define HV_X64_MSR_STIMER3_COUNT        HV_REGISTER_STIMER3_COUNT
 269 #define HV_X64_MSR_STIMER3_CONFIG       HV_REGISTER_STIMER3_CONFIG
 270 #define HV_X64_MSR_SCONTROL             HV_REGISTER_SCONTROL
 271 #define HV_X64_MSR_SVERSION             HV_REGISTER_SVERSION
 272 #define HV_X64_MSR_SIMP                 HV_REGISTER_SIMP
 273 #define HV_X64_MSR_SIEFP                HV_REGISTER_SIEFP
 274 #define HV_X64_MSR_VP_INDEX             HV_REGISTER_VP_INDEX
 275 #define HV_X64_MSR_EOM                  HV_REGISTER_EOM
 276 #define HV_X64_MSR_SINT0                HV_REGISTER_SINT0
 277 #define HV_X64_MSR_SINT15               HV_REGISTER_SINT15
 278 #define HV_X64_MSR_CRASH_P0             HV_REGISTER_CRASH_P0
 279 #define HV_X64_MSR_CRASH_P1             HV_REGISTER_CRASH_P1
 280 #define HV_X64_MSR_CRASH_P2             HV_REGISTER_CRASH_P2
 281 #define HV_X64_MSR_CRASH_P3             HV_REGISTER_CRASH_P3
 282 #define HV_X64_MSR_CRASH_P4             HV_REGISTER_CRASH_P4
 283 #define HV_X64_MSR_CRASH_CTL            HV_REGISTER_CRASH_CTL
 284 #define HV_X64_MSR_TIME_REF_COUNT       HV_REGISTER_TIME_REF_COUNT
 285 #define HV_X64_MSR_REFERENCE_TSC        HV_REGISTER_REFERENCE_TSC
 286
 287 /* Hyper-V memory host visibility */
 288 enum hv_mem_host_visibility {
 289         VMBUS_PAGE_NOT_VISIBLE          = 0,
 290         VMBUS_PAGE_VISIBLE_READ_ONLY    = 1,
 291         VMBUS_PAGE_VISIBLE_READ_WRITE   = 3
 292 };
 293
 294 /* HvCallModifySparseGpaPageHostVisibility hypercall */
 295 #define HV_MAX_MODIFY_GPA_REP_COUNT     ((PAGE_SIZE / sizeof(u64)) - 2)
 296 struct hv_gpa_range_for_visibility {
 297         u64 partition_id;
 298         u32 host_visibility:2;
 299         u32 reserved0:30;
 300         u32 reserved1;
 301         u64 gpa_page_list[HV_MAX_MODIFY_GPA_REP_COUNT];
 302 } __packed;
 303
 304 /*
 305  * Declare the MSR used to setup pages used to communicate with the hypervisor.
 306  */
 307 union hv_x64_msr_hypercall_contents {
 308         u64 as_uint64;
 309         struct {
 310                 u64 enable:1;
 311                 u64 reserved:11;
 312                 u64 guest_physical_address:52;
 313         } __packed;
 314 };
 315
 316 union hv_vp_assist_msr_contents {
 317         u64 as_uint64;
 318         struct {
 319                 u64 enable:1;
 320                 u64 reserved:11;
 321                 u64 pfn:52;
 322         } __packed;
 323 };
 324
 325 struct hv_reenlightenment_control {
 326         __u64 vector:8;
 327         __u64 reserved1:8;
 328         __u64 enabled:1;
 329         __u64 reserved2:15;
 330         __u64 target_vp:32;
 331 }  __packed;
 332
 333 struct hv_tsc_emulation_control {
 334         __u64 enabled:1;
 335         __u64 reserved:63;
 336 } __packed;
 337
 338 struct hv_tsc_emulation_status {
 339         __u64 inprogress:1;
 340         __u64 reserved:63;
 341 } __packed;
 342
 343 #define HV_X64_MSR_HYPERCALL_ENABLE             0x00000001
 344 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
 345 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK  \
 346                 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
 347
 348 #define HV_X64_MSR_CRASH_PARAMS         \
 349                 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
 350
 351 #define HV_IPI_LOW_VECTOR       0x10
 352 #define HV_IPI_HIGH_VECTOR      0xff
 353
 354 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE        0x00000001
 355 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12
 356 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK  \
 357                 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
 358
 359 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */
 360 #define HV_X64_ENLIGHTENED_VMCS_VERSION         0xff
 361
 362 #define HV_X64_MSR_TSC_REFERENCE_ENABLE         0x00000001
 363 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT  12
 364
 365 /* Number of XMM registers used in hypercall input/output */
 366 #define HV_HYPERCALL_MAX_XMM_REGISTERS          6
 367
 368 struct hv_nested_enlightenments_control {
 369         struct {
 370                 __u32 directhypercall:1;
 371                 __u32 reserved:31;
 372         } features;
 373         struct {
 374                 __u32 reserved;
 375         } hypercallControls;
 376 } __packed;
 377
 378 /* Define virtual processor assist page structure. */
 379 struct hv_vp_assist_page {
 380         __u32 apic_assist;
 381         __u32 reserved1;
 382         __u32 vtl_entry_reason;
 383         __u32 vtl_reserved;
 384         __u64 vtl_ret_x64rax;
 385         __u64 vtl_ret_x64rcx;
 386         struct hv_nested_enlightenments_control nested_control;
 387         __u8 enlighten_vmentry;
 388         __u8 reserved2[7];
 389         __u64 current_nested_vmcs;
 390         __u8 synthetic_time_unhalted_timer_expired;
 391         __u8 reserved3[7];
 392         __u8 virtualization_fault_information[40];
 393         __u8 reserved4[8];
 394         __u8 intercept_message[256];
 395         __u8 vtl_ret_actions[256];
 396 } __packed;
 397
 398 struct hv_enlightened_vmcs {
 399         u32 revision_id;
 400         u32 abort;
 401
 402         u16 host_es_selector;
 403         u16 host_cs_selector;
 404         u16 host_ss_selector;
 405         u16 host_ds_selector;
 406         u16 host_fs_selector;
 407         u16 host_gs_selector;
 408         u16 host_tr_selector;
 409
 410         u16 padding16_1;
 411
 412         u64 host_ia32_pat;
 413         u64 host_ia32_efer;
 414
 415         u64 host_cr0;
 416         u64 host_cr3;
 417         u64 host_cr4;
 418
 419         u64 host_ia32_sysenter_esp;
 420         u64 host_ia32_sysenter_eip;
 421         u64 host_rip;
 422         u32 host_ia32_sysenter_cs;
 423
 424         u32 pin_based_vm_exec_control;
 425         u32 vm_exit_controls;
 426         u32 secondary_vm_exec_control;
 427
 428         u64 io_bitmap_a;
 429         u64 io_bitmap_b;
 430         u64 msr_bitmap;
 431
 432         u16 guest_es_selector;
 433         u16 guest_cs_selector;
 434         u16 guest_ss_selector;
 435         u16 guest_ds_selector;
 436         u16 guest_fs_selector;
 437         u16 guest_gs_selector;
 438         u16 guest_ldtr_selector;
 439         u16 guest_tr_selector;
 440
 441         u32 guest_es_limit;
 442         u32 guest_cs_limit;
 443         u32 guest_ss_limit;
 444         u32 guest_ds_limit;
 445         u32 guest_fs_limit;
 446         u32 guest_gs_limit;
 447         u32 guest_ldtr_limit;
 448         u32 guest_tr_limit;
 449         u32 guest_gdtr_limit;
 450         u32 guest_idtr_limit;
 451
 452         u32 guest_es_ar_bytes;
 453         u32 guest_cs_ar_bytes;
 454         u32 guest_ss_ar_bytes;
 455         u32 guest_ds_ar_bytes;
 456         u32 guest_fs_ar_bytes;
 457         u32 guest_gs_ar_bytes;
 458         u32 guest_ldtr_ar_bytes;
 459         u32 guest_tr_ar_bytes;
 460
 461         u64 guest_es_base;
 462         u64 guest_cs_base;
 463         u64 guest_ss_base;
 464         u64 guest_ds_base;
 465         u64 guest_fs_base;
 466         u64 guest_gs_base;
 467         u64 guest_ldtr_base;
 468         u64 guest_tr_base;
 469         u64 guest_gdtr_base;
 470         u64 guest_idtr_base;
 471
 472         u64 padding64_1[3];
 473
 474         u64 vm_exit_msr_store_addr;
 475         u64 vm_exit_msr_load_addr;
 476         u64 vm_entry_msr_load_addr;
 477
 478         u64 cr3_target_value0;
 479         u64 cr3_target_value1;
 480         u64 cr3_target_value2;
 481         u64 cr3_target_value3;
 482
 483         u32 page_fault_error_code_mask;
 484         u32 page_fault_error_code_match;
 485
 486         u32 cr3_target_count;
 487         u32 vm_exit_msr_store_count;
 488         u32 vm_exit_msr_load_count;
 489         u32 vm_entry_msr_load_count;
 490
 491         u64 tsc_offset;
 492         u64 virtual_apic_page_addr;
 493         u64 vmcs_link_pointer;
 494
 495         u64 guest_ia32_debugctl;
 496         u64 guest_ia32_pat;
 497         u64 guest_ia32_efer;
 498
 499         u64 guest_pdptr0;
 500         u64 guest_pdptr1;
 501         u64 guest_pdptr2;
 502         u64 guest_pdptr3;
 503
 504         u64 guest_pending_dbg_exceptions;
 505         u64 guest_sysenter_esp;
 506         u64 guest_sysenter_eip;
 507
 508         u32 guest_activity_state;
 509         u32 guest_sysenter_cs;
 510
 511         u64 cr0_guest_host_mask;
 512         u64 cr4_guest_host_mask;
 513         u64 cr0_read_shadow;
 514         u64 cr4_read_shadow;
 515         u64 guest_cr0;
 516         u64 guest_cr3;
 517         u64 guest_cr4;
 518         u64 guest_dr7;
 519
 520         u64 host_fs_base;
 521         u64 host_gs_base;
 522         u64 host_tr_base;
 523         u64 host_gdtr_base;
 524         u64 host_idtr_base;
 525         u64 host_rsp;
 526
 527         u64 ept_pointer;
 528
 529         u16 virtual_processor_id;
 530         u16 padding16_2[3];
 531
 532         u64 padding64_2[5];
 533         u64 guest_physical_address;
 534
 535         u32 vm_instruction_error;
 536         u32 vm_exit_reason;
 537         u32 vm_exit_intr_info;
 538         u32 vm_exit_intr_error_code;
 539         u32 idt_vectoring_info_field;
 540         u32 idt_vectoring_error_code;
 541         u32 vm_exit_instruction_len;
 542         u32 vmx_instruction_info;
 543
 544         u64 exit_qualification;
 545         u64 exit_io_instruction_ecx;
 546         u64 exit_io_instruction_esi;
 547         u64 exit_io_instruction_edi;
 548         u64 exit_io_instruction_eip;
 549
 550         u64 guest_linear_address;
 551         u64 guest_rsp;
 552         u64 guest_rflags;
 553
 554         u32 guest_interruptibility_info;
 555         u32 cpu_based_vm_exec_control;
 556         u32 exception_bitmap;
 557         u32 vm_entry_controls;
 558         u32 vm_entry_intr_info_field;
 559         u32 vm_entry_exception_error_code;
 560         u32 vm_entry_instruction_len;
 561         u32 tpr_threshold;
 562
 563         u64 guest_rip;
 564
 565         u32 hv_clean_fields;
 566         u32 padding32_1;
 567         u32 hv_synthetic_controls;
 568         struct {
 569                 u32 nested_flush_hypercall:1;
 570                 u32 msr_bitmap:1;
 571                 u32 reserved:30;
 572         }  __packed hv_enlightenments_control;
 573         u32 hv_vp_id;
 574         u32 padding32_2;
 575         u64 hv_vm_id;
 576         u64 partition_assist_page;
 577         u64 padding64_4[4];
 578         u64 guest_bndcfgs;
 579         u64 guest_ia32_perf_global_ctrl;
 580         u64 guest_ia32_s_cet;
 581         u64 guest_ssp;
 582         u64 guest_ia32_int_ssp_table_addr;
 583         u64 guest_ia32_lbr_ctl;
 584         u64 padding64_5[2];
 585         u64 xss_exit_bitmap;
 586         u64 encls_exiting_bitmap;
 587         u64 host_ia32_perf_global_ctrl;
 588         u64 tsc_multiplier;
 589         u64 host_ia32_s_cet;
 590         u64 host_ssp;
 591         u64 host_ia32_int_ssp_table_addr;
 592         u64 padding64_6;
 593 } __packed;
 594
 595 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE                     0
 596 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP                BIT(0)
 597 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP               BIT(1)
 598 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2             BIT(2)
 599 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1             BIT(3)
 600 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC             BIT(4)
 601 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT            BIT(5)
 602 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY            BIT(6)
 603 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN            BIT(7)
 604 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR                     BIT(8)
 605 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT             BIT(9)
 606 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC              BIT(10)
 607 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1               BIT(11)
 608 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2               BIT(12)
 609 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER             BIT(13)
 610 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1                BIT(14)
 611 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL    BIT(15)
 612
 613 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL                      0xFFFF
 614
 615 /*
 616  * Note, Hyper-V isn't actually stealing bit 28 from Intel, just abusing it by
 617  * pairing it with architecturally impossible exit reasons.  Bit 28 is set only
 618  * on SMI exits to a SMI transfer monitor (STM) and if and only if a MTF VM-Exit
 619  * is pending.  I.e. it will never be set by hardware for non-SMI exits (there
 620  * are only three), nor will it ever be set unless the VMM is an STM.
 621  */
 622 #define HV_VMX_SYNTHETIC_EXIT_REASON_TRAP_AFTER_FLUSH           0x10000031
 623
 624 /*
 625  * Hyper-V uses the software reserved 32 bytes in VMCB control area to expose
 626  * SVM enlightenments to guests.
 627  */
 628 struct hv_vmcb_enlightenments {
 629         struct __packed hv_enlightenments_control {
 630                 u32 nested_flush_hypercall:1;
 631                 u32 msr_bitmap:1;
 632                 u32 enlightened_npt_tlb: 1;
 633                 u32 reserved:29;
 634         } __packed hv_enlightenments_control;
 635         u32 hv_vp_id;
 636         u64 hv_vm_id;
 637         u64 partition_assist_page;
 638         u64 reserved;
 639 } __packed;
 640
 641 /*
 642  * Hyper-V uses the software reserved clean bit in VMCB.
 643  */
 644 #define HV_VMCB_NESTED_ENLIGHTENMENTS           31
 645
 646 /* Synthetic VM-Exit */
 647 #define HV_SVM_EXITCODE_ENL                     0xf0000000
 648 #define HV_SVM_ENL_EXITCODE_TRAP_AFTER_FLUSH    (1)
 649
 650 struct hv_partition_assist_pg {
 651         u32 tlb_lock_count;
 652 };
 653
 654 enum hv_interrupt_type {
 655         HV_X64_INTERRUPT_TYPE_FIXED             = 0x0000,
 656         HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY    = 0x0001,
 657         HV_X64_INTERRUPT_TYPE_SMI               = 0x0002,
 658         HV_X64_INTERRUPT_TYPE_REMOTEREAD        = 0x0003,
 659         HV_X64_INTERRUPT_TYPE_NMI               = 0x0004,
 660         HV_X64_INTERRUPT_TYPE_INIT              = 0x0005,
 661         HV_X64_INTERRUPT_TYPE_SIPI              = 0x0006,
 662         HV_X64_INTERRUPT_TYPE_EXTINT            = 0x0007,
 663         HV_X64_INTERRUPT_TYPE_LOCALINT0         = 0x0008,
 664         HV_X64_INTERRUPT_TYPE_LOCALINT1         = 0x0009,
 665         HV_X64_INTERRUPT_TYPE_MAXIMUM           = 0x000A,
 666 };
 667
 668 union hv_msi_address_register {
 669         u32 as_uint32;
 670         struct {
 671                 u32 reserved1:2;
 672                 u32 destination_mode:1;
 673                 u32 redirection_hint:1;
 674                 u32 reserved2:8;
 675                 u32 destination_id:8;
 676                 u32 msi_base:12;
 677         };
 678 } __packed;
 679
 680 union hv_msi_data_register {
 681         u32 as_uint32;
 682         struct {
 683                 u32 vector:8;
 684                 u32 delivery_mode:3;
 685                 u32 reserved1:3;
 686                 u32 level_assert:1;
 687                 u32 trigger_mode:1;
 688                 u32 reserved2:16;
 689         };
 690 } __packed;
 691
 692 /* HvRetargetDeviceInterrupt hypercall */
 693 union hv_msi_entry {
 694         u64 as_uint64;
 695         struct {
 696                 union hv_msi_address_register address;
 697                 union hv_msi_data_register data;
 698         } __packed;
 699 };
 700
 701 #include <asm-generic/hyperv-tlfs.h>
 702
 703 #endif